1b0fb8423SAlexander Graf /* 2b0fb8423SAlexander Graf * QEMU PowerPC MPC8544 global util pseudo-device 3b0fb8423SAlexander Graf * 4b0fb8423SAlexander Graf * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved. 5b0fb8423SAlexander Graf * 6b0fb8423SAlexander Graf * Author: Alexander Graf, <alex@csgraf.de> 7b0fb8423SAlexander Graf * 8b0fb8423SAlexander Graf * This is free software; you can redistribute it and/or modify 9b0fb8423SAlexander Graf * it under the terms of the GNU General Public License as published by 10b0fb8423SAlexander Graf * the Free Software Foundation; either version 2 of the License, or 11b0fb8423SAlexander Graf * (at your option) any later version. 12b0fb8423SAlexander Graf * 13b0fb8423SAlexander Graf * ***************************************************************** 14b0fb8423SAlexander Graf * 15b0fb8423SAlexander Graf * The documentation for this device is noted in the MPC8544 documentation, 16b0fb8423SAlexander Graf * file name "MPC8544ERM.pdf". You can easily find it on the web. 17b0fb8423SAlexander Graf * 18b0fb8423SAlexander Graf */ 19b0fb8423SAlexander Graf 200d75590dSPeter Maydell #include "qemu/osdep.h" 21*4771d756SPaolo Bonzini #include "qemu-common.h" 22*4771d756SPaolo Bonzini #include "cpu.h" 2383c9f4caSPaolo Bonzini #include "hw/hw.h" 249c17d615SPaolo Bonzini #include "sysemu/sysemu.h" 2583c9f4caSPaolo Bonzini #include "hw/sysbus.h" 26b0fb8423SAlexander Graf 27b0fb8423SAlexander Graf #define MPC8544_GUTS_MMIO_SIZE 0x1000 28b0fb8423SAlexander Graf #define MPC8544_GUTS_RSTCR_RESET 0x02 29b0fb8423SAlexander Graf 30b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORPLLSR 0x00 31b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORBMSR 0x04 32b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORIMPSCR 0x08 33b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR 0x0C 34b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDBGMSR 0x10 35b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR2 0x14 36b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPPORCR 0x20 37b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPIOCR 0x30 38b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPOUTDR 0x40 39b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPINDR 0x50 40b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PMUXCR 0x60 41b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DEVDISR 0x70 42b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_POWMGTCSR 0x80 43b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_MCPSUMR 0x90 44b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTRSCR 0x94 45b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PVR 0xA0 46b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SVR 0xA4 47b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTCR 0xB0 48b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_IOVSELSR 0xC0 49b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCSR 0xB20 50b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCDR 0xB24 51b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCLKDR 0xB28 52b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_CLKOCR 0xE00 53b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS1CR1 0xF04 54b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR1 0xF10 55b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR3 0xF18 56b0fb8423SAlexander Graf 5743f691e9SAndreas Färber #define TYPE_MPC8544_GUTS "mpc8544-guts" 5843f691e9SAndreas Färber #define MPC8544_GUTS(obj) OBJECT_CHECK(GutsState, (obj), TYPE_MPC8544_GUTS) 5943f691e9SAndreas Färber 60b0fb8423SAlexander Graf struct GutsState { 6143f691e9SAndreas Färber /*< private >*/ 6243f691e9SAndreas Färber SysBusDevice parent_obj; 6343f691e9SAndreas Färber /*< public >*/ 6443f691e9SAndreas Färber 651c7af35fSAvi Kivity MemoryRegion iomem; 66b0fb8423SAlexander Graf }; 67b0fb8423SAlexander Graf 68b0fb8423SAlexander Graf typedef struct GutsState GutsState; 69b0fb8423SAlexander Graf 70a8170e5eSAvi Kivity static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr, 711c7af35fSAvi Kivity unsigned size) 72b0fb8423SAlexander Graf { 73b0fb8423SAlexander Graf uint32_t value = 0; 744917cf44SAndreas Färber PowerPCCPU *cpu = POWERPC_CPU(current_cpu); 754917cf44SAndreas Färber CPUPPCState *env = &cpu->env; 76b0fb8423SAlexander Graf 77b0fb8423SAlexander Graf addr &= MPC8544_GUTS_MMIO_SIZE - 1; 78b0fb8423SAlexander Graf switch (addr) { 79b0fb8423SAlexander Graf case MPC8544_GUTS_ADDR_PVR: 80b0fb8423SAlexander Graf value = env->spr[SPR_PVR]; 81b0fb8423SAlexander Graf break; 82b0fb8423SAlexander Graf case MPC8544_GUTS_ADDR_SVR: 83b0fb8423SAlexander Graf value = env->spr[SPR_E500_SVR]; 84b0fb8423SAlexander Graf break; 85b0fb8423SAlexander Graf default: 86b0fb8423SAlexander Graf fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr); 87b0fb8423SAlexander Graf break; 88b0fb8423SAlexander Graf } 89b0fb8423SAlexander Graf 90b0fb8423SAlexander Graf return value; 91b0fb8423SAlexander Graf } 92b0fb8423SAlexander Graf 93a8170e5eSAvi Kivity static void mpc8544_guts_write(void *opaque, hwaddr addr, 941c7af35fSAvi Kivity uint64_t value, unsigned size) 95b0fb8423SAlexander Graf { 96b0fb8423SAlexander Graf addr &= MPC8544_GUTS_MMIO_SIZE - 1; 97b0fb8423SAlexander Graf 98b0fb8423SAlexander Graf switch (addr) { 99b0fb8423SAlexander Graf case MPC8544_GUTS_ADDR_RSTCR: 100b0fb8423SAlexander Graf if (value & MPC8544_GUTS_RSTCR_RESET) { 101b0fb8423SAlexander Graf qemu_system_reset_request(); 102b0fb8423SAlexander Graf } 103b0fb8423SAlexander Graf break; 104b0fb8423SAlexander Graf default: 105b0fb8423SAlexander Graf fprintf(stderr, "guts: Unknown register write: %x = %x\n", 1061c7af35fSAvi Kivity (int)addr, (unsigned)value); 107b0fb8423SAlexander Graf break; 108b0fb8423SAlexander Graf } 109b0fb8423SAlexander Graf } 110b0fb8423SAlexander Graf 1111c7af35fSAvi Kivity static const MemoryRegionOps mpc8544_guts_ops = { 1121c7af35fSAvi Kivity .read = mpc8544_guts_read, 1131c7af35fSAvi Kivity .write = mpc8544_guts_write, 1141c7af35fSAvi Kivity .endianness = DEVICE_BIG_ENDIAN, 1151c7af35fSAvi Kivity .valid = { 1161c7af35fSAvi Kivity .min_access_size = 4, 1171c7af35fSAvi Kivity .max_access_size = 4, 1181c7af35fSAvi Kivity }, 119b0fb8423SAlexander Graf }; 120b0fb8423SAlexander Graf 1217587ea5bSAndreas Färber static void mpc8544_guts_initfn(Object *obj) 122b0fb8423SAlexander Graf { 1237587ea5bSAndreas Färber SysBusDevice *d = SYS_BUS_DEVICE(obj); 1247587ea5bSAndreas Färber GutsState *s = MPC8544_GUTS(obj); 125b0fb8423SAlexander Graf 12640c5dce9SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &mpc8544_guts_ops, s, 1271f1a83f4SAndreas Färber "mpc8544.guts", MPC8544_GUTS_MMIO_SIZE); 1287587ea5bSAndreas Färber sysbus_init_mmio(d, &s->iomem); 129999e12bbSAnthony Liguori } 130999e12bbSAnthony Liguori 1318c43a6f0SAndreas Färber static const TypeInfo mpc8544_guts_info = { 13243f691e9SAndreas Färber .name = TYPE_MPC8544_GUTS, 13339bffca2SAnthony Liguori .parent = TYPE_SYS_BUS_DEVICE, 13439bffca2SAnthony Liguori .instance_size = sizeof(GutsState), 1357587ea5bSAndreas Färber .instance_init = mpc8544_guts_initfn, 136b0fb8423SAlexander Graf }; 137b0fb8423SAlexander Graf 13883f7d43aSAndreas Färber static void mpc8544_guts_register_types(void) 139b0fb8423SAlexander Graf { 14039bffca2SAnthony Liguori type_register_static(&mpc8544_guts_info); 141b0fb8423SAlexander Graf } 14283f7d43aSAndreas Färber 14383f7d43aSAndreas Färber type_init(mpc8544_guts_register_types) 144