1b0fb8423SAlexander Graf /* 2b0fb8423SAlexander Graf * QEMU PowerPC MPC8544 global util pseudo-device 3b0fb8423SAlexander Graf * 4b0fb8423SAlexander Graf * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved. 5b0fb8423SAlexander Graf * 6b0fb8423SAlexander Graf * Author: Alexander Graf, <alex@csgraf.de> 7b0fb8423SAlexander Graf * 8b0fb8423SAlexander Graf * This is free software; you can redistribute it and/or modify 9b0fb8423SAlexander Graf * it under the terms of the GNU General Public License as published by 10b0fb8423SAlexander Graf * the Free Software Foundation; either version 2 of the License, or 11b0fb8423SAlexander Graf * (at your option) any later version. 12b0fb8423SAlexander Graf * 13b0fb8423SAlexander Graf * ***************************************************************** 14b0fb8423SAlexander Graf * 15b0fb8423SAlexander Graf * The documentation for this device is noted in the MPC8544 documentation, 16b0fb8423SAlexander Graf * file name "MPC8544ERM.pdf". You can easily find it on the web. 17b0fb8423SAlexander Graf * 18b0fb8423SAlexander Graf */ 19b0fb8423SAlexander Graf 20b0fb8423SAlexander Graf #include "hw.h" 219c17d615SPaolo Bonzini #include "sysemu/sysemu.h" 22b0fb8423SAlexander Graf #include "sysbus.h" 23b0fb8423SAlexander Graf 24b0fb8423SAlexander Graf #define MPC8544_GUTS_MMIO_SIZE 0x1000 25b0fb8423SAlexander Graf #define MPC8544_GUTS_RSTCR_RESET 0x02 26b0fb8423SAlexander Graf 27b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORPLLSR 0x00 28b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORBMSR 0x04 29b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORIMPSCR 0x08 30b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR 0x0C 31b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDBGMSR 0x10 32b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR2 0x14 33b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPPORCR 0x20 34b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPIOCR 0x30 35b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPOUTDR 0x40 36b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPINDR 0x50 37b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PMUXCR 0x60 38b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DEVDISR 0x70 39b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_POWMGTCSR 0x80 40b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_MCPSUMR 0x90 41b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTRSCR 0x94 42b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PVR 0xA0 43b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SVR 0xA4 44b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTCR 0xB0 45b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_IOVSELSR 0xC0 46b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCSR 0xB20 47b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCDR 0xB24 48b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCLKDR 0xB28 49b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_CLKOCR 0xE00 50b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS1CR1 0xF04 51b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR1 0xF10 52b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR3 0xF18 53b0fb8423SAlexander Graf 54b0fb8423SAlexander Graf struct GutsState { 55b0fb8423SAlexander Graf SysBusDevice busdev; 561c7af35fSAvi Kivity MemoryRegion iomem; 57b0fb8423SAlexander Graf }; 58b0fb8423SAlexander Graf 59b0fb8423SAlexander Graf typedef struct GutsState GutsState; 60b0fb8423SAlexander Graf 61a8170e5eSAvi Kivity static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr, 621c7af35fSAvi Kivity unsigned size) 63b0fb8423SAlexander Graf { 64b0fb8423SAlexander Graf uint32_t value = 0; 65e2684c0bSAndreas Färber CPUPPCState *env = cpu_single_env; 66b0fb8423SAlexander Graf 67b0fb8423SAlexander Graf addr &= MPC8544_GUTS_MMIO_SIZE - 1; 68b0fb8423SAlexander Graf switch (addr) { 69b0fb8423SAlexander Graf case MPC8544_GUTS_ADDR_PVR: 70b0fb8423SAlexander Graf value = env->spr[SPR_PVR]; 71b0fb8423SAlexander Graf break; 72b0fb8423SAlexander Graf case MPC8544_GUTS_ADDR_SVR: 73b0fb8423SAlexander Graf value = env->spr[SPR_E500_SVR]; 74b0fb8423SAlexander Graf break; 75b0fb8423SAlexander Graf default: 76b0fb8423SAlexander Graf fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr); 77b0fb8423SAlexander Graf break; 78b0fb8423SAlexander Graf } 79b0fb8423SAlexander Graf 80b0fb8423SAlexander Graf return value; 81b0fb8423SAlexander Graf } 82b0fb8423SAlexander Graf 83a8170e5eSAvi Kivity static void mpc8544_guts_write(void *opaque, hwaddr addr, 841c7af35fSAvi Kivity uint64_t value, unsigned size) 85b0fb8423SAlexander Graf { 86b0fb8423SAlexander Graf addr &= MPC8544_GUTS_MMIO_SIZE - 1; 87b0fb8423SAlexander Graf 88b0fb8423SAlexander Graf switch (addr) { 89b0fb8423SAlexander Graf case MPC8544_GUTS_ADDR_RSTCR: 90b0fb8423SAlexander Graf if (value & MPC8544_GUTS_RSTCR_RESET) { 91b0fb8423SAlexander Graf qemu_system_reset_request(); 92b0fb8423SAlexander Graf } 93b0fb8423SAlexander Graf break; 94b0fb8423SAlexander Graf default: 95b0fb8423SAlexander Graf fprintf(stderr, "guts: Unknown register write: %x = %x\n", 961c7af35fSAvi Kivity (int)addr, (unsigned)value); 97b0fb8423SAlexander Graf break; 98b0fb8423SAlexander Graf } 99b0fb8423SAlexander Graf } 100b0fb8423SAlexander Graf 1011c7af35fSAvi Kivity static const MemoryRegionOps mpc8544_guts_ops = { 1021c7af35fSAvi Kivity .read = mpc8544_guts_read, 1031c7af35fSAvi Kivity .write = mpc8544_guts_write, 1041c7af35fSAvi Kivity .endianness = DEVICE_BIG_ENDIAN, 1051c7af35fSAvi Kivity .valid = { 1061c7af35fSAvi Kivity .min_access_size = 4, 1071c7af35fSAvi Kivity .max_access_size = 4, 1081c7af35fSAvi Kivity }, 109b0fb8423SAlexander Graf }; 110b0fb8423SAlexander Graf 111b0fb8423SAlexander Graf static int mpc8544_guts_initfn(SysBusDevice *dev) 112b0fb8423SAlexander Graf { 113b0fb8423SAlexander Graf GutsState *s; 114b0fb8423SAlexander Graf 115*1356b98dSAndreas Färber s = FROM_SYSBUS(GutsState, SYS_BUS_DEVICE(dev)); 116b0fb8423SAlexander Graf 1171c7af35fSAvi Kivity memory_region_init_io(&s->iomem, &mpc8544_guts_ops, s, 1181c7af35fSAvi Kivity "mpc6544.guts", MPC8544_GUTS_MMIO_SIZE); 119750ecd44SAvi Kivity sysbus_init_mmio(dev, &s->iomem); 120b0fb8423SAlexander Graf 121b0fb8423SAlexander Graf return 0; 122b0fb8423SAlexander Graf } 123b0fb8423SAlexander Graf 124999e12bbSAnthony Liguori static void mpc8544_guts_class_init(ObjectClass *klass, void *data) 125999e12bbSAnthony Liguori { 126999e12bbSAnthony Liguori SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 127999e12bbSAnthony Liguori 128999e12bbSAnthony Liguori k->init = mpc8544_guts_initfn; 129999e12bbSAnthony Liguori } 130999e12bbSAnthony Liguori 1318c43a6f0SAndreas Färber static const TypeInfo mpc8544_guts_info = { 132999e12bbSAnthony Liguori .name = "mpc8544-guts", 13339bffca2SAnthony Liguori .parent = TYPE_SYS_BUS_DEVICE, 13439bffca2SAnthony Liguori .instance_size = sizeof(GutsState), 135999e12bbSAnthony Liguori .class_init = mpc8544_guts_class_init, 136b0fb8423SAlexander Graf }; 137b0fb8423SAlexander Graf 13883f7d43aSAndreas Färber static void mpc8544_guts_register_types(void) 139b0fb8423SAlexander Graf { 14039bffca2SAnthony Liguori type_register_static(&mpc8544_guts_info); 141b0fb8423SAlexander Graf } 14283f7d43aSAndreas Färber 14383f7d43aSAndreas Färber type_init(mpc8544_guts_register_types) 144