xref: /qemu/hw/ppc/mpc8544_guts.c (revision 0d75590d919454be322f21d55494b8937651fc86)
1b0fb8423SAlexander Graf /*
2b0fb8423SAlexander Graf  * QEMU PowerPC MPC8544 global util pseudo-device
3b0fb8423SAlexander Graf  *
4b0fb8423SAlexander Graf  * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
5b0fb8423SAlexander Graf  *
6b0fb8423SAlexander Graf  * Author: Alexander Graf, <alex@csgraf.de>
7b0fb8423SAlexander Graf  *
8b0fb8423SAlexander Graf  * This is free software; you can redistribute it and/or modify
9b0fb8423SAlexander Graf  * it under the terms of  the GNU General  Public License as published by
10b0fb8423SAlexander Graf  * the Free Software Foundation;  either version 2 of the  License, or
11b0fb8423SAlexander Graf  * (at your option) any later version.
12b0fb8423SAlexander Graf  *
13b0fb8423SAlexander Graf  * *****************************************************************
14b0fb8423SAlexander Graf  *
15b0fb8423SAlexander Graf  * The documentation for this device is noted in the MPC8544 documentation,
16b0fb8423SAlexander Graf  * file name "MPC8544ERM.pdf". You can easily find it on the web.
17b0fb8423SAlexander Graf  *
18b0fb8423SAlexander Graf  */
19b0fb8423SAlexander Graf 
20*0d75590dSPeter Maydell #include "qemu/osdep.h"
2183c9f4caSPaolo Bonzini #include "hw/hw.h"
229c17d615SPaolo Bonzini #include "sysemu/sysemu.h"
2383c9f4caSPaolo Bonzini #include "hw/sysbus.h"
24b0fb8423SAlexander Graf 
25b0fb8423SAlexander Graf #define MPC8544_GUTS_MMIO_SIZE        0x1000
26b0fb8423SAlexander Graf #define MPC8544_GUTS_RSTCR_RESET      0x02
27b0fb8423SAlexander Graf 
28b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORPLLSR    0x00
29b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORBMSR     0x04
30b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORIMPSCR   0x08
31b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR    0x0C
32b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDBGMSR   0x10
33b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PORDEVSR2   0x14
34b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPPORCR     0x20
35b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPIOCR      0x30
36b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPOUTDR     0x40
37b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_GPINDR      0x50
38b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PMUXCR      0x60
39b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DEVDISR     0x70
40b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_POWMGTCSR   0x80
41b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_MCPSUMR     0x90
42b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTRSCR     0x94
43b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_PVR         0xA0
44b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SVR         0xA4
45b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_RSTCR       0xB0
46b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_IOVSELSR    0xC0
47b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCSR      0xB20
48b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCDR      0xB24
49b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_DDRCLKDR    0xB28
50b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_CLKOCR      0xE00
51b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS1CR1    0xF04
52b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR1    0xF10
53b0fb8423SAlexander Graf #define MPC8544_GUTS_ADDR_SRDS2CR3    0xF18
54b0fb8423SAlexander Graf 
5543f691e9SAndreas Färber #define TYPE_MPC8544_GUTS "mpc8544-guts"
5643f691e9SAndreas Färber #define MPC8544_GUTS(obj) OBJECT_CHECK(GutsState, (obj), TYPE_MPC8544_GUTS)
5743f691e9SAndreas Färber 
58b0fb8423SAlexander Graf struct GutsState {
5943f691e9SAndreas Färber     /*< private >*/
6043f691e9SAndreas Färber     SysBusDevice parent_obj;
6143f691e9SAndreas Färber     /*< public >*/
6243f691e9SAndreas Färber 
631c7af35fSAvi Kivity     MemoryRegion iomem;
64b0fb8423SAlexander Graf };
65b0fb8423SAlexander Graf 
66b0fb8423SAlexander Graf typedef struct GutsState GutsState;
67b0fb8423SAlexander Graf 
68a8170e5eSAvi Kivity static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
691c7af35fSAvi Kivity                                   unsigned size)
70b0fb8423SAlexander Graf {
71b0fb8423SAlexander Graf     uint32_t value = 0;
724917cf44SAndreas Färber     PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
734917cf44SAndreas Färber     CPUPPCState *env = &cpu->env;
74b0fb8423SAlexander Graf 
75b0fb8423SAlexander Graf     addr &= MPC8544_GUTS_MMIO_SIZE - 1;
76b0fb8423SAlexander Graf     switch (addr) {
77b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_PVR:
78b0fb8423SAlexander Graf         value = env->spr[SPR_PVR];
79b0fb8423SAlexander Graf         break;
80b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_SVR:
81b0fb8423SAlexander Graf         value = env->spr[SPR_E500_SVR];
82b0fb8423SAlexander Graf         break;
83b0fb8423SAlexander Graf     default:
84b0fb8423SAlexander Graf         fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr);
85b0fb8423SAlexander Graf         break;
86b0fb8423SAlexander Graf     }
87b0fb8423SAlexander Graf 
88b0fb8423SAlexander Graf     return value;
89b0fb8423SAlexander Graf }
90b0fb8423SAlexander Graf 
91a8170e5eSAvi Kivity static void mpc8544_guts_write(void *opaque, hwaddr addr,
921c7af35fSAvi Kivity                                uint64_t value, unsigned size)
93b0fb8423SAlexander Graf {
94b0fb8423SAlexander Graf     addr &= MPC8544_GUTS_MMIO_SIZE - 1;
95b0fb8423SAlexander Graf 
96b0fb8423SAlexander Graf     switch (addr) {
97b0fb8423SAlexander Graf     case MPC8544_GUTS_ADDR_RSTCR:
98b0fb8423SAlexander Graf         if (value & MPC8544_GUTS_RSTCR_RESET) {
99b0fb8423SAlexander Graf             qemu_system_reset_request();
100b0fb8423SAlexander Graf         }
101b0fb8423SAlexander Graf         break;
102b0fb8423SAlexander Graf     default:
103b0fb8423SAlexander Graf         fprintf(stderr, "guts: Unknown register write: %x = %x\n",
1041c7af35fSAvi Kivity                 (int)addr, (unsigned)value);
105b0fb8423SAlexander Graf         break;
106b0fb8423SAlexander Graf     }
107b0fb8423SAlexander Graf }
108b0fb8423SAlexander Graf 
1091c7af35fSAvi Kivity static const MemoryRegionOps mpc8544_guts_ops = {
1101c7af35fSAvi Kivity     .read = mpc8544_guts_read,
1111c7af35fSAvi Kivity     .write = mpc8544_guts_write,
1121c7af35fSAvi Kivity     .endianness = DEVICE_BIG_ENDIAN,
1131c7af35fSAvi Kivity     .valid = {
1141c7af35fSAvi Kivity         .min_access_size = 4,
1151c7af35fSAvi Kivity         .max_access_size = 4,
1161c7af35fSAvi Kivity     },
117b0fb8423SAlexander Graf };
118b0fb8423SAlexander Graf 
1197587ea5bSAndreas Färber static void mpc8544_guts_initfn(Object *obj)
120b0fb8423SAlexander Graf {
1217587ea5bSAndreas Färber     SysBusDevice *d = SYS_BUS_DEVICE(obj);
1227587ea5bSAndreas Färber     GutsState *s = MPC8544_GUTS(obj);
123b0fb8423SAlexander Graf 
12440c5dce9SPaolo Bonzini     memory_region_init_io(&s->iomem, OBJECT(s), &mpc8544_guts_ops, s,
1251f1a83f4SAndreas Färber                           "mpc8544.guts", MPC8544_GUTS_MMIO_SIZE);
1267587ea5bSAndreas Färber     sysbus_init_mmio(d, &s->iomem);
127999e12bbSAnthony Liguori }
128999e12bbSAnthony Liguori 
1298c43a6f0SAndreas Färber static const TypeInfo mpc8544_guts_info = {
13043f691e9SAndreas Färber     .name          = TYPE_MPC8544_GUTS,
13139bffca2SAnthony Liguori     .parent        = TYPE_SYS_BUS_DEVICE,
13239bffca2SAnthony Liguori     .instance_size = sizeof(GutsState),
1337587ea5bSAndreas Färber     .instance_init = mpc8544_guts_initfn,
134b0fb8423SAlexander Graf };
135b0fb8423SAlexander Graf 
13683f7d43aSAndreas Färber static void mpc8544_guts_register_types(void)
137b0fb8423SAlexander Graf {
13839bffca2SAnthony Liguori     type_register_static(&mpc8544_guts_info);
139b0fb8423SAlexander Graf }
14083f7d43aSAndreas Färber 
14183f7d43aSAndreas Färber type_init(mpc8544_guts_register_types)
142