1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "mac.h" 34 #include "hw/boards.h" 35 #include "hw/input/adb.h" 36 #include "sysemu/sysemu.h" 37 #include "net/net.h" 38 #include "hw/isa/isa.h" 39 #include "hw/pci/pci.h" 40 #include "hw/pci/pci_host.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 52 #define MAX_IDE_BUS 2 53 #define CFG_ADDR 0xf0000510 54 #define TBFREQ 16600000UL 55 #define CLOCKFREQ 266000000UL 56 #define BUSFREQ 66000000UL 57 58 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 59 60 #define GRACKLE_BASE 0xfec00000 61 #define PROM_BASE 0xffc00000 62 #define PROM_SIZE (4 * MiB) 63 64 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 65 Error **errp) 66 { 67 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 68 } 69 70 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 71 { 72 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 73 } 74 75 static void ppc_heathrow_reset(void *opaque) 76 { 77 PowerPCCPU *cpu = opaque; 78 79 cpu_reset(CPU(cpu)); 80 } 81 82 static void ppc_heathrow_init(MachineState *machine) 83 { 84 const char *bios_name = machine->firmware ?: PROM_FILENAME; 85 PowerPCCPU *cpu = NULL; 86 CPUPPCState *env = NULL; 87 char *filename; 88 int i, bios_size = -1; 89 MemoryRegion *bios = g_new(MemoryRegion, 1); 90 uint64_t bios_addr; 91 uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0; 92 int32_t kernel_size = 0, initrd_size = 0; 93 PCIBus *pci_bus; 94 Object *macio; 95 MACIOIDEState *macio_ide; 96 SysBusDevice *s; 97 DeviceState *dev, *pic_dev, *grackle_dev; 98 BusState *adb_bus; 99 uint16_t ppc_boot_device; 100 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 101 void *fw_cfg; 102 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; 103 104 /* init CPUs */ 105 for (i = 0; i < machine->smp.cpus; i++) { 106 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 107 env = &cpu->env; 108 109 /* Set time-base frequency to 16.6 Mhz */ 110 cpu_ppc_tb_init(env, TBFREQ); 111 qemu_register_reset(ppc_heathrow_reset, cpu); 112 } 113 114 /* allocate RAM */ 115 if (machine->ram_size > 2047 * MiB) { 116 error_report("Too much memory for this machine: %" PRId64 " MB, " 117 "maximum 2047 MB", machine->ram_size / MiB); 118 exit(1); 119 } 120 121 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 122 123 /* allocate and load firmware ROM */ 124 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, 125 &error_fatal); 126 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 127 128 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 129 if (filename) { 130 /* Load OpenBIOS (ELF) */ 131 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, 132 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 133 /* Unfortunately, load_elf sign-extends reading elf32 */ 134 bios_addr = (uint32_t)bios_addr; 135 136 if (bios_size <= 0) { 137 /* or if could not load ELF try loading a binary ROM image */ 138 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 139 bios_addr = PROM_BASE; 140 } 141 g_free(filename); 142 } 143 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { 144 error_report("could not load PowerPC bios '%s'", bios_name); 145 exit(1); 146 } 147 148 if (machine->kernel_filename) { 149 int bswap_needed = 0; 150 151 #ifdef BSWAP_NEEDED 152 bswap_needed = 1; 153 #endif 154 kernel_base = KERNEL_LOAD_ADDR; 155 kernel_size = load_elf(machine->kernel_filename, NULL, 156 translate_kernel_address, NULL, NULL, NULL, 157 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 158 if (kernel_size < 0) 159 kernel_size = load_aout(machine->kernel_filename, kernel_base, 160 machine->ram_size - kernel_base, 161 bswap_needed, TARGET_PAGE_SIZE); 162 if (kernel_size < 0) 163 kernel_size = load_image_targphys(machine->kernel_filename, 164 kernel_base, 165 machine->ram_size - kernel_base); 166 if (kernel_size < 0) { 167 error_report("could not load kernel '%s'", 168 machine->kernel_filename); 169 exit(1); 170 } 171 /* load initrd */ 172 if (machine->initrd_filename) { 173 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 174 KERNEL_GAP); 175 initrd_size = load_image_targphys(machine->initrd_filename, 176 initrd_base, 177 machine->ram_size - initrd_base); 178 if (initrd_size < 0) { 179 error_report("could not load initial ram disk '%s'", 180 machine->initrd_filename); 181 exit(1); 182 } 183 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 184 } else { 185 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 186 } 187 ppc_boot_device = 'm'; 188 } else { 189 ppc_boot_device = '\0'; 190 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 191 /* 192 * TOFIX: for now, the second IDE channel is not properly 193 * used by OHW. The Mac floppy disk are not emulated. 194 * For now, OHW cannot boot from the network. 195 */ 196 #if 0 197 if (machine->boot_config.order[i] >= 'a' && 198 machine->boot_config.order[i] <= 'f') { 199 ppc_boot_device = machine->boot_config.order[i]; 200 break; 201 } 202 #else 203 if (machine->boot_config.order[i] >= 'c' && 204 machine->boot_config.order[i] <= 'd') { 205 ppc_boot_device = machine->boot_config.order[i]; 206 break; 207 } 208 #endif 209 } 210 if (ppc_boot_device == '\0') { 211 error_report("No valid boot device for G3 Beige machine"); 212 exit(1); 213 } 214 } 215 216 /* Grackle PCI host bridge */ 217 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 218 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000); 219 s = SYS_BUS_DEVICE(grackle_dev); 220 sysbus_realize_and_unref(s, &error_fatal); 221 222 sysbus_mmio_map(s, 0, GRACKLE_BASE); 223 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 224 /* PCI hole */ 225 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 226 sysbus_mmio_get_region(s, 2)); 227 /* Register 2 MB of ISA IO space */ 228 memory_region_add_subregion(get_system_memory(), 0xfe000000, 229 sysbus_mmio_get_region(s, 3)); 230 231 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus; 232 233 /* MacIO */ 234 macio = OBJECT(pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO)); 235 qdev_prop_set_uint64(DEVICE(macio), "frequency", tbfreq); 236 237 dev = DEVICE(object_resolve_path_component(macio, "escc")); 238 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 239 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 240 241 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); 242 243 pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); 244 for (i = 0; i < 4; i++) { 245 qdev_connect_gpio_out(grackle_dev, i, 246 qdev_get_gpio_in(pic_dev, 0x15 + i)); 247 } 248 249 /* Connect the heathrow PIC outputs to the 6xx bus */ 250 for (i = 0; i < machine->smp.cpus; i++) { 251 switch (PPC_INPUT(env)) { 252 case PPC_FLAGS_INPUT_6xx: 253 /* XXX: we register only 1 output pin for heathrow PIC */ 254 qdev_connect_gpio_out(pic_dev, 0, 255 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); 256 break; 257 default: 258 error_report("Bus model not supported on OldWorld Mac machine"); 259 exit(1); 260 } 261 } 262 263 pci_vga_init(pci_bus); 264 265 for (i = 0; i < nb_nics; i++) { 266 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 267 } 268 269 /* MacIO IDE */ 270 ide_drive_get(hd, ARRAY_SIZE(hd)); 271 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); 272 macio_ide_init_drives(macio_ide, hd); 273 274 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); 275 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 276 277 /* MacIO CUDA/ADB */ 278 dev = DEVICE(object_resolve_path_component(macio, "cuda")); 279 adb_bus = qdev_get_child_bus(dev, "adb.0"); 280 dev = qdev_new(TYPE_ADB_KEYBOARD); 281 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 282 dev = qdev_new(TYPE_ADB_MOUSE); 283 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 284 285 if (machine_usb(machine)) { 286 pci_create_simple(pci_bus, -1, "pci-ohci"); 287 } 288 289 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 290 graphic_depth = 15; 291 292 /* No PCI init: the BIOS will do it */ 293 294 dev = qdev_new(TYPE_FW_CFG_MEM); 295 fw_cfg = FW_CFG(dev); 296 qdev_prop_set_uint32(dev, "data_width", 1); 297 qdev_prop_set_bit(dev, "dma_enabled", false); 298 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 299 OBJECT(fw_cfg)); 300 s = SYS_BUS_DEVICE(dev); 301 sysbus_realize_and_unref(s, &error_fatal); 302 sysbus_mmio_map(s, 0, CFG_ADDR); 303 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 304 305 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 306 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 307 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 308 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 309 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 310 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 311 if (machine->kernel_cmdline) { 312 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 313 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 314 machine->kernel_cmdline); 315 } else { 316 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 317 } 318 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 319 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 320 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 321 322 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 323 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 324 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 325 326 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 327 if (kvm_enabled()) { 328 uint8_t *hypercall; 329 330 hypercall = g_malloc(16); 331 kvmppc_get_hypercall(env, hypercall, 16); 332 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 333 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 334 } 335 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 336 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 337 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 338 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 339 340 /* MacOS NDRV VGA driver */ 341 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 342 if (filename) { 343 gchar *ndrv_file; 344 gsize ndrv_size; 345 346 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 347 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 348 } 349 g_free(filename); 350 } 351 352 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 353 } 354 355 /* 356 * Implementation of an interface to adjust firmware path 357 * for the bootindex property handling. 358 */ 359 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 360 DeviceState *dev) 361 { 362 PCIDevice *pci; 363 MACIOIDEState *macio_ide; 364 365 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 366 pci = PCI_DEVICE(dev); 367 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 368 } 369 370 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 371 macio_ide = MACIO_IDE(dev); 372 return g_strdup_printf("ata-3@%x", macio_ide->addr); 373 } 374 375 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 376 return g_strdup("disk"); 377 } 378 379 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 380 return g_strdup("cdrom"); 381 } 382 383 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 384 return g_strdup("disk"); 385 } 386 387 return NULL; 388 } 389 390 static int heathrow_kvm_type(MachineState *machine, const char *arg) 391 { 392 /* Always force PR KVM */ 393 return 2; 394 } 395 396 static void heathrow_class_init(ObjectClass *oc, void *data) 397 { 398 MachineClass *mc = MACHINE_CLASS(oc); 399 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 400 401 mc->desc = "Heathrow based PowerMAC"; 402 mc->init = ppc_heathrow_init; 403 mc->block_default_type = IF_IDE; 404 /* SMP is not supported currently */ 405 mc->max_cpus = 1; 406 #ifndef TARGET_PPC64 407 mc->is_default = true; 408 #endif 409 /* TOFIX "cad" when Mac floppy is implemented */ 410 mc->default_boot_order = "cd"; 411 mc->kvm_type = heathrow_kvm_type; 412 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 413 mc->default_display = "std"; 414 mc->ignore_boot_device_suffixes = true; 415 mc->default_ram_id = "ppc_heathrow.ram"; 416 fwc->get_dev_path = heathrow_fw_dev_path; 417 } 418 419 static const TypeInfo ppc_heathrow_machine_info = { 420 .name = MACHINE_TYPE_NAME("g3beige"), 421 .parent = TYPE_MACHINE, 422 .class_init = heathrow_class_init, 423 .interfaces = (InterfaceInfo[]) { 424 { TYPE_FW_PATH_PROVIDER }, 425 { } 426 }, 427 }; 428 429 static void ppc_heathrow_register_types(void) 430 { 431 type_register_static(&ppc_heathrow_machine_info); 432 } 433 434 type_init(ppc_heathrow_register_types); 435