1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "hw/ppc/ppc.h" 30 #include "mac.h" 31 #include "hw/input/adb.h" 32 #include "hw/timer/m48t59.h" 33 #include "sysemu/sysemu.h" 34 #include "net/net.h" 35 #include "hw/isa/isa.h" 36 #include "hw/pci/pci.h" 37 #include "hw/pci/pci_host.h" 38 #include "hw/boards.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/char/escc.h" 41 #include "hw/misc/macio/macio.h" 42 #include "hw/ide.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "qemu/error-report.h" 46 #include "sysemu/kvm.h" 47 #include "kvm_ppc.h" 48 #include "exec/address-spaces.h" 49 #include "qemu/cutils.h" 50 51 #define MAX_IDE_BUS 2 52 #define CFG_ADDR 0xf0000510 53 #define TBFREQ 16600000UL 54 #define CLOCKFREQ 266000000UL 55 #define BUSFREQ 66000000UL 56 57 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 58 59 #define GRACKLE_BASE 0xfec00000 60 61 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 62 Error **errp) 63 { 64 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 65 } 66 67 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 68 { 69 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 70 } 71 72 static void ppc_heathrow_reset(void *opaque) 73 { 74 PowerPCCPU *cpu = opaque; 75 76 cpu_reset(CPU(cpu)); 77 } 78 79 static void ppc_heathrow_init(MachineState *machine) 80 { 81 ram_addr_t ram_size = machine->ram_size; 82 const char *kernel_filename = machine->kernel_filename; 83 const char *kernel_cmdline = machine->kernel_cmdline; 84 const char *initrd_filename = machine->initrd_filename; 85 const char *boot_device = machine->boot_order; 86 MemoryRegion *sysmem = get_system_memory(); 87 PowerPCCPU *cpu = NULL; 88 CPUPPCState *env = NULL; 89 char *filename; 90 qemu_irq *pic; 91 int linux_boot, i; 92 MemoryRegion *ram = g_new(MemoryRegion, 1); 93 MemoryRegion *bios = g_new(MemoryRegion, 1); 94 MemoryRegion *isa = g_new(MemoryRegion, 1); 95 uint32_t kernel_base, initrd_base, cmdline_base = 0; 96 int32_t kernel_size, initrd_size; 97 PCIBus *pci_bus; 98 OldWorldMacIOState *macio; 99 MACIOIDEState *macio_ide; 100 SysBusDevice *s; 101 DeviceState *dev, *pic_dev; 102 BusState *adb_bus; 103 int bios_size, ndrv_size; 104 uint8_t *ndrv_file; 105 uint16_t ppc_boot_device; 106 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 107 void *fw_cfg; 108 uint64_t tbfreq; 109 110 linux_boot = (kernel_filename != NULL); 111 112 /* init CPUs */ 113 for (i = 0; i < smp_cpus; i++) { 114 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 115 env = &cpu->env; 116 117 /* Set time-base frequency to 16.6 Mhz */ 118 cpu_ppc_tb_init(env, TBFREQ); 119 qemu_register_reset(ppc_heathrow_reset, cpu); 120 } 121 122 /* allocate RAM */ 123 if (ram_size > (2047 << 20)) { 124 fprintf(stderr, 125 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", 126 ((unsigned int)ram_size / (1 << 20))); 127 exit(1); 128 } 129 130 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", 131 ram_size); 132 memory_region_add_subregion(sysmem, 0, ram); 133 134 /* allocate and load BIOS */ 135 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 136 &error_fatal); 137 138 if (bios_name == NULL) 139 bios_name = PROM_FILENAME; 140 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 141 memory_region_set_readonly(bios, true); 142 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 143 144 /* Load OpenBIOS (ELF) */ 145 if (filename) { 146 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 147 1, PPC_ELF_MACHINE, 0, 0); 148 g_free(filename); 149 } else { 150 bios_size = -1; 151 } 152 if (bios_size < 0 || bios_size > BIOS_SIZE) { 153 error_report("could not load PowerPC bios '%s'", bios_name); 154 exit(1); 155 } 156 157 if (linux_boot) { 158 uint64_t lowaddr = 0; 159 int bswap_needed; 160 161 #ifdef BSWAP_NEEDED 162 bswap_needed = 1; 163 #else 164 bswap_needed = 0; 165 #endif 166 kernel_base = KERNEL_LOAD_ADDR; 167 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 168 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 169 0, 0); 170 if (kernel_size < 0) 171 kernel_size = load_aout(kernel_filename, kernel_base, 172 ram_size - kernel_base, bswap_needed, 173 TARGET_PAGE_SIZE); 174 if (kernel_size < 0) 175 kernel_size = load_image_targphys(kernel_filename, 176 kernel_base, 177 ram_size - kernel_base); 178 if (kernel_size < 0) { 179 error_report("could not load kernel '%s'", kernel_filename); 180 exit(1); 181 } 182 /* load initrd */ 183 if (initrd_filename) { 184 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 185 initrd_size = load_image_targphys(initrd_filename, initrd_base, 186 ram_size - initrd_base); 187 if (initrd_size < 0) { 188 error_report("could not load initial ram disk '%s'", 189 initrd_filename); 190 exit(1); 191 } 192 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 193 } else { 194 initrd_base = 0; 195 initrd_size = 0; 196 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 197 } 198 ppc_boot_device = 'm'; 199 } else { 200 kernel_base = 0; 201 kernel_size = 0; 202 initrd_base = 0; 203 initrd_size = 0; 204 ppc_boot_device = '\0'; 205 for (i = 0; boot_device[i] != '\0'; i++) { 206 /* TOFIX: for now, the second IDE channel is not properly 207 * used by OHW. The Mac floppy disk are not emulated. 208 * For now, OHW cannot boot from the network. 209 */ 210 #if 0 211 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 212 ppc_boot_device = boot_device[i]; 213 break; 214 } 215 #else 216 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 217 ppc_boot_device = boot_device[i]; 218 break; 219 } 220 #endif 221 } 222 if (ppc_boot_device == '\0') { 223 error_report("No valid boot device for G3 Beige machine"); 224 exit(1); 225 } 226 } 227 228 /* Register 2 MB of ISA IO space */ 229 memory_region_init_alias(isa, NULL, "isa_mmio", 230 get_system_io(), 0, 0x00200000); 231 memory_region_add_subregion(sysmem, 0xfe000000, isa); 232 233 /* XXX: we register only 1 output pin for heathrow PIC */ 234 pic_dev = qdev_create(NULL, TYPE_HEATHROW); 235 qdev_init_nofail(pic_dev); 236 237 /* Connect the heathrow PIC outputs to the 6xx bus */ 238 for (i = 0; i < smp_cpus; i++) { 239 switch (PPC_INPUT(env)) { 240 case PPC_FLAGS_INPUT_6xx: 241 qdev_connect_gpio_out(pic_dev, 0, 242 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); 243 break; 244 default: 245 error_report("Bus model not supported on OldWorld Mac machine"); 246 exit(1); 247 } 248 } 249 250 pic = g_new0(qemu_irq, HEATHROW_NUM_IRQS); 251 for (i = 0; i < HEATHROW_NUM_IRQS; i++) { 252 pic[i] = qdev_get_gpio_in(pic_dev, i); 253 } 254 255 /* Timebase Frequency */ 256 if (kvm_enabled()) { 257 tbfreq = kvmppc_get_tbfreq(); 258 } else { 259 tbfreq = TBFREQ; 260 } 261 262 /* init basic PC hardware */ 263 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 264 error_report("Only 6xx bus is supported on heathrow machine"); 265 exit(1); 266 } 267 268 /* Grackle PCI host bridge */ 269 dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE); 270 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 271 &error_abort); 272 qdev_init_nofail(dev); 273 s = SYS_BUS_DEVICE(dev); 274 sysbus_mmio_map(s, 0, GRACKLE_BASE); 275 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 276 /* PCI hole */ 277 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 278 sysbus_mmio_get_region(s, 2)); 279 280 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 281 282 pci_vga_init(pci_bus); 283 284 for (i = 0; i < nb_nics; i++) { 285 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 286 } 287 288 ide_drive_get(hd, ARRAY_SIZE(hd)); 289 290 /* MacIO */ 291 macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO)); 292 dev = DEVICE(macio); 293 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ 294 qdev_connect_gpio_out(dev, 1, pic[0x10]); /* ESCC-B */ 295 qdev_connect_gpio_out(dev, 2, pic[0x0F]); /* ESCC-A */ 296 qdev_connect_gpio_out(dev, 3, pic[0x0D]); /* IDE-0 */ 297 qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE-0 DMA */ 298 qdev_connect_gpio_out(dev, 5, pic[0x0E]); /* IDE-1 */ 299 qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE-1 DMA */ 300 qdev_prop_set_uint64(dev, "frequency", tbfreq); 301 object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", 302 &error_abort); 303 qdev_init_nofail(dev); 304 305 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 306 "ide[0]")); 307 macio_ide_init_drives(macio_ide, hd); 308 309 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 310 "ide[1]")); 311 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 312 313 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 314 adb_bus = qdev_get_child_bus(dev, "adb.0"); 315 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 316 qdev_init_nofail(dev); 317 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 318 qdev_init_nofail(dev); 319 320 if (machine_usb(machine)) { 321 pci_create_simple(pci_bus, -1, "pci-ohci"); 322 } 323 324 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 325 graphic_depth = 15; 326 327 /* No PCI init: the BIOS will do it */ 328 329 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 330 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 331 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 332 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 333 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 334 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 335 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 336 if (kernel_cmdline) { 337 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 338 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 339 } else { 340 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 341 } 342 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 343 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 344 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 345 346 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 347 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 348 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 349 350 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 351 if (kvm_enabled()) { 352 #ifdef CONFIG_KVM 353 uint8_t *hypercall; 354 355 hypercall = g_malloc(16); 356 kvmppc_get_hypercall(env, hypercall, 16); 357 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 358 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 359 #endif 360 } 361 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 362 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 363 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 364 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 365 366 /* MacOS NDRV VGA driver */ 367 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 368 if (filename) { 369 ndrv_size = get_image_size(filename); 370 if (ndrv_size != -1) { 371 ndrv_file = g_malloc(ndrv_size); 372 ndrv_size = load_image(filename, ndrv_file); 373 374 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 375 } 376 g_free(filename); 377 } 378 379 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 380 } 381 382 static int heathrow_kvm_type(const char *arg) 383 { 384 /* Always force PR KVM */ 385 return 2; 386 } 387 388 static void heathrow_class_init(ObjectClass *oc, void *data) 389 { 390 MachineClass *mc = MACHINE_CLASS(oc); 391 392 mc->desc = "Heathrow based PowerMAC"; 393 mc->init = ppc_heathrow_init; 394 mc->block_default_type = IF_IDE; 395 mc->max_cpus = MAX_CPUS; 396 #ifndef TARGET_PPC64 397 mc->is_default = 1; 398 #endif 399 /* TOFIX "cad" when Mac floppy is implemented */ 400 mc->default_boot_order = "cd"; 401 mc->kvm_type = heathrow_kvm_type; 402 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 403 } 404 405 static const TypeInfo ppc_heathrow_machine_info = { 406 .name = MACHINE_TYPE_NAME("g3beige"), 407 .parent = TYPE_MACHINE, 408 .class_init = heathrow_class_init 409 }; 410 411 static void ppc_heathrow_register_types(void) 412 { 413 type_register_static(&ppc_heathrow_machine_info); 414 } 415 416 type_init(ppc_heathrow_register_types); 417