1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "mac.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 #include "exec/address-spaces.h" 52 53 #define MAX_IDE_BUS 2 54 #define CFG_ADDR 0xf0000510 55 #define TBFREQ 16600000UL 56 #define CLOCKFREQ 266000000UL 57 #define BUSFREQ 66000000UL 58 59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 60 61 #define GRACKLE_BASE 0xfec00000 62 #define PROM_BASE 0xffc00000 63 #define PROM_SIZE (4 * MiB) 64 65 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 66 Error **errp) 67 { 68 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 69 } 70 71 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 72 { 73 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 74 } 75 76 static void ppc_heathrow_reset(void *opaque) 77 { 78 PowerPCCPU *cpu = opaque; 79 80 cpu_reset(CPU(cpu)); 81 } 82 83 static void ppc_heathrow_init(MachineState *machine) 84 { 85 ram_addr_t ram_size = machine->ram_size; 86 const char *kernel_filename = machine->kernel_filename; 87 const char *kernel_cmdline = machine->kernel_cmdline; 88 const char *initrd_filename = machine->initrd_filename; 89 const char *boot_device = machine->boot_order; 90 MemoryRegion *sysmem = get_system_memory(); 91 PowerPCCPU *cpu = NULL; 92 CPUPPCState *env = NULL; 93 char *filename; 94 int linux_boot, i; 95 MemoryRegion *bios = g_new(MemoryRegion, 1); 96 uint32_t kernel_base, initrd_base, cmdline_base = 0; 97 int32_t kernel_size, initrd_size; 98 PCIBus *pci_bus; 99 PCIDevice *macio; 100 MACIOIDEState *macio_ide; 101 ESCCState *escc; 102 SysBusDevice *s; 103 DeviceState *dev, *pic_dev; 104 BusState *adb_bus; 105 uint64_t bios_addr; 106 int bios_size; 107 unsigned int smp_cpus = machine->smp.cpus; 108 uint16_t ppc_boot_device; 109 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 110 void *fw_cfg; 111 uint64_t tbfreq; 112 113 linux_boot = (kernel_filename != NULL); 114 115 /* init CPUs */ 116 for (i = 0; i < smp_cpus; i++) { 117 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 118 env = &cpu->env; 119 120 /* Set time-base frequency to 16.6 Mhz */ 121 cpu_ppc_tb_init(env, TBFREQ); 122 qemu_register_reset(ppc_heathrow_reset, cpu); 123 } 124 125 /* allocate RAM */ 126 if (ram_size > 2047 * MiB) { 127 error_report("Too much memory for this machine: %" PRId64 " MB, " 128 "maximum 2047 MB", ram_size / MiB); 129 exit(1); 130 } 131 132 memory_region_add_subregion(sysmem, 0, machine->ram); 133 134 /* allocate and load firmware ROM */ 135 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, 136 &error_fatal); 137 memory_region_add_subregion(sysmem, PROM_BASE, bios); 138 139 if (!bios_name) { 140 bios_name = PROM_FILENAME; 141 } 142 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 143 if (filename) { 144 /* Load OpenBIOS (ELF) */ 145 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, 146 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 147 /* Unfortunately, load_elf sign-extends reading elf32 */ 148 bios_addr = (uint32_t)bios_addr; 149 150 if (bios_size <= 0) { 151 /* or load binary ROM image */ 152 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 153 bios_addr = PROM_BASE; 154 } 155 g_free(filename); 156 } else { 157 bios_size = -1; 158 } 159 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { 160 error_report("could not load PowerPC bios '%s'", bios_name); 161 exit(1); 162 } 163 164 if (linux_boot) { 165 int bswap_needed; 166 167 #ifdef BSWAP_NEEDED 168 bswap_needed = 1; 169 #else 170 bswap_needed = 0; 171 #endif 172 kernel_base = KERNEL_LOAD_ADDR; 173 kernel_size = load_elf(kernel_filename, NULL, 174 translate_kernel_address, NULL, NULL, NULL, 175 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 176 if (kernel_size < 0) 177 kernel_size = load_aout(kernel_filename, kernel_base, 178 ram_size - kernel_base, bswap_needed, 179 TARGET_PAGE_SIZE); 180 if (kernel_size < 0) 181 kernel_size = load_image_targphys(kernel_filename, 182 kernel_base, 183 ram_size - kernel_base); 184 if (kernel_size < 0) { 185 error_report("could not load kernel '%s'", kernel_filename); 186 exit(1); 187 } 188 /* load initrd */ 189 if (initrd_filename) { 190 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 191 initrd_size = load_image_targphys(initrd_filename, initrd_base, 192 ram_size - initrd_base); 193 if (initrd_size < 0) { 194 error_report("could not load initial ram disk '%s'", 195 initrd_filename); 196 exit(1); 197 } 198 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 199 } else { 200 initrd_base = 0; 201 initrd_size = 0; 202 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 203 } 204 ppc_boot_device = 'm'; 205 } else { 206 kernel_base = 0; 207 kernel_size = 0; 208 initrd_base = 0; 209 initrd_size = 0; 210 ppc_boot_device = '\0'; 211 for (i = 0; boot_device[i] != '\0'; i++) { 212 /* TOFIX: for now, the second IDE channel is not properly 213 * used by OHW. The Mac floppy disk are not emulated. 214 * For now, OHW cannot boot from the network. 215 */ 216 #if 0 217 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 218 ppc_boot_device = boot_device[i]; 219 break; 220 } 221 #else 222 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 223 ppc_boot_device = boot_device[i]; 224 break; 225 } 226 #endif 227 } 228 if (ppc_boot_device == '\0') { 229 error_report("No valid boot device for G3 Beige machine"); 230 exit(1); 231 } 232 } 233 234 /* XXX: we register only 1 output pin for heathrow PIC */ 235 pic_dev = qdev_new(TYPE_HEATHROW); 236 sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal); 237 238 /* Connect the heathrow PIC outputs to the 6xx bus */ 239 for (i = 0; i < smp_cpus; i++) { 240 switch (PPC_INPUT(env)) { 241 case PPC_FLAGS_INPUT_6xx: 242 qdev_connect_gpio_out(pic_dev, 0, 243 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); 244 break; 245 default: 246 error_report("Bus model not supported on OldWorld Mac machine"); 247 exit(1); 248 } 249 } 250 251 /* Timebase Frequency */ 252 if (kvm_enabled()) { 253 tbfreq = kvmppc_get_tbfreq(); 254 } else { 255 tbfreq = TBFREQ; 256 } 257 258 /* init basic PC hardware */ 259 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 260 error_report("Only 6xx bus is supported on heathrow machine"); 261 exit(1); 262 } 263 264 /* Grackle PCI host bridge */ 265 dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 266 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 267 s = SYS_BUS_DEVICE(dev); 268 sysbus_realize_and_unref(s, &error_fatal); 269 270 sysbus_mmio_map(s, 0, GRACKLE_BASE); 271 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 272 /* PCI hole */ 273 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 274 sysbus_mmio_get_region(s, 2)); 275 /* Register 2 MB of ISA IO space */ 276 memory_region_add_subregion(get_system_memory(), 0xfe000000, 277 sysbus_mmio_get_region(s, 3)); 278 279 for (i = 0; i < 4; i++) { 280 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x15 + i)); 281 } 282 283 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 284 285 pci_vga_init(pci_bus); 286 287 for (i = 0; i < nb_nics; i++) { 288 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 289 } 290 291 ide_drive_get(hd, ARRAY_SIZE(hd)); 292 293 /* MacIO */ 294 macio = pci_new(-1, TYPE_OLDWORLD_MACIO); 295 dev = DEVICE(macio); 296 qdev_prop_set_uint64(dev, "frequency", tbfreq); 297 object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev), 298 &error_abort); 299 300 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc")); 301 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0)); 302 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1)); 303 304 pci_realize_and_unref(macio, pci_bus, &error_fatal); 305 306 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 307 "ide[0]")); 308 macio_ide_init_drives(macio_ide, hd); 309 310 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 311 "ide[1]")); 312 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 313 314 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 315 adb_bus = qdev_get_child_bus(dev, "adb.0"); 316 dev = qdev_new(TYPE_ADB_KEYBOARD); 317 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 318 dev = qdev_new(TYPE_ADB_MOUSE); 319 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 320 321 if (machine_usb(machine)) { 322 pci_create_simple(pci_bus, -1, "pci-ohci"); 323 } 324 325 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 326 graphic_depth = 15; 327 328 /* No PCI init: the BIOS will do it */ 329 330 dev = qdev_new(TYPE_FW_CFG_MEM); 331 fw_cfg = FW_CFG(dev); 332 qdev_prop_set_uint32(dev, "data_width", 1); 333 qdev_prop_set_bit(dev, "dma_enabled", false); 334 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 335 OBJECT(fw_cfg)); 336 s = SYS_BUS_DEVICE(dev); 337 sysbus_realize_and_unref(s, &error_fatal); 338 sysbus_mmio_map(s, 0, CFG_ADDR); 339 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 340 341 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 342 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 343 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 344 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 345 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 346 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 347 if (kernel_cmdline) { 348 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 349 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 350 } else { 351 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 352 } 353 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 354 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 355 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 356 357 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 358 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 359 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 360 361 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 362 if (kvm_enabled()) { 363 uint8_t *hypercall; 364 365 hypercall = g_malloc(16); 366 kvmppc_get_hypercall(env, hypercall, 16); 367 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 368 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 369 } 370 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 371 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 372 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 373 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 374 375 /* MacOS NDRV VGA driver */ 376 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 377 if (filename) { 378 gchar *ndrv_file; 379 gsize ndrv_size; 380 381 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 382 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 383 } 384 g_free(filename); 385 } 386 387 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 388 } 389 390 /* 391 * Implementation of an interface to adjust firmware path 392 * for the bootindex property handling. 393 */ 394 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 395 DeviceState *dev) 396 { 397 PCIDevice *pci; 398 IDEBus *ide_bus; 399 IDEState *ide_s; 400 MACIOIDEState *macio_ide; 401 402 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 403 pci = PCI_DEVICE(dev); 404 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 405 } 406 407 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 408 macio_ide = MACIO_IDE(dev); 409 return g_strdup_printf("ata-3@%x", macio_ide->addr); 410 } 411 412 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 413 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 414 ide_s = idebus_active_if(ide_bus); 415 416 if (ide_s->drive_kind == IDE_CD) { 417 return g_strdup("cdrom"); 418 } 419 420 return g_strdup("disk"); 421 } 422 423 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 424 return g_strdup("disk"); 425 } 426 427 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 428 return g_strdup("cdrom"); 429 } 430 431 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 432 return g_strdup("disk"); 433 } 434 435 return NULL; 436 } 437 438 static int heathrow_kvm_type(MachineState *machine, const char *arg) 439 { 440 /* Always force PR KVM */ 441 return 2; 442 } 443 444 static void heathrow_class_init(ObjectClass *oc, void *data) 445 { 446 MachineClass *mc = MACHINE_CLASS(oc); 447 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 448 449 mc->desc = "Heathrow based PowerMAC"; 450 mc->init = ppc_heathrow_init; 451 mc->block_default_type = IF_IDE; 452 mc->max_cpus = MAX_CPUS; 453 #ifndef TARGET_PPC64 454 mc->is_default = true; 455 #endif 456 /* TOFIX "cad" when Mac floppy is implemented */ 457 mc->default_boot_order = "cd"; 458 mc->kvm_type = heathrow_kvm_type; 459 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 460 mc->default_display = "std"; 461 mc->ignore_boot_device_suffixes = true; 462 mc->default_ram_id = "ppc_heathrow.ram"; 463 fwc->get_dev_path = heathrow_fw_dev_path; 464 } 465 466 static const TypeInfo ppc_heathrow_machine_info = { 467 .name = MACHINE_TYPE_NAME("g3beige"), 468 .parent = TYPE_MACHINE, 469 .class_init = heathrow_class_init, 470 .interfaces = (InterfaceInfo[]) { 471 { TYPE_FW_PATH_PROVIDER }, 472 { } 473 }, 474 }; 475 476 static void ppc_heathrow_register_types(void) 477 { 478 type_register_static(&ppc_heathrow_machine_info); 479 } 480 481 type_init(ppc_heathrow_register_types); 482