1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "exec/target_page.h" 32 #include "hw/ppc/ppc.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/boards.h" 35 #include "hw/input/adb.h" 36 #include "system/system.h" 37 #include "net/net.h" 38 #include "hw/isa/isa.h" 39 #include "hw/pci/pci.h" 40 #include "hw/pci/pci_host.h" 41 #include "hw/pci-host/grackle.h" 42 #include "hw/nvram/fw_cfg.h" 43 #include "hw/char/escc.h" 44 #include "hw/misc/macio/macio.h" 45 #include "hw/loader.h" 46 #include "hw/fw-path-provider.h" 47 #include "elf.h" 48 #include "qemu/error-report.h" 49 #include "system/kvm.h" 50 #include "system/reset.h" 51 #include "kvm_ppc.h" 52 53 #define MAX_IDE_BUS 2 54 #define CFG_ADDR 0xf0000510 55 #define TBFREQ 16600000UL 56 #define CLOCKFREQ 266000000UL 57 #define BUSFREQ 66000000UL 58 59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 60 61 #define PROM_FILENAME "openbios-ppc" 62 #define PROM_BASE 0xffc00000 63 #define PROM_SIZE (4 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x01000000 66 #define KERNEL_GAP 0x00100000 67 68 #define GRACKLE_BASE 0xfec00000 69 70 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 71 Error **errp) 72 { 73 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 74 } 75 76 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 77 { 78 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 79 } 80 81 static void ppc_heathrow_reset(void *opaque) 82 { 83 PowerPCCPU *cpu = opaque; 84 85 cpu_ppc_tb_reset(&cpu->env); 86 cpu_reset(CPU(cpu)); 87 } 88 89 static void ppc_heathrow_init(MachineState *machine) 90 { 91 const char *bios_name = machine->firmware ?: PROM_FILENAME; 92 MachineClass *mc = MACHINE_GET_CLASS(machine); 93 PowerPCCPU *cpu = NULL; 94 CPUPPCState *env = NULL; 95 char *filename; 96 int i, bios_size = -1; 97 MemoryRegion *bios = g_new(MemoryRegion, 1); 98 uint64_t bios_addr; 99 uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0; 100 int32_t kernel_size = 0, initrd_size = 0; 101 PCIBus *pci_bus; 102 Object *macio; 103 MACIOIDEState *macio_ide; 104 SysBusDevice *s; 105 DeviceState *dev, *pic_dev, *grackle_dev; 106 BusState *adb_bus; 107 uint16_t ppc_boot_device; 108 DriveInfo *dinfo, *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 109 void *fw_cfg; 110 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; 111 112 /* init CPUs */ 113 for (i = 0; i < machine->smp.cpus; i++) { 114 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 115 env = &cpu->env; 116 117 /* Set time-base frequency to 16.6 Mhz */ 118 cpu_ppc_tb_init(env, TBFREQ); 119 qemu_register_reset(ppc_heathrow_reset, cpu); 120 } 121 122 /* allocate RAM */ 123 if (machine->ram_size > 2047 * MiB) { 124 error_report("Too much memory for this machine: %" PRId64 " MB, " 125 "maximum 2047 MB", machine->ram_size / MiB); 126 exit(1); 127 } 128 129 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 130 131 /* allocate and load firmware ROM */ 132 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, 133 &error_fatal); 134 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 135 136 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 137 if (filename) { 138 /* Load OpenBIOS (ELF) */ 139 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, 140 NULL, NULL, ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); 141 /* Unfortunately, load_elf sign-extends reading elf32 */ 142 bios_addr = (uint32_t)bios_addr; 143 144 if (bios_size <= 0) { 145 /* or if could not load ELF try loading a binary ROM image */ 146 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 147 bios_addr = PROM_BASE; 148 } 149 g_free(filename); 150 } 151 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { 152 error_report("could not load PowerPC bios '%s'", bios_name); 153 exit(1); 154 } 155 156 if (machine->kernel_filename) { 157 kernel_base = KERNEL_LOAD_ADDR; 158 kernel_size = load_elf(machine->kernel_filename, NULL, 159 translate_kernel_address, NULL, NULL, NULL, 160 NULL, NULL, ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); 161 if (kernel_size < 0) { 162 kernel_size = load_aout(machine->kernel_filename, kernel_base, 163 machine->ram_size - kernel_base, 164 true, TARGET_PAGE_SIZE); 165 } 166 if (kernel_size < 0) { 167 kernel_size = load_image_targphys(machine->kernel_filename, 168 kernel_base, 169 machine->ram_size - kernel_base); 170 } 171 if (kernel_size < 0) { 172 error_report("could not load kernel '%s'", 173 machine->kernel_filename); 174 exit(1); 175 } 176 /* load initrd */ 177 if (machine->initrd_filename) { 178 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 179 KERNEL_GAP); 180 initrd_size = load_image_targphys(machine->initrd_filename, 181 initrd_base, 182 machine->ram_size - initrd_base); 183 if (initrd_size < 0) { 184 error_report("could not load initial ram disk '%s'", 185 machine->initrd_filename); 186 exit(1); 187 } 188 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 189 } else { 190 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 191 } 192 ppc_boot_device = 'm'; 193 } else { 194 ppc_boot_device = '\0'; 195 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 196 /* 197 * TOFIX: for now, the second IDE channel is not properly 198 * used by OHW. The Mac floppy disk are not emulated. 199 * For now, OHW cannot boot from the network. 200 */ 201 #if 0 202 if (machine->boot_config.order[i] >= 'a' && 203 machine->boot_config.order[i] <= 'f') { 204 ppc_boot_device = machine->boot_config.order[i]; 205 break; 206 } 207 #else 208 if (machine->boot_config.order[i] >= 'c' && 209 machine->boot_config.order[i] <= 'd') { 210 ppc_boot_device = machine->boot_config.order[i]; 211 break; 212 } 213 #endif 214 } 215 if (ppc_boot_device == '\0') { 216 error_report("No valid boot device for G3 Beige machine"); 217 exit(1); 218 } 219 } 220 221 /* Grackle PCI host bridge */ 222 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 223 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000); 224 s = SYS_BUS_DEVICE(grackle_dev); 225 sysbus_realize_and_unref(s, &error_fatal); 226 227 sysbus_mmio_map(s, 0, GRACKLE_BASE); 228 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 229 /* PCI hole */ 230 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 231 sysbus_mmio_get_region(s, 2)); 232 /* Register 2 MB of ISA IO space */ 233 memory_region_add_subregion(get_system_memory(), 0xfe000000, 234 sysbus_mmio_get_region(s, 3)); 235 236 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus; 237 238 /* MacIO */ 239 macio = OBJECT(pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO)); 240 qdev_prop_set_uint64(DEVICE(macio), "frequency", tbfreq); 241 242 dev = DEVICE(object_resolve_path_component(macio, "escc")); 243 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 244 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 245 246 dinfo = drive_get(IF_MTD, 0, 0); 247 if (dinfo) { 248 dev = DEVICE(object_resolve_path_component(macio, "nvram")); 249 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 250 } 251 252 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); 253 254 pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); 255 for (i = 0; i < 4; i++) { 256 qdev_connect_gpio_out(grackle_dev, i, 257 qdev_get_gpio_in(pic_dev, 0x15 + i)); 258 } 259 260 /* Connect the heathrow PIC outputs to the 6xx bus */ 261 for (i = 0; i < machine->smp.cpus; i++) { 262 switch (PPC_INPUT(env)) { 263 case PPC_FLAGS_INPUT_6xx: 264 /* XXX: we register only 1 output pin for heathrow PIC */ 265 qdev_connect_gpio_out(pic_dev, 0, 266 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); 267 break; 268 default: 269 error_report("Bus model not supported on OldWorld Mac machine"); 270 exit(1); 271 } 272 } 273 274 pci_vga_init(pci_bus); 275 276 pci_init_nic_devices(pci_bus, mc->default_nic); 277 278 /* MacIO IDE */ 279 ide_drive_get(hd, ARRAY_SIZE(hd)); 280 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); 281 macio_ide_init_drives(macio_ide, hd); 282 283 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); 284 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 285 286 /* MacIO CUDA/ADB */ 287 dev = DEVICE(object_resolve_path_component(macio, "cuda")); 288 adb_bus = qdev_get_child_bus(dev, "adb.0"); 289 dev = qdev_new(TYPE_ADB_KEYBOARD); 290 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 291 dev = qdev_new(TYPE_ADB_MOUSE); 292 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 293 294 if (machine_usb(machine)) { 295 pci_create_simple(pci_bus, -1, "pci-ohci"); 296 } 297 298 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 299 graphic_depth = 15; 300 } 301 302 /* No PCI init: the BIOS will do it */ 303 304 dev = qdev_new(TYPE_FW_CFG_MEM); 305 fw_cfg = FW_CFG(dev); 306 qdev_prop_set_uint32(dev, "data_width", 1); 307 qdev_prop_set_bit(dev, "dma_enabled", false); 308 object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg)); 309 s = SYS_BUS_DEVICE(dev); 310 sysbus_realize_and_unref(s, &error_fatal); 311 sysbus_mmio_map(s, 0, CFG_ADDR); 312 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 313 314 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 315 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 316 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 317 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 318 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 319 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 320 if (machine->kernel_cmdline) { 321 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 322 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 323 machine->kernel_cmdline); 324 } else { 325 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 326 } 327 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 328 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 329 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 330 331 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 332 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 333 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 334 335 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 336 if (kvm_enabled()) { 337 uint8_t *hypercall; 338 339 hypercall = g_malloc(16); 340 kvmppc_get_hypercall(env, hypercall, 16); 341 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 342 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 343 } 344 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 345 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 346 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 347 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 348 349 /* MacOS NDRV VGA driver */ 350 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 351 if (filename) { 352 gchar *ndrv_file; 353 gsize ndrv_size; 354 355 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 356 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 357 } 358 g_free(filename); 359 } 360 361 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 362 } 363 364 /* 365 * Implementation of an interface to adjust firmware path 366 * for the bootindex property handling. 367 */ 368 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 369 DeviceState *dev) 370 { 371 PCIDevice *pci; 372 MACIOIDEState *macio_ide; 373 374 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 375 pci = PCI_DEVICE(dev); 376 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 377 } 378 379 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 380 macio_ide = MACIO_IDE(dev); 381 return g_strdup_printf("ata-3@%x", macio_ide->addr); 382 } 383 384 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 385 return g_strdup("disk"); 386 } 387 388 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 389 return g_strdup("cdrom"); 390 } 391 392 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 393 return g_strdup("disk"); 394 } 395 396 return NULL; 397 } 398 399 static int heathrow_kvm_type(MachineState *machine, const char *arg) 400 { 401 /* Always force PR KVM */ 402 return 2; 403 } 404 405 static void heathrow_class_init(ObjectClass *oc, const void *data) 406 { 407 MachineClass *mc = MACHINE_CLASS(oc); 408 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 409 410 mc->desc = "Heathrow based PowerMac"; 411 mc->init = ppc_heathrow_init; 412 mc->block_default_type = IF_IDE; 413 /* SMP is not supported currently */ 414 mc->max_cpus = 1; 415 #ifndef TARGET_PPC64 416 mc->is_default = true; 417 #endif 418 /* TOFIX "cad" when Mac floppy is implemented */ 419 mc->default_boot_order = "cd"; 420 mc->kvm_type = heathrow_kvm_type; 421 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 422 mc->default_display = "std"; 423 mc->default_nic = "ne2k_pci"; 424 mc->ignore_boot_device_suffixes = true; 425 mc->default_ram_id = "ppc_heathrow.ram"; 426 fwc->get_dev_path = heathrow_fw_dev_path; 427 } 428 429 static const TypeInfo ppc_heathrow_machine_info = { 430 .name = MACHINE_TYPE_NAME("g3beige"), 431 .parent = TYPE_MACHINE, 432 .class_init = heathrow_class_init, 433 .interfaces = (const InterfaceInfo[]) { 434 { TYPE_FW_PATH_PROVIDER }, 435 { } 436 }, 437 }; 438 439 static void ppc_heathrow_register_types(void) 440 { 441 type_register_static(&ppc_heathrow_machine_info); 442 } 443 444 type_init(ppc_heathrow_register_types); 445