1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "mac.h" 34 #include "hw/boards.h" 35 #include "hw/input/adb.h" 36 #include "sysemu/sysemu.h" 37 #include "net/net.h" 38 #include "hw/isa/isa.h" 39 #include "hw/pci/pci.h" 40 #include "hw/pci/pci_host.h" 41 #include "hw/pci-host/grackle.h" 42 #include "hw/nvram/fw_cfg.h" 43 #include "hw/char/escc.h" 44 #include "hw/misc/macio/macio.h" 45 #include "hw/loader.h" 46 #include "hw/fw-path-provider.h" 47 #include "elf.h" 48 #include "qemu/error-report.h" 49 #include "sysemu/kvm.h" 50 #include "sysemu/reset.h" 51 #include "kvm_ppc.h" 52 53 #define MAX_IDE_BUS 2 54 #define CFG_ADDR 0xf0000510 55 #define TBFREQ 16600000UL 56 #define CLOCKFREQ 266000000UL 57 #define BUSFREQ 66000000UL 58 59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 60 61 #define PROM_FILENAME "openbios-ppc" 62 #define PROM_BASE 0xffc00000 63 #define PROM_SIZE (4 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x01000000 66 #define KERNEL_GAP 0x00100000 67 68 #define GRACKLE_BASE 0xfec00000 69 70 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 71 Error **errp) 72 { 73 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 74 } 75 76 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 77 { 78 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 79 } 80 81 static void ppc_heathrow_reset(void *opaque) 82 { 83 PowerPCCPU *cpu = opaque; 84 85 cpu_reset(CPU(cpu)); 86 } 87 88 static void ppc_heathrow_init(MachineState *machine) 89 { 90 const char *bios_name = machine->firmware ?: PROM_FILENAME; 91 PowerPCCPU *cpu = NULL; 92 CPUPPCState *env = NULL; 93 char *filename; 94 int i, bios_size = -1; 95 MemoryRegion *bios = g_new(MemoryRegion, 1); 96 uint64_t bios_addr; 97 uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0; 98 int32_t kernel_size = 0, initrd_size = 0; 99 PCIBus *pci_bus; 100 Object *macio; 101 MACIOIDEState *macio_ide; 102 SysBusDevice *s; 103 DeviceState *dev, *pic_dev, *grackle_dev; 104 BusState *adb_bus; 105 uint16_t ppc_boot_device; 106 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 107 void *fw_cfg; 108 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; 109 110 /* init CPUs */ 111 for (i = 0; i < machine->smp.cpus; i++) { 112 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 113 env = &cpu->env; 114 115 /* Set time-base frequency to 16.6 Mhz */ 116 cpu_ppc_tb_init(env, TBFREQ); 117 qemu_register_reset(ppc_heathrow_reset, cpu); 118 } 119 120 /* allocate RAM */ 121 if (machine->ram_size > 2047 * MiB) { 122 error_report("Too much memory for this machine: %" PRId64 " MB, " 123 "maximum 2047 MB", machine->ram_size / MiB); 124 exit(1); 125 } 126 127 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 128 129 /* allocate and load firmware ROM */ 130 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, 131 &error_fatal); 132 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 133 134 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 135 if (filename) { 136 /* Load OpenBIOS (ELF) */ 137 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, 138 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 139 /* Unfortunately, load_elf sign-extends reading elf32 */ 140 bios_addr = (uint32_t)bios_addr; 141 142 if (bios_size <= 0) { 143 /* or if could not load ELF try loading a binary ROM image */ 144 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 145 bios_addr = PROM_BASE; 146 } 147 g_free(filename); 148 } 149 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { 150 error_report("could not load PowerPC bios '%s'", bios_name); 151 exit(1); 152 } 153 154 if (machine->kernel_filename) { 155 int bswap_needed = 0; 156 157 #ifdef BSWAP_NEEDED 158 bswap_needed = 1; 159 #endif 160 kernel_base = KERNEL_LOAD_ADDR; 161 kernel_size = load_elf(machine->kernel_filename, NULL, 162 translate_kernel_address, NULL, NULL, NULL, 163 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 164 if (kernel_size < 0) 165 kernel_size = load_aout(machine->kernel_filename, kernel_base, 166 machine->ram_size - kernel_base, 167 bswap_needed, TARGET_PAGE_SIZE); 168 if (kernel_size < 0) 169 kernel_size = load_image_targphys(machine->kernel_filename, 170 kernel_base, 171 machine->ram_size - kernel_base); 172 if (kernel_size < 0) { 173 error_report("could not load kernel '%s'", 174 machine->kernel_filename); 175 exit(1); 176 } 177 /* load initrd */ 178 if (machine->initrd_filename) { 179 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 180 KERNEL_GAP); 181 initrd_size = load_image_targphys(machine->initrd_filename, 182 initrd_base, 183 machine->ram_size - initrd_base); 184 if (initrd_size < 0) { 185 error_report("could not load initial ram disk '%s'", 186 machine->initrd_filename); 187 exit(1); 188 } 189 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 190 } else { 191 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 192 } 193 ppc_boot_device = 'm'; 194 } else { 195 ppc_boot_device = '\0'; 196 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 197 /* 198 * TOFIX: for now, the second IDE channel is not properly 199 * used by OHW. The Mac floppy disk are not emulated. 200 * For now, OHW cannot boot from the network. 201 */ 202 #if 0 203 if (machine->boot_config.order[i] >= 'a' && 204 machine->boot_config.order[i] <= 'f') { 205 ppc_boot_device = machine->boot_config.order[i]; 206 break; 207 } 208 #else 209 if (machine->boot_config.order[i] >= 'c' && 210 machine->boot_config.order[i] <= 'd') { 211 ppc_boot_device = machine->boot_config.order[i]; 212 break; 213 } 214 #endif 215 } 216 if (ppc_boot_device == '\0') { 217 error_report("No valid boot device for G3 Beige machine"); 218 exit(1); 219 } 220 } 221 222 /* Grackle PCI host bridge */ 223 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 224 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000); 225 s = SYS_BUS_DEVICE(grackle_dev); 226 sysbus_realize_and_unref(s, &error_fatal); 227 228 sysbus_mmio_map(s, 0, GRACKLE_BASE); 229 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 230 /* PCI hole */ 231 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 232 sysbus_mmio_get_region(s, 2)); 233 /* Register 2 MB of ISA IO space */ 234 memory_region_add_subregion(get_system_memory(), 0xfe000000, 235 sysbus_mmio_get_region(s, 3)); 236 237 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus; 238 239 /* MacIO */ 240 macio = OBJECT(pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO)); 241 qdev_prop_set_uint64(DEVICE(macio), "frequency", tbfreq); 242 243 dev = DEVICE(object_resolve_path_component(macio, "escc")); 244 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 245 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 246 247 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); 248 249 pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); 250 for (i = 0; i < 4; i++) { 251 qdev_connect_gpio_out(grackle_dev, i, 252 qdev_get_gpio_in(pic_dev, 0x15 + i)); 253 } 254 255 /* Connect the heathrow PIC outputs to the 6xx bus */ 256 for (i = 0; i < machine->smp.cpus; i++) { 257 switch (PPC_INPUT(env)) { 258 case PPC_FLAGS_INPUT_6xx: 259 /* XXX: we register only 1 output pin for heathrow PIC */ 260 qdev_connect_gpio_out(pic_dev, 0, 261 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); 262 break; 263 default: 264 error_report("Bus model not supported on OldWorld Mac machine"); 265 exit(1); 266 } 267 } 268 269 pci_vga_init(pci_bus); 270 271 for (i = 0; i < nb_nics; i++) { 272 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 273 } 274 275 /* MacIO IDE */ 276 ide_drive_get(hd, ARRAY_SIZE(hd)); 277 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); 278 macio_ide_init_drives(macio_ide, hd); 279 280 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); 281 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 282 283 /* MacIO CUDA/ADB */ 284 dev = DEVICE(object_resolve_path_component(macio, "cuda")); 285 adb_bus = qdev_get_child_bus(dev, "adb.0"); 286 dev = qdev_new(TYPE_ADB_KEYBOARD); 287 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 288 dev = qdev_new(TYPE_ADB_MOUSE); 289 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 290 291 if (machine_usb(machine)) { 292 pci_create_simple(pci_bus, -1, "pci-ohci"); 293 } 294 295 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 296 graphic_depth = 15; 297 298 /* No PCI init: the BIOS will do it */ 299 300 dev = qdev_new(TYPE_FW_CFG_MEM); 301 fw_cfg = FW_CFG(dev); 302 qdev_prop_set_uint32(dev, "data_width", 1); 303 qdev_prop_set_bit(dev, "dma_enabled", false); 304 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 305 OBJECT(fw_cfg)); 306 s = SYS_BUS_DEVICE(dev); 307 sysbus_realize_and_unref(s, &error_fatal); 308 sysbus_mmio_map(s, 0, CFG_ADDR); 309 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 310 311 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 312 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 313 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 314 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 315 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 316 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 317 if (machine->kernel_cmdline) { 318 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 319 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 320 machine->kernel_cmdline); 321 } else { 322 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 323 } 324 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 325 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 326 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 327 328 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 329 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 330 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 331 332 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 333 if (kvm_enabled()) { 334 uint8_t *hypercall; 335 336 hypercall = g_malloc(16); 337 kvmppc_get_hypercall(env, hypercall, 16); 338 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 339 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 340 } 341 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 342 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 343 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 344 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 345 346 /* MacOS NDRV VGA driver */ 347 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 348 if (filename) { 349 gchar *ndrv_file; 350 gsize ndrv_size; 351 352 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 353 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 354 } 355 g_free(filename); 356 } 357 358 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 359 } 360 361 /* 362 * Implementation of an interface to adjust firmware path 363 * for the bootindex property handling. 364 */ 365 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 366 DeviceState *dev) 367 { 368 PCIDevice *pci; 369 MACIOIDEState *macio_ide; 370 371 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 372 pci = PCI_DEVICE(dev); 373 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 374 } 375 376 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 377 macio_ide = MACIO_IDE(dev); 378 return g_strdup_printf("ata-3@%x", macio_ide->addr); 379 } 380 381 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 382 return g_strdup("disk"); 383 } 384 385 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 386 return g_strdup("cdrom"); 387 } 388 389 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 390 return g_strdup("disk"); 391 } 392 393 return NULL; 394 } 395 396 static int heathrow_kvm_type(MachineState *machine, const char *arg) 397 { 398 /* Always force PR KVM */ 399 return 2; 400 } 401 402 static void heathrow_class_init(ObjectClass *oc, void *data) 403 { 404 MachineClass *mc = MACHINE_CLASS(oc); 405 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 406 407 mc->desc = "Heathrow based PowerMAC"; 408 mc->init = ppc_heathrow_init; 409 mc->block_default_type = IF_IDE; 410 /* SMP is not supported currently */ 411 mc->max_cpus = 1; 412 #ifndef TARGET_PPC64 413 mc->is_default = true; 414 #endif 415 /* TOFIX "cad" when Mac floppy is implemented */ 416 mc->default_boot_order = "cd"; 417 mc->kvm_type = heathrow_kvm_type; 418 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 419 mc->default_display = "std"; 420 mc->ignore_boot_device_suffixes = true; 421 mc->default_ram_id = "ppc_heathrow.ram"; 422 fwc->get_dev_path = heathrow_fw_dev_path; 423 } 424 425 static const TypeInfo ppc_heathrow_machine_info = { 426 .name = MACHINE_TYPE_NAME("g3beige"), 427 .parent = TYPE_MACHINE, 428 .class_init = heathrow_class_init, 429 .interfaces = (InterfaceInfo[]) { 430 { TYPE_FW_PATH_PROVIDER }, 431 { } 432 }, 433 }; 434 435 static void ppc_heathrow_register_types(void) 436 { 437 type_register_static(&ppc_heathrow_machine_info); 438 } 439 440 type_init(ppc_heathrow_register_types); 441