1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "mac.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 #include "exec/address-spaces.h" 52 53 #define MAX_IDE_BUS 2 54 #define CFG_ADDR 0xf0000510 55 #define TBFREQ 16600000UL 56 #define CLOCKFREQ 266000000UL 57 #define BUSFREQ 66000000UL 58 59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 60 61 #define GRACKLE_BASE 0xfec00000 62 63 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 64 Error **errp) 65 { 66 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 67 } 68 69 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 70 { 71 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 72 } 73 74 static void ppc_heathrow_reset(void *opaque) 75 { 76 PowerPCCPU *cpu = opaque; 77 78 cpu_reset(CPU(cpu)); 79 } 80 81 static void ppc_heathrow_init(MachineState *machine) 82 { 83 ram_addr_t ram_size = machine->ram_size; 84 const char *kernel_filename = machine->kernel_filename; 85 const char *kernel_cmdline = machine->kernel_cmdline; 86 const char *initrd_filename = machine->initrd_filename; 87 const char *boot_device = machine->boot_order; 88 MemoryRegion *sysmem = get_system_memory(); 89 PowerPCCPU *cpu = NULL; 90 CPUPPCState *env = NULL; 91 char *filename; 92 int linux_boot, i; 93 MemoryRegion *bios = g_new(MemoryRegion, 1); 94 uint32_t kernel_base, initrd_base, cmdline_base = 0; 95 int32_t kernel_size, initrd_size; 96 PCIBus *pci_bus; 97 PCIDevice *macio; 98 MACIOIDEState *macio_ide; 99 ESCCState *escc; 100 SysBusDevice *s; 101 DeviceState *dev, *pic_dev; 102 BusState *adb_bus; 103 int bios_size; 104 unsigned int smp_cpus = machine->smp.cpus; 105 uint16_t ppc_boot_device; 106 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 107 void *fw_cfg; 108 uint64_t tbfreq; 109 110 linux_boot = (kernel_filename != NULL); 111 112 /* init CPUs */ 113 for (i = 0; i < smp_cpus; i++) { 114 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 115 env = &cpu->env; 116 117 /* Set time-base frequency to 16.6 Mhz */ 118 cpu_ppc_tb_init(env, TBFREQ); 119 qemu_register_reset(ppc_heathrow_reset, cpu); 120 } 121 122 /* allocate RAM */ 123 if (ram_size > 2047 * MiB) { 124 error_report("Too much memory for this machine: %" PRId64 " MB, " 125 "maximum 2047 MB", ram_size / MiB); 126 exit(1); 127 } 128 129 memory_region_add_subregion(sysmem, 0, machine->ram); 130 131 /* allocate and load BIOS */ 132 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 133 &error_fatal); 134 135 if (bios_name == NULL) 136 bios_name = PROM_FILENAME; 137 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 138 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 139 140 /* Load OpenBIOS (ELF) */ 141 if (filename) { 142 bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL, NULL, 143 1, PPC_ELF_MACHINE, 0, 0); 144 g_free(filename); 145 } else { 146 bios_size = -1; 147 } 148 if (bios_size < 0 || bios_size > BIOS_SIZE) { 149 error_report("could not load PowerPC bios '%s'", bios_name); 150 exit(1); 151 } 152 153 if (linux_boot) { 154 int bswap_needed; 155 156 #ifdef BSWAP_NEEDED 157 bswap_needed = 1; 158 #else 159 bswap_needed = 0; 160 #endif 161 kernel_base = KERNEL_LOAD_ADDR; 162 kernel_size = load_elf(kernel_filename, NULL, 163 translate_kernel_address, NULL, NULL, NULL, 164 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 165 if (kernel_size < 0) 166 kernel_size = load_aout(kernel_filename, kernel_base, 167 ram_size - kernel_base, bswap_needed, 168 TARGET_PAGE_SIZE); 169 if (kernel_size < 0) 170 kernel_size = load_image_targphys(kernel_filename, 171 kernel_base, 172 ram_size - kernel_base); 173 if (kernel_size < 0) { 174 error_report("could not load kernel '%s'", kernel_filename); 175 exit(1); 176 } 177 /* load initrd */ 178 if (initrd_filename) { 179 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 180 initrd_size = load_image_targphys(initrd_filename, initrd_base, 181 ram_size - initrd_base); 182 if (initrd_size < 0) { 183 error_report("could not load initial ram disk '%s'", 184 initrd_filename); 185 exit(1); 186 } 187 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 188 } else { 189 initrd_base = 0; 190 initrd_size = 0; 191 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 192 } 193 ppc_boot_device = 'm'; 194 } else { 195 kernel_base = 0; 196 kernel_size = 0; 197 initrd_base = 0; 198 initrd_size = 0; 199 ppc_boot_device = '\0'; 200 for (i = 0; boot_device[i] != '\0'; i++) { 201 /* TOFIX: for now, the second IDE channel is not properly 202 * used by OHW. The Mac floppy disk are not emulated. 203 * For now, OHW cannot boot from the network. 204 */ 205 #if 0 206 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 207 ppc_boot_device = boot_device[i]; 208 break; 209 } 210 #else 211 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 212 ppc_boot_device = boot_device[i]; 213 break; 214 } 215 #endif 216 } 217 if (ppc_boot_device == '\0') { 218 error_report("No valid boot device for G3 Beige machine"); 219 exit(1); 220 } 221 } 222 223 /* XXX: we register only 1 output pin for heathrow PIC */ 224 pic_dev = qdev_new(TYPE_HEATHROW); 225 sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal); 226 227 /* Connect the heathrow PIC outputs to the 6xx bus */ 228 for (i = 0; i < smp_cpus; i++) { 229 switch (PPC_INPUT(env)) { 230 case PPC_FLAGS_INPUT_6xx: 231 qdev_connect_gpio_out(pic_dev, 0, 232 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); 233 break; 234 default: 235 error_report("Bus model not supported on OldWorld Mac machine"); 236 exit(1); 237 } 238 } 239 240 /* Timebase Frequency */ 241 if (kvm_enabled()) { 242 tbfreq = kvmppc_get_tbfreq(); 243 } else { 244 tbfreq = TBFREQ; 245 } 246 247 /* init basic PC hardware */ 248 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 249 error_report("Only 6xx bus is supported on heathrow machine"); 250 exit(1); 251 } 252 253 /* Grackle PCI host bridge */ 254 dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 255 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 256 object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev), 257 &error_abort); 258 s = SYS_BUS_DEVICE(dev); 259 sysbus_realize_and_unref(s, &error_fatal); 260 sysbus_mmio_map(s, 0, GRACKLE_BASE); 261 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 262 /* PCI hole */ 263 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 264 sysbus_mmio_get_region(s, 2)); 265 /* Register 2 MB of ISA IO space */ 266 memory_region_add_subregion(get_system_memory(), 0xfe000000, 267 sysbus_mmio_get_region(s, 3)); 268 269 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 270 271 pci_vga_init(pci_bus); 272 273 for (i = 0; i < nb_nics; i++) { 274 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 275 } 276 277 ide_drive_get(hd, ARRAY_SIZE(hd)); 278 279 /* MacIO */ 280 macio = pci_new(-1, TYPE_OLDWORLD_MACIO); 281 dev = DEVICE(macio); 282 qdev_prop_set_uint64(dev, "frequency", tbfreq); 283 object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev), 284 &error_abort); 285 286 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc")); 287 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0)); 288 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1)); 289 290 pci_realize_and_unref(macio, pci_bus, &error_fatal); 291 292 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 293 "ide[0]")); 294 macio_ide_init_drives(macio_ide, hd); 295 296 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 297 "ide[1]")); 298 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 299 300 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 301 adb_bus = qdev_get_child_bus(dev, "adb.0"); 302 dev = qdev_new(TYPE_ADB_KEYBOARD); 303 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 304 dev = qdev_new(TYPE_ADB_MOUSE); 305 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 306 307 if (machine_usb(machine)) { 308 pci_create_simple(pci_bus, -1, "pci-ohci"); 309 } 310 311 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 312 graphic_depth = 15; 313 314 /* No PCI init: the BIOS will do it */ 315 316 dev = qdev_new(TYPE_FW_CFG_MEM); 317 fw_cfg = FW_CFG(dev); 318 qdev_prop_set_uint32(dev, "data_width", 1); 319 qdev_prop_set_bit(dev, "dma_enabled", false); 320 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 321 OBJECT(fw_cfg)); 322 s = SYS_BUS_DEVICE(dev); 323 sysbus_realize_and_unref(s, &error_fatal); 324 sysbus_mmio_map(s, 0, CFG_ADDR); 325 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 326 327 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 328 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 329 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 330 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 331 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 332 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 333 if (kernel_cmdline) { 334 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 335 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 336 } else { 337 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 338 } 339 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 340 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 341 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 342 343 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 344 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 345 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 346 347 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 348 if (kvm_enabled()) { 349 uint8_t *hypercall; 350 351 hypercall = g_malloc(16); 352 kvmppc_get_hypercall(env, hypercall, 16); 353 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 354 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 355 } 356 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 357 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 358 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 359 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 360 361 /* MacOS NDRV VGA driver */ 362 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 363 if (filename) { 364 gchar *ndrv_file; 365 gsize ndrv_size; 366 367 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 368 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 369 } 370 g_free(filename); 371 } 372 373 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 374 } 375 376 /* 377 * Implementation of an interface to adjust firmware path 378 * for the bootindex property handling. 379 */ 380 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 381 DeviceState *dev) 382 { 383 PCIDevice *pci; 384 IDEBus *ide_bus; 385 IDEState *ide_s; 386 MACIOIDEState *macio_ide; 387 388 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 389 pci = PCI_DEVICE(dev); 390 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 391 } 392 393 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 394 macio_ide = MACIO_IDE(dev); 395 return g_strdup_printf("ata-3@%x", macio_ide->addr); 396 } 397 398 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 399 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 400 ide_s = idebus_active_if(ide_bus); 401 402 if (ide_s->drive_kind == IDE_CD) { 403 return g_strdup("cdrom"); 404 } 405 406 return g_strdup("disk"); 407 } 408 409 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 410 return g_strdup("disk"); 411 } 412 413 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 414 return g_strdup("cdrom"); 415 } 416 417 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 418 return g_strdup("disk"); 419 } 420 421 return NULL; 422 } 423 424 static int heathrow_kvm_type(MachineState *machine, const char *arg) 425 { 426 /* Always force PR KVM */ 427 return 2; 428 } 429 430 static void heathrow_class_init(ObjectClass *oc, void *data) 431 { 432 MachineClass *mc = MACHINE_CLASS(oc); 433 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 434 435 mc->desc = "Heathrow based PowerMAC"; 436 mc->init = ppc_heathrow_init; 437 mc->block_default_type = IF_IDE; 438 mc->max_cpus = MAX_CPUS; 439 #ifndef TARGET_PPC64 440 mc->is_default = true; 441 #endif 442 /* TOFIX "cad" when Mac floppy is implemented */ 443 mc->default_boot_order = "cd"; 444 mc->kvm_type = heathrow_kvm_type; 445 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 446 mc->default_display = "std"; 447 mc->ignore_boot_device_suffixes = true; 448 mc->default_ram_id = "ppc_heathrow.ram"; 449 fwc->get_dev_path = heathrow_fw_dev_path; 450 } 451 452 static const TypeInfo ppc_heathrow_machine_info = { 453 .name = MACHINE_TYPE_NAME("g3beige"), 454 .parent = TYPE_MACHINE, 455 .class_init = heathrow_class_init, 456 .interfaces = (InterfaceInfo[]) { 457 { TYPE_FW_PATH_PROVIDER }, 458 { } 459 }, 460 }; 461 462 static void ppc_heathrow_register_types(void) 463 { 464 type_register_static(&ppc_heathrow_machine_info); 465 } 466 467 type_init(ppc_heathrow_register_types); 468