1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "qemu/datadir.h" 20 #include "qemu/units.h" 21 #include "qapi/error.h" 22 #include "e500.h" 23 #include "e500-ccsr.h" 24 #include "net/net.h" 25 #include "qemu/config-file.h" 26 #include "hw/char/serial.h" 27 #include "hw/pci/pci.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/kvm.h" 30 #include "sysemu/reset.h" 31 #include "sysemu/runstate.h" 32 #include "kvm_ppc.h" 33 #include "sysemu/device_tree.h" 34 #include "hw/ppc/openpic.h" 35 #include "hw/ppc/openpic_kvm.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "hw/sysbus.h" 41 #include "exec/address-spaces.h" 42 #include "qemu/host-utils.h" 43 #include "qemu/option.h" 44 #include "hw/pci-host/ppce500.h" 45 #include "qemu/error-report.h" 46 #include "hw/platform-bus.h" 47 #include "hw/net/fsl_etsec/etsec.h" 48 #include "hw/i2c/i2c.h" 49 #include "hw/irq.h" 50 51 #define EPAPR_MAGIC (0x45504150) 52 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 53 #define DTC_LOAD_PAD 0x1800000 54 #define DTC_PAD_MASK 0xFFFFF 55 #define DTB_MAX_SIZE (8 * MiB) 56 #define INITRD_LOAD_PAD 0x2000000 57 #define INITRD_PAD_MASK 0xFFFFFF 58 59 #define RAM_SIZES_ALIGN (64 * MiB) 60 61 /* TODO: parameterize */ 62 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 63 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 64 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 65 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 66 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 67 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 68 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 69 #define MPC8544_UTIL_OFFSET 0xe0000ULL 70 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 71 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 72 #define MPC8XXX_GPIO_IRQ 47 73 #define MPC8544_I2C_IRQ 43 74 #define RTC_REGS_OFFSET 0x68 75 76 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) 77 78 struct boot_info 79 { 80 uint32_t dt_base; 81 uint32_t dt_size; 82 uint32_t entry; 83 }; 84 85 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 86 int nr_slots, int *len) 87 { 88 int i = 0; 89 int slot; 90 int pci_irq; 91 int host_irq; 92 int last_slot = first_slot + nr_slots; 93 uint32_t *pci_map; 94 95 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 96 pci_map = g_malloc(*len); 97 98 for (slot = first_slot; slot < last_slot; slot++) { 99 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 100 pci_map[i++] = cpu_to_be32(slot << 11); 101 pci_map[i++] = cpu_to_be32(0x0); 102 pci_map[i++] = cpu_to_be32(0x0); 103 pci_map[i++] = cpu_to_be32(pci_irq + 1); 104 pci_map[i++] = cpu_to_be32(mpic); 105 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 106 pci_map[i++] = cpu_to_be32(host_irq + 1); 107 pci_map[i++] = cpu_to_be32(0x1); 108 } 109 } 110 111 assert((i * sizeof(uint32_t)) == *len); 112 113 return pci_map; 114 } 115 116 static void dt_serial_create(void *fdt, unsigned long long offset, 117 const char *soc, const char *mpic, 118 const char *alias, int idx, bool defcon) 119 { 120 char *ser; 121 122 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 123 qemu_fdt_add_subnode(fdt, ser); 124 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 125 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 126 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 127 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 128 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ); 129 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 130 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 131 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 132 133 if (defcon) { 134 /* 135 * "linux,stdout-path" and "stdout" properties are deprecated by linux 136 * kernel. New platforms should only use the "stdout-path" property. Set 137 * the new property and continue using older property to remain 138 * compatible with the existing firmware. 139 */ 140 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 141 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 142 } 143 g_free(ser); 144 } 145 146 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 147 { 148 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 149 int irq0 = MPC8XXX_GPIO_IRQ; 150 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 151 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 152 int gpio_ph; 153 154 qemu_fdt_add_subnode(fdt, node); 155 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 156 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 157 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 158 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 159 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 160 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 161 gpio_ph = qemu_fdt_alloc_phandle(fdt); 162 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 163 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 164 165 /* Power Off Pin */ 166 qemu_fdt_add_subnode(fdt, poweroff); 167 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 168 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 169 170 g_free(node); 171 g_free(poweroff); 172 } 173 174 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 175 { 176 int offset = RTC_REGS_OFFSET; 177 178 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 179 qemu_fdt_add_subnode(fdt, rtc); 180 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 181 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 182 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 183 184 g_free(rtc); 185 } 186 187 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 188 const char *alias) 189 { 190 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 191 int irq0 = MPC8544_I2C_IRQ; 192 193 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 194 qemu_fdt_add_subnode(fdt, i2c); 195 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 196 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 197 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 198 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 199 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 200 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 201 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 202 203 g_free(i2c); 204 } 205 206 207 typedef struct PlatformDevtreeData { 208 void *fdt; 209 const char *mpic; 210 int irq_start; 211 const char *node; 212 PlatformBusDevice *pbus; 213 } PlatformDevtreeData; 214 215 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 216 { 217 eTSEC *etsec = ETSEC_COMMON(sbdev); 218 PlatformBusDevice *pbus = data->pbus; 219 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 220 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 221 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 222 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 223 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 224 gchar *group = g_strdup_printf("%s/queue-group", node); 225 void *fdt = data->fdt; 226 227 assert((int64_t)mmio0 >= 0); 228 assert(irq0 >= 0); 229 assert(irq1 >= 0); 230 assert(irq2 >= 0); 231 232 qemu_fdt_add_subnode(fdt, node); 233 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0); 234 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 235 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 236 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 237 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 238 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 239 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 240 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 241 242 qemu_fdt_add_subnode(fdt, group); 243 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 244 qemu_fdt_setprop_cells(fdt, group, "interrupts", 245 data->irq_start + irq0, 0x2, 246 data->irq_start + irq1, 0x2, 247 data->irq_start + irq2, 0x2); 248 249 g_free(node); 250 g_free(group); 251 252 return 0; 253 } 254 255 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 256 { 257 PlatformDevtreeData *data = opaque; 258 bool matched = false; 259 260 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 261 create_devtree_etsec(sbdev, data); 262 matched = true; 263 } 264 265 if (!matched) { 266 error_report("Device %s is not supported by this machine yet.", 267 qdev_fw_name(DEVICE(sbdev))); 268 exit(1); 269 } 270 } 271 272 static void platform_bus_create_devtree(PPCE500MachineState *pms, 273 void *fdt, const char *mpic) 274 { 275 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 276 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 277 const char platcomp[] = "qemu,platform\0simple-bus"; 278 uint64_t addr = pmc->platform_bus_base; 279 uint64_t size = pmc->platform_bus_size; 280 int irq_start = pmc->platform_bus_first_irq; 281 282 /* Create a /platform node that we can put all devices into */ 283 284 qemu_fdt_add_subnode(fdt, node); 285 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 286 287 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 288 address and size */ 289 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 290 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 291 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 292 293 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 294 295 /* Create dt nodes for dynamic devices */ 296 PlatformDevtreeData data = { 297 .fdt = fdt, 298 .mpic = mpic, 299 .irq_start = irq_start, 300 .node = node, 301 .pbus = pms->pbus_dev, 302 }; 303 304 /* Loop through all dynamic sysbus devices and create nodes for them */ 305 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 306 307 g_free(node); 308 } 309 310 static int ppce500_load_device_tree(PPCE500MachineState *pms, 311 hwaddr addr, 312 hwaddr initrd_base, 313 hwaddr initrd_size, 314 hwaddr kernel_base, 315 hwaddr kernel_size, 316 bool dry_run) 317 { 318 MachineState *machine = MACHINE(pms); 319 unsigned int smp_cpus = machine->smp.cpus; 320 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 321 CPUPPCState *env = first_cpu->env_ptr; 322 int ret = -1; 323 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 324 int fdt_size; 325 void *fdt; 326 uint8_t hypercall[16]; 327 uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; 328 uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; 329 int i; 330 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 331 char *soc; 332 char *mpic; 333 uint32_t mpic_ph; 334 uint32_t msi_ph; 335 char *gutil; 336 char *pci; 337 char *msi; 338 uint32_t *pci_map = NULL; 339 int len; 340 uint32_t pci_ranges[14] = 341 { 342 0x2000000, 0x0, pmc->pci_mmio_bus_base, 343 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 344 0x0, 0x20000000, 345 346 0x1000000, 0x0, 0x0, 347 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 348 0x0, 0x10000, 349 }; 350 const char *dtb_file = machine->dtb; 351 const char *toplevel_compat = machine->dt_compatible; 352 353 if (dtb_file) { 354 char *filename; 355 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 356 if (!filename) { 357 goto out; 358 } 359 360 fdt = load_device_tree(filename, &fdt_size); 361 g_free(filename); 362 if (!fdt) { 363 goto out; 364 } 365 goto done; 366 } 367 368 fdt = create_device_tree(&fdt_size); 369 if (fdt == NULL) { 370 goto out; 371 } 372 373 /* Manipulate device tree in memory. */ 374 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 375 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 376 377 qemu_fdt_add_subnode(fdt, "/memory"); 378 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 379 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 380 sizeof(mem_reg_property)); 381 382 qemu_fdt_add_subnode(fdt, "/chosen"); 383 if (initrd_size) { 384 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 385 initrd_base); 386 if (ret < 0) { 387 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 388 } 389 390 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 391 (initrd_base + initrd_size)); 392 if (ret < 0) { 393 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 394 } 395 396 } 397 398 if (kernel_base != -1ULL) { 399 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 400 kernel_base >> 32, kernel_base, 401 kernel_size >> 32, kernel_size); 402 } 403 404 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 405 machine->kernel_cmdline); 406 if (ret < 0) 407 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 408 409 if (kvm_enabled()) { 410 /* Read out host's frequencies */ 411 clock_freq = kvmppc_get_clockfreq(); 412 tb_freq = kvmppc_get_tbfreq(); 413 414 /* indicate KVM hypercall interface */ 415 qemu_fdt_add_subnode(fdt, "/hypervisor"); 416 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 417 "linux,kvm"); 418 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 419 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 420 hypercall, sizeof(hypercall)); 421 /* if KVM supports the idle hcall, set property indicating this */ 422 if (kvmppc_get_hasidle(env)) { 423 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 424 } 425 } 426 427 /* Create CPU nodes */ 428 qemu_fdt_add_subnode(fdt, "/cpus"); 429 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 430 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 431 432 /* We need to generate the cpu nodes in reverse order, so Linux can pick 433 the first node as boot node and be happy */ 434 for (i = smp_cpus - 1; i >= 0; i--) { 435 CPUState *cpu; 436 char *cpu_name; 437 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 438 439 cpu = qemu_get_cpu(i); 440 if (cpu == NULL) { 441 continue; 442 } 443 env = cpu->env_ptr; 444 445 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 446 qemu_fdt_add_subnode(fdt, cpu_name); 447 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 448 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 449 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 450 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 451 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 452 env->dcache_line_size); 453 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 454 env->icache_line_size); 455 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 456 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 457 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 458 if (cpu->cpu_index) { 459 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 460 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 461 "spin-table"); 462 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 463 cpu_release_addr); 464 } else { 465 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 466 } 467 g_free(cpu_name); 468 } 469 470 qemu_fdt_add_subnode(fdt, "/aliases"); 471 /* XXX These should go into their respective devices' code */ 472 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 473 qemu_fdt_add_subnode(fdt, soc); 474 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 475 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 476 sizeof(compatible_sb)); 477 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 478 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 479 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 480 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 481 MPC8544_CCSRBAR_SIZE); 482 /* XXX should contain a reasonable value */ 483 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 484 485 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 486 qemu_fdt_add_subnode(fdt, mpic); 487 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 488 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 489 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 490 0x40000); 491 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 492 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 493 mpic_ph = qemu_fdt_alloc_phandle(fdt); 494 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 495 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 496 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 497 498 /* 499 * We have to generate ser1 first, because Linux takes the first 500 * device it finds in the dt as serial output device. And we generate 501 * devices in reverse order to the dt. 502 */ 503 if (serial_hd(1)) { 504 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 505 soc, mpic, "serial1", 1, false); 506 } 507 508 if (serial_hd(0)) { 509 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 510 soc, mpic, "serial0", 0, true); 511 } 512 513 /* i2c */ 514 dt_i2c_create(fdt, soc, mpic, "i2c"); 515 516 dt_rtc_create(fdt, "i2c", "rtc"); 517 518 519 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 520 MPC8544_UTIL_OFFSET); 521 qemu_fdt_add_subnode(fdt, gutil); 522 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 523 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 524 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 525 g_free(gutil); 526 527 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 528 qemu_fdt_add_subnode(fdt, msi); 529 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 530 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 531 msi_ph = qemu_fdt_alloc_phandle(fdt); 532 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 533 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 534 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 535 0xe0, 0x0, 536 0xe1, 0x0, 537 0xe2, 0x0, 538 0xe3, 0x0, 539 0xe4, 0x0, 540 0xe5, 0x0, 541 0xe6, 0x0, 542 0xe7, 0x0); 543 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 544 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 545 g_free(msi); 546 547 pci = g_strdup_printf("/pci@%llx", 548 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 549 qemu_fdt_add_subnode(fdt, pci); 550 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 551 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 552 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 553 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 554 0x0, 0x7); 555 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 556 pmc->pci_first_slot, pmc->pci_nr_slots, 557 &len); 558 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 559 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 560 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 561 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 562 for (i = 0; i < 14; i++) { 563 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 564 } 565 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 566 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 567 qemu_fdt_setprop_cells(fdt, pci, "reg", 568 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 569 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 570 0, 0x1000); 571 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 572 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 573 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 574 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 575 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 576 g_free(pci); 577 578 if (pmc->has_mpc8xxx_gpio) { 579 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 580 } 581 g_free(soc); 582 583 if (pms->pbus_dev) { 584 platform_bus_create_devtree(pms, fdt, mpic); 585 } 586 g_free(mpic); 587 588 pmc->fixup_devtree(fdt); 589 590 if (toplevel_compat) { 591 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 592 strlen(toplevel_compat) + 1); 593 } 594 595 done: 596 if (!dry_run) { 597 qemu_fdt_dumpdtb(fdt, fdt_size); 598 cpu_physical_memory_write(addr, fdt, fdt_size); 599 } 600 ret = fdt_size; 601 g_free(fdt); 602 603 out: 604 g_free(pci_map); 605 606 return ret; 607 } 608 609 typedef struct DeviceTreeParams { 610 PPCE500MachineState *machine; 611 hwaddr addr; 612 hwaddr initrd_base; 613 hwaddr initrd_size; 614 hwaddr kernel_base; 615 hwaddr kernel_size; 616 Notifier notifier; 617 } DeviceTreeParams; 618 619 static void ppce500_reset_device_tree(void *opaque) 620 { 621 DeviceTreeParams *p = opaque; 622 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 623 p->initrd_size, p->kernel_base, p->kernel_size, 624 false); 625 } 626 627 static void ppce500_init_notify(Notifier *notifier, void *data) 628 { 629 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 630 ppce500_reset_device_tree(p); 631 } 632 633 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 634 hwaddr addr, 635 hwaddr initrd_base, 636 hwaddr initrd_size, 637 hwaddr kernel_base, 638 hwaddr kernel_size) 639 { 640 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 641 p->machine = machine; 642 p->addr = addr; 643 p->initrd_base = initrd_base; 644 p->initrd_size = initrd_size; 645 p->kernel_base = kernel_base; 646 p->kernel_size = kernel_size; 647 648 qemu_register_reset(ppce500_reset_device_tree, p); 649 p->notifier.notify = ppce500_init_notify; 650 qemu_add_machine_init_done_notifier(&p->notifier); 651 652 /* Issue the device tree loader once, so that we get the size of the blob */ 653 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 654 kernel_base, kernel_size, true); 655 } 656 657 /* Create -kernel TLB entries for BookE. */ 658 hwaddr booke206_page_size_to_tlb(uint64_t size) 659 { 660 return 63 - clz64(size / KiB); 661 } 662 663 static int booke206_initial_map_tsize(CPUPPCState *env) 664 { 665 struct boot_info *bi = env->load_info; 666 hwaddr dt_end; 667 int ps; 668 669 /* Our initial TLB entry needs to cover everything from 0 to 670 the device tree top */ 671 dt_end = bi->dt_base + bi->dt_size; 672 ps = booke206_page_size_to_tlb(dt_end) + 1; 673 if (ps & 1) { 674 /* e500v2 can only do even TLB size bits */ 675 ps++; 676 } 677 return ps; 678 } 679 680 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 681 { 682 int tsize; 683 684 tsize = booke206_initial_map_tsize(env); 685 return (1ULL << 10 << tsize); 686 } 687 688 static void mmubooke_create_initial_mapping(CPUPPCState *env) 689 { 690 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 691 hwaddr size; 692 int ps; 693 694 ps = booke206_initial_map_tsize(env); 695 size = (ps << MAS1_TSIZE_SHIFT); 696 tlb->mas1 = MAS1_VALID | size; 697 tlb->mas2 = 0; 698 tlb->mas7_3 = 0; 699 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 700 701 env->tlb_dirty = true; 702 } 703 704 static void ppce500_cpu_reset_sec(void *opaque) 705 { 706 PowerPCCPU *cpu = opaque; 707 CPUState *cs = CPU(cpu); 708 709 cpu_reset(cs); 710 711 cs->exception_index = EXCP_HLT; 712 } 713 714 static void ppce500_cpu_reset(void *opaque) 715 { 716 PowerPCCPU *cpu = opaque; 717 CPUState *cs = CPU(cpu); 718 CPUPPCState *env = &cpu->env; 719 struct boot_info *bi = env->load_info; 720 721 cpu_reset(cs); 722 723 /* Set initial guest state. */ 724 cs->halted = 0; 725 env->gpr[1] = (16 * MiB) - 8; 726 env->gpr[3] = bi->dt_base; 727 env->gpr[4] = 0; 728 env->gpr[5] = 0; 729 env->gpr[6] = EPAPR_MAGIC; 730 env->gpr[7] = mmubooke_initial_mapsize(env); 731 env->gpr[8] = 0; 732 env->gpr[9] = 0; 733 env->nip = bi->entry; 734 mmubooke_create_initial_mapping(env); 735 } 736 737 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 738 IrqLines *irqs) 739 { 740 DeviceState *dev; 741 SysBusDevice *s; 742 int i, j, k; 743 MachineState *machine = MACHINE(pms); 744 unsigned int smp_cpus = machine->smp.cpus; 745 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 746 747 dev = qdev_new(TYPE_OPENPIC); 748 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); 749 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 750 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 751 752 s = SYS_BUS_DEVICE(dev); 753 sysbus_realize_and_unref(s, &error_fatal); 754 755 k = 0; 756 for (i = 0; i < smp_cpus; i++) { 757 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 758 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 759 } 760 } 761 762 return dev; 763 } 764 765 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 766 IrqLines *irqs, Error **errp) 767 { 768 DeviceState *dev; 769 CPUState *cs; 770 771 dev = qdev_new(TYPE_KVM_OPENPIC); 772 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 773 774 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 775 object_unparent(OBJECT(dev)); 776 return NULL; 777 } 778 779 CPU_FOREACH(cs) { 780 if (kvm_openpic_connect_vcpu(dev, cs)) { 781 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 782 __func__); 783 abort(); 784 } 785 } 786 787 return dev; 788 } 789 790 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 791 MemoryRegion *ccsr, 792 IrqLines *irqs) 793 { 794 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 795 DeviceState *dev = NULL; 796 SysBusDevice *s; 797 798 if (kvm_enabled()) { 799 Error *err = NULL; 800 801 if (kvm_kernel_irqchip_allowed()) { 802 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 803 } 804 if (kvm_kernel_irqchip_required() && !dev) { 805 error_reportf_err(err, 806 "kernel_irqchip requested but unavailable: "); 807 exit(1); 808 } 809 } 810 811 if (!dev) { 812 dev = ppce500_init_mpic_qemu(pms, irqs); 813 } 814 815 s = SYS_BUS_DEVICE(dev); 816 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 817 s->mmio[0].memory); 818 819 return dev; 820 } 821 822 static void ppce500_power_off(void *opaque, int line, int on) 823 { 824 if (on) { 825 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 826 } 827 } 828 829 void ppce500_init(MachineState *machine) 830 { 831 MemoryRegion *address_space_mem = get_system_memory(); 832 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 833 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 834 PCIBus *pci_bus; 835 CPUPPCState *env = NULL; 836 uint64_t loadaddr; 837 hwaddr kernel_base = -1LL; 838 int kernel_size = 0; 839 hwaddr dt_base = 0; 840 hwaddr initrd_base = 0; 841 int initrd_size = 0; 842 hwaddr cur_base = 0; 843 char *filename; 844 const char *payload_name; 845 bool kernel_as_payload; 846 hwaddr bios_entry = 0; 847 target_long payload_size; 848 struct boot_info *boot_info; 849 int dt_size; 850 int i; 851 unsigned int smp_cpus = machine->smp.cpus; 852 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 853 * 4 respectively */ 854 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 855 IrqLines *irqs; 856 DeviceState *dev, *mpicdev; 857 CPUPPCState *firstenv = NULL; 858 MemoryRegion *ccsr_addr_space; 859 SysBusDevice *s; 860 PPCE500CCSRState *ccsr; 861 I2CBus *i2c; 862 863 irqs = g_new0(IrqLines, smp_cpus); 864 for (i = 0; i < smp_cpus; i++) { 865 PowerPCCPU *cpu; 866 CPUState *cs; 867 qemu_irq *input; 868 869 cpu = POWERPC_CPU(object_new(machine->cpu_type)); 870 env = &cpu->env; 871 cs = CPU(cpu); 872 873 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 874 error_report("MMU model %i not supported by this machine", 875 env->mmu_model); 876 exit(1); 877 } 878 879 /* 880 * Secondary CPU starts in halted state for now. Needs to change 881 * when implementing non-kernel boot. 882 */ 883 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, 884 &error_fatal); 885 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); 886 887 if (!firstenv) { 888 firstenv = env; 889 } 890 891 input = (qemu_irq *)env->irq_inputs; 892 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 893 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 894 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 895 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 896 897 ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); 898 899 /* Register reset handler */ 900 if (!i) { 901 /* Primary CPU */ 902 struct boot_info *boot_info; 903 boot_info = g_malloc0(sizeof(struct boot_info)); 904 qemu_register_reset(ppce500_cpu_reset, cpu); 905 env->load_info = boot_info; 906 } else { 907 /* Secondary CPUs */ 908 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 909 } 910 } 911 912 env = firstenv; 913 914 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { 915 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); 916 exit(EXIT_FAILURE); 917 } 918 919 /* Register Memory */ 920 memory_region_add_subregion(address_space_mem, 0, machine->ram); 921 922 dev = qdev_new("e500-ccsr"); 923 object_property_add_child(qdev_get_machine(), "e500-ccsr", 924 OBJECT(dev)); 925 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 926 ccsr = CCSR(dev); 927 ccsr_addr_space = &ccsr->ccsr_space; 928 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 929 ccsr_addr_space); 930 931 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 932 g_free(irqs); 933 934 /* Serial */ 935 if (serial_hd(0)) { 936 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 937 0, qdev_get_gpio_in(mpicdev, 42), 399193, 938 serial_hd(0), DEVICE_BIG_ENDIAN); 939 } 940 941 if (serial_hd(1)) { 942 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 943 0, qdev_get_gpio_in(mpicdev, 42), 399193, 944 serial_hd(1), DEVICE_BIG_ENDIAN); 945 } 946 /* I2C */ 947 dev = qdev_new("mpc-i2c"); 948 s = SYS_BUS_DEVICE(dev); 949 sysbus_realize_and_unref(s, &error_fatal); 950 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 951 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 952 sysbus_mmio_get_region(s, 0)); 953 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 954 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); 955 956 957 /* General Utility device */ 958 dev = qdev_new("mpc8544-guts"); 959 s = SYS_BUS_DEVICE(dev); 960 sysbus_realize_and_unref(s, &error_fatal); 961 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 962 sysbus_mmio_get_region(s, 0)); 963 964 /* PCI */ 965 dev = qdev_new("e500-pcihost"); 966 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); 967 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 968 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 969 s = SYS_BUS_DEVICE(dev); 970 sysbus_realize_and_unref(s, &error_fatal); 971 for (i = 0; i < PCI_NUM_PINS; i++) { 972 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 973 } 974 975 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 976 sysbus_mmio_get_region(s, 0)); 977 978 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 979 if (!pci_bus) 980 printf("couldn't create PCI controller!\n"); 981 982 if (pci_bus) { 983 /* Register network interfaces. */ 984 for (i = 0; i < nb_nics; i++) { 985 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 986 } 987 } 988 989 /* Register spinning region */ 990 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 991 992 if (pmc->has_mpc8xxx_gpio) { 993 qemu_irq poweroff_irq; 994 995 dev = qdev_new("mpc8xxx_gpio"); 996 s = SYS_BUS_DEVICE(dev); 997 sysbus_realize_and_unref(s, &error_fatal); 998 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 999 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 1000 sysbus_mmio_get_region(s, 0)); 1001 1002 /* Power Off GPIO at Pin 0 */ 1003 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 1004 qdev_connect_gpio_out(dev, 0, poweroff_irq); 1005 } 1006 1007 /* Platform Bus Device */ 1008 if (pmc->has_platform_bus) { 1009 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1010 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1011 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1012 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1013 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1014 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1015 1016 s = SYS_BUS_DEVICE(pms->pbus_dev); 1017 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1018 int irqn = pmc->platform_bus_first_irq + i; 1019 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1020 } 1021 1022 memory_region_add_subregion(address_space_mem, 1023 pmc->platform_bus_base, 1024 sysbus_mmio_get_region(s, 0)); 1025 } 1026 1027 /* 1028 * Smart firmware defaults ahead! 1029 * 1030 * We follow the following table to select which payload we execute. 1031 * 1032 * -kernel | -bios | payload 1033 * ---------+-------+--------- 1034 * N | Y | u-boot 1035 * N | N | u-boot 1036 * Y | Y | u-boot 1037 * Y | N | kernel 1038 * 1039 * This ensures backwards compatibility with how we used to expose 1040 * -kernel to users but allows them to run through u-boot as well. 1041 */ 1042 kernel_as_payload = false; 1043 if (machine->firmware == NULL) { 1044 if (machine->kernel_filename) { 1045 payload_name = machine->kernel_filename; 1046 kernel_as_payload = true; 1047 } else { 1048 payload_name = "u-boot.e500"; 1049 } 1050 } else { 1051 payload_name = machine->firmware; 1052 } 1053 1054 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1055 if (!filename) { 1056 error_report("could not find firmware/kernel file '%s'", payload_name); 1057 exit(1); 1058 } 1059 1060 payload_size = load_elf(filename, NULL, NULL, NULL, 1061 &bios_entry, &loadaddr, NULL, NULL, 1062 1, PPC_ELF_MACHINE, 0, 0); 1063 if (payload_size < 0) { 1064 /* 1065 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1066 * ePAPR compliant kernel 1067 */ 1068 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1069 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1070 NULL, NULL); 1071 if (payload_size < 0) { 1072 error_report("could not load firmware '%s'", filename); 1073 exit(1); 1074 } 1075 } 1076 1077 g_free(filename); 1078 1079 if (kernel_as_payload) { 1080 kernel_base = loadaddr; 1081 kernel_size = payload_size; 1082 } 1083 1084 cur_base = loadaddr + payload_size; 1085 if (cur_base < 32 * MiB) { 1086 /* u-boot occupies memory up to 32MB, so load blobs above */ 1087 cur_base = 32 * MiB; 1088 } 1089 1090 /* Load bare kernel only if no bios/u-boot has been provided */ 1091 if (machine->kernel_filename && !kernel_as_payload) { 1092 kernel_base = cur_base; 1093 kernel_size = load_image_targphys(machine->kernel_filename, 1094 cur_base, 1095 machine->ram_size - cur_base); 1096 if (kernel_size < 0) { 1097 error_report("could not load kernel '%s'", 1098 machine->kernel_filename); 1099 exit(1); 1100 } 1101 1102 cur_base += kernel_size; 1103 } 1104 1105 /* Load initrd. */ 1106 if (machine->initrd_filename) { 1107 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1108 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1109 machine->ram_size - initrd_base); 1110 1111 if (initrd_size < 0) { 1112 error_report("could not load initial ram disk '%s'", 1113 machine->initrd_filename); 1114 exit(1); 1115 } 1116 1117 cur_base = initrd_base + initrd_size; 1118 } 1119 1120 /* 1121 * Reserve space for dtb behind the kernel image because Linux has a bug 1122 * where it can only handle the dtb if it's within the first 64MB of where 1123 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1124 * ensures enough space between kernel and initrd. 1125 */ 1126 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1127 if (dt_base + DTB_MAX_SIZE > machine->ram_size) { 1128 error_report("not enough memory for device tree"); 1129 exit(1); 1130 } 1131 1132 dt_size = ppce500_prep_device_tree(pms, dt_base, 1133 initrd_base, initrd_size, 1134 kernel_base, kernel_size); 1135 if (dt_size < 0) { 1136 error_report("couldn't load device tree"); 1137 exit(1); 1138 } 1139 assert(dt_size < DTB_MAX_SIZE); 1140 1141 boot_info = env->load_info; 1142 boot_info->entry = bios_entry; 1143 boot_info->dt_base = dt_base; 1144 boot_info->dt_size = dt_size; 1145 } 1146 1147 static void e500_ccsr_initfn(Object *obj) 1148 { 1149 PPCE500CCSRState *ccsr = CCSR(obj); 1150 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1151 MPC8544_CCSRBAR_SIZE); 1152 } 1153 1154 static const TypeInfo e500_ccsr_info = { 1155 .name = TYPE_CCSR, 1156 .parent = TYPE_SYS_BUS_DEVICE, 1157 .instance_size = sizeof(PPCE500CCSRState), 1158 .instance_init = e500_ccsr_initfn, 1159 }; 1160 1161 static const TypeInfo ppce500_info = { 1162 .name = TYPE_PPCE500_MACHINE, 1163 .parent = TYPE_MACHINE, 1164 .abstract = true, 1165 .instance_size = sizeof(PPCE500MachineState), 1166 .class_size = sizeof(PPCE500MachineClass), 1167 }; 1168 1169 static void e500_register_types(void) 1170 { 1171 type_register_static(&e500_ccsr_info); 1172 type_register_static(&ppce500_info); 1173 } 1174 1175 type_init(e500_register_types) 1176