1 /* 2 * QEMU Eyetech AmigaOne/Mai Logic Teron emulation 3 * 4 * Copyright (c) 2023 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 * 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/units.h" 12 #include "qemu/datadir.h" 13 #include "qemu/log.h" 14 #include "qemu/error-report.h" 15 #include "qapi/error.h" 16 #include "hw/ppc/ppc.h" 17 #include "hw/boards.h" 18 #include "hw/loader.h" 19 #include "hw/pci-host/articia.h" 20 #include "hw/isa/vt82c686.h" 21 #include "hw/ide/pci.h" 22 #include "hw/i2c/smbus_eeprom.h" 23 #include "hw/ppc/ppc.h" 24 #include "system/block-backend.h" 25 #include "system/qtest.h" 26 #include "system/reset.h" 27 #include "kvm_ppc.h" 28 #include "elf.h" 29 30 #include <zlib.h> /* for crc32 */ 31 32 #define BUS_FREQ_HZ 100000000 33 34 #define INITRD_MIN_ADDR 0x600000 35 36 /* 37 * Firmware binary available at 38 * https://www.hyperion-entertainment.com/index.php/downloads?view=files&parent=28 39 * then "tail -c 524288 updater.image >u-boot-amigaone.bin" 40 * 41 * BIOS emulator in firmware cannot run QEMU vgabios and hangs on it, use 42 * -device VGA,romfile=VGABIOS-lgpl-latest.bin 43 * from http://www.nongnu.org/vgabios/ instead. 44 */ 45 #define PROM_ADDR 0xfff00000 46 #define PROM_SIZE (512 * KiB) 47 48 /* AmigaOS calls this routine from ROM, use this if no firmware loaded */ 49 static const char dummy_fw[] = { 50 0x54, 0x63, 0xc2, 0x3e, /* srwi r3,r3,8 */ 51 0x7c, 0x63, 0x18, 0xf8, /* not r3,r3 */ 52 0x4e, 0x80, 0x00, 0x20, /* blr */ 53 }; 54 55 #define NVRAM_ADDR 0xfd0e0000 56 #define NVRAM_SIZE (4 * KiB) 57 58 static char default_env[] = 59 "baudrate=115200\0" 60 "stdout=vga\0" 61 "stdin=ps2kbd\0" 62 "bootcmd=boota; menu; run menuboot_cmd\0" 63 "boot1=ide\0" 64 "boot2=cdrom\0" 65 "boota_timeout=3\0" 66 "ide_doreset=on\0" 67 "pci_irqa=9\0" 68 "pci_irqa_select=level\0" 69 "pci_irqb=10\0" 70 "pci_irqb_select=level\0" 71 "pci_irqc=11\0" 72 "pci_irqc_select=level\0" 73 "pci_irqd=7\0" 74 "pci_irqd_select=level\0" 75 "a1ide_irq=1111\0" 76 "a1ide_xfer=FFFF\0"; 77 #define CRC32_DEFAULT_ENV 0xb5548481 78 #define CRC32_ALL_ZEROS 0x603b0489 79 80 #define TYPE_A1_NVRAM "a1-nvram" 81 OBJECT_DECLARE_SIMPLE_TYPE(A1NVRAMState, A1_NVRAM) 82 83 struct A1NVRAMState { 84 SysBusDevice parent_obj; 85 86 MemoryRegion mr; 87 BlockBackend *blk; 88 }; 89 90 static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned int size) 91 { 92 /* read callback not used because of romd mode */ 93 g_assert_not_reached(); 94 } 95 96 static void nvram_write(void *opaque, hwaddr addr, uint64_t val, 97 unsigned int size) 98 { 99 A1NVRAMState *s = opaque; 100 uint8_t *p = memory_region_get_ram_ptr(&s->mr); 101 102 p[addr] = val; 103 if (s->blk) { 104 blk_pwrite(s->blk, addr, 1, &val, 0); 105 } 106 } 107 108 static const MemoryRegionOps nvram_ops = { 109 .read = nvram_read, 110 .write = nvram_write, 111 .endianness = DEVICE_BIG_ENDIAN, 112 .impl = { 113 .min_access_size = 1, 114 .max_access_size = 1, 115 }, 116 }; 117 118 static void nvram_realize(DeviceState *dev, Error **errp) 119 { 120 A1NVRAMState *s = A1_NVRAM(dev); 121 void *p; 122 uint32_t crc, *c; 123 124 memory_region_init_rom_device(&s->mr, NULL, &nvram_ops, s, "nvram", 125 NVRAM_SIZE, &error_fatal); 126 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mr); 127 c = p = memory_region_get_ram_ptr(&s->mr); 128 if (s->blk) { 129 if (blk_getlength(s->blk) != NVRAM_SIZE) { 130 error_setg(errp, "NVRAM backing file size must be %" PRId64 "bytes", 131 NVRAM_SIZE); 132 return; 133 } 134 blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, 135 BLK_PERM_ALL, &error_fatal); 136 if (blk_pread(s->blk, 0, NVRAM_SIZE, p, 0) < 0) { 137 error_setg(errp, "Cannot read NVRAM contents from backing file"); 138 return; 139 } 140 } 141 crc = crc32(0, p + 4, NVRAM_SIZE - 4); 142 if (crc == CRC32_ALL_ZEROS) { /* If env is uninitialized set default */ 143 *c = cpu_to_be32(CRC32_DEFAULT_ENV); 144 /* Also copies terminating \0 as env is terminated by \0\0 */ 145 memcpy(p + 4, default_env, sizeof(default_env)); 146 if (s->blk) { 147 blk_pwrite(s->blk, 0, sizeof(crc) + sizeof(default_env), p, 0); 148 } 149 return; 150 } 151 if (*c == 0) { 152 *c = cpu_to_be32(crc32(0, p + 4, NVRAM_SIZE - 4)); 153 if (s->blk) { 154 blk_pwrite(s->blk, 0, 4, p, 0); 155 } 156 } 157 if (be32_to_cpu(*c) != crc) { 158 warn_report("NVRAM checksum mismatch"); 159 } 160 } 161 162 static const Property nvram_properties[] = { 163 DEFINE_PROP_DRIVE("drive", A1NVRAMState, blk), 164 }; 165 166 static void nvram_class_init(ObjectClass *oc, void *data) 167 { 168 DeviceClass *dc = DEVICE_CLASS(oc); 169 170 dc->realize = nvram_realize; 171 device_class_set_props(dc, nvram_properties); 172 } 173 174 static const TypeInfo nvram_types[] = { 175 { 176 .name = TYPE_A1_NVRAM, 177 .parent = TYPE_SYS_BUS_DEVICE, 178 .instance_size = sizeof(A1NVRAMState), 179 .class_init = nvram_class_init, 180 }, 181 }; 182 DEFINE_TYPES(nvram_types) 183 184 struct boot_info { 185 hwaddr entry; 186 hwaddr stack; 187 hwaddr bd_info; 188 hwaddr initrd_start; 189 hwaddr initrd_end; 190 hwaddr cmdline_start; 191 hwaddr cmdline_end; 192 }; 193 194 /* Board info struct from U-Boot */ 195 struct bd_info { 196 uint32_t bi_memstart; 197 uint32_t bi_memsize; 198 uint32_t bi_flashstart; 199 uint32_t bi_flashsize; 200 uint32_t bi_flashoffset; 201 uint32_t bi_sramstart; 202 uint32_t bi_sramsize; 203 uint32_t bi_bootflags; 204 uint32_t bi_ip_addr; 205 uint8_t bi_enetaddr[6]; 206 uint16_t bi_ethspeed; 207 uint32_t bi_intfreq; 208 uint32_t bi_busfreq; 209 uint32_t bi_baudrate; 210 } QEMU_PACKED; 211 212 static void create_bd_info(hwaddr addr, ram_addr_t ram_size) 213 { 214 struct bd_info *bd = g_new0(struct bd_info, 1); 215 216 bd->bi_memsize = cpu_to_be32(ram_size); 217 bd->bi_flashstart = cpu_to_be32(PROM_ADDR); 218 bd->bi_flashsize = cpu_to_be32(1); /* match what U-Boot detects */ 219 bd->bi_bootflags = cpu_to_be32(1); 220 bd->bi_intfreq = cpu_to_be32(11.5 * BUS_FREQ_HZ); 221 bd->bi_busfreq = cpu_to_be32(BUS_FREQ_HZ); 222 bd->bi_baudrate = cpu_to_be32(115200); 223 224 cpu_physical_memory_write(addr, bd, sizeof(*bd)); 225 } 226 227 static void amigaone_cpu_reset(void *opaque) 228 { 229 PowerPCCPU *cpu = opaque; 230 CPUPPCState *env = &cpu->env; 231 232 cpu_reset(CPU(cpu)); 233 if (env->load_info) { 234 struct boot_info *bi = env->load_info; 235 236 env->gpr[1] = bi->stack; 237 env->gpr[2] = 1024; 238 env->gpr[3] = bi->bd_info; 239 env->gpr[4] = bi->initrd_start; 240 env->gpr[5] = bi->initrd_end; 241 env->gpr[6] = bi->cmdline_start; 242 env->gpr[7] = bi->cmdline_end; 243 env->nip = bi->entry; 244 } 245 cpu_ppc_tb_reset(env); 246 } 247 248 static void fix_spd_data(uint8_t *spd) 249 { 250 uint32_t bank_size = 4 * MiB * spd[31]; 251 uint32_t rows = bank_size / spd[13] / spd[17]; 252 spd[3] = ctz32(rows) - spd[4]; 253 } 254 255 static void amigaone_init(MachineState *machine) 256 { 257 PowerPCCPU *cpu; 258 CPUPPCState *env; 259 MemoryRegion *rom, *pci_mem, *mr; 260 ssize_t sz; 261 PCIBus *pci_bus; 262 Object *via; 263 DeviceState *dev; 264 I2CBus *i2c_bus; 265 uint8_t *spd_data; 266 DriveInfo *di; 267 hwaddr loadaddr; 268 struct boot_info *bi = NULL; 269 270 /* init CPU */ 271 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 272 env = &cpu->env; 273 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 274 error_report("Incompatible CPU, only 6xx bus supported"); 275 exit(1); 276 } 277 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); 278 qemu_register_reset(amigaone_cpu_reset, cpu); 279 280 /* RAM */ 281 if (machine->ram_size > 2 * GiB) { 282 error_report("RAM size more than 2 GiB is not supported"); 283 exit(1); 284 } 285 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 286 if (machine->ram_size < 1 * GiB + 32 * KiB) { 287 /* Firmware uses this area for startup */ 288 mr = g_new(MemoryRegion, 1); 289 memory_region_init_ram(mr, NULL, "init-cache", 32 * KiB, &error_fatal); 290 memory_region_add_subregion(get_system_memory(), 0x40000000, mr); 291 } 292 293 /* nvram */ 294 dev = qdev_new(TYPE_A1_NVRAM); 295 di = drive_get(IF_MTD, 0, 0); 296 if (di) { 297 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di)); 298 } 299 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 300 memory_region_add_subregion(get_system_memory(), NVRAM_ADDR, 301 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 302 303 /* allocate and load firmware */ 304 rom = g_new(MemoryRegion, 1); 305 memory_region_init_rom(rom, NULL, "rom", PROM_SIZE, &error_fatal); 306 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); 307 if (!machine->firmware) { 308 rom_add_blob_fixed("dummy-fw", dummy_fw, sizeof(dummy_fw), 309 PROM_ADDR + PROM_SIZE - 0x80); 310 } else { 311 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, 312 machine->firmware); 313 if (!filename) { 314 error_report("Could not find firmware '%s'", machine->firmware); 315 exit(1); 316 } 317 sz = load_image_targphys(filename, PROM_ADDR, PROM_SIZE); 318 if (sz <= 0 || sz > PROM_SIZE) { 319 error_report("Could not load firmware '%s'", filename); 320 exit(1); 321 } 322 } 323 324 /* Articia S */ 325 dev = sysbus_create_simple(TYPE_ARTICIA, 0xfe000000, NULL); 326 327 i2c_bus = I2C_BUS(qdev_get_child_bus(dev, "smbus")); 328 if (machine->ram_size > 512 * MiB) { 329 spd_data = spd_data_generate(SDR, machine->ram_size / 2); 330 } else { 331 spd_data = spd_data_generate(SDR, machine->ram_size); 332 } 333 fix_spd_data(spd_data); 334 smbus_eeprom_init_one(i2c_bus, 0x51, spd_data); 335 if (machine->ram_size > 512 * MiB) { 336 smbus_eeprom_init_one(i2c_bus, 0x52, spd_data); 337 } 338 339 pci_mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 340 mr = g_new(MemoryRegion, 1); 341 memory_region_init_alias(mr, OBJECT(dev), "pci-mem-low", pci_mem, 342 0, 0xe0000); 343 memory_region_add_subregion(get_system_memory(), 0xfd000000, mr); 344 mr = g_new(MemoryRegion, 1); 345 memory_region_init_alias(mr, OBJECT(dev), "pci-mem-high", pci_mem, 346 0x80000000, 0x7d000000); 347 memory_region_add_subregion(get_system_memory(), 0x80000000, mr); 348 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 349 350 /* VIA VT82c686B South Bridge (multifunction PCI device) */ 351 via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(7, 0), 352 TYPE_VT82C686B_ISA)); 353 object_property_add_alias(OBJECT(machine), "rtc-time", 354 object_resolve_path_component(via, "rtc"), 355 "date"); 356 qdev_connect_gpio_out_named(DEVICE(via), "intr", 0, 357 qdev_get_gpio_in(DEVICE(cpu), 358 PPC6xx_INPUT_INT)); 359 for (int i = 0; i < PCI_NUM_PINS; i++) { 360 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in_named(DEVICE(via), 361 "pirq", i)); 362 } 363 pci_ide_create_devs(PCI_DEVICE(object_resolve_path_component(via, "ide"))); 364 pci_vga_init(pci_bus); 365 366 if (!machine->kernel_filename) { 367 return; 368 } 369 370 /* handle -kernel, -initrd, -append options and emulate U-Boot */ 371 bi = g_new0(struct boot_info, 1); 372 cpu->env.load_info = bi; 373 374 loadaddr = MIN(machine->ram_size, 256 * MiB); 375 bi->bd_info = loadaddr - 8 * MiB; 376 create_bd_info(bi->bd_info, machine->ram_size); 377 bi->stack = bi->bd_info - 64 * KiB - 8; 378 379 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 380 size_t len = strlen(machine->kernel_cmdline); 381 382 loadaddr = bi->bd_info + 1 * MiB; 383 cpu_physical_memory_write(loadaddr, machine->kernel_cmdline, len + 1); 384 bi->cmdline_start = loadaddr; 385 bi->cmdline_end = loadaddr + len + 1; /* including terminating '\0' */ 386 } 387 388 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, 389 &bi->entry, &loadaddr, NULL, NULL, 390 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0); 391 if (sz <= 0) { 392 sz = load_uimage(machine->kernel_filename, &bi->entry, &loadaddr, 393 NULL, NULL, NULL); 394 } 395 if (sz <= 0) { 396 error_report("Could not load kernel '%s'", 397 machine->kernel_filename); 398 exit(1); 399 } 400 loadaddr += sz; 401 402 if (machine->initrd_filename) { 403 loadaddr = ROUND_UP(loadaddr + 4 * MiB, 4 * KiB); 404 loadaddr = MAX(loadaddr, INITRD_MIN_ADDR); 405 sz = load_image_targphys(machine->initrd_filename, loadaddr, 406 bi->bd_info - loadaddr); 407 if (sz <= 0) { 408 error_report("Could not load initrd '%s'", 409 machine->initrd_filename); 410 exit(1); 411 } 412 bi->initrd_start = loadaddr; 413 bi->initrd_end = loadaddr + sz; 414 } 415 } 416 417 static void amigaone_machine_init(MachineClass *mc) 418 { 419 mc->desc = "Eyetech AmigaOne/Mai Logic Teron"; 420 mc->init = amigaone_init; 421 mc->block_default_type = IF_IDE; 422 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2"); 423 mc->default_display = "std"; 424 mc->default_ram_id = "ram"; 425 mc->default_ram_size = 512 * MiB; 426 } 427 428 DEFINE_MACHINE("amigaone", amigaone_machine_init) 429