1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/error-report.h" 19 #include "qemu/range.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 23 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 24 { 25 for (uint16_t i = 0; i < total_vfs; i++) { 26 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 27 object_unparent(OBJECT(vf)); 28 object_unref(OBJECT(vf)); 29 } 30 g_free(dev->exp.sriov_pf.vf); 31 dev->exp.sriov_pf.vf = NULL; 32 } 33 34 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 35 const char *vfname, uint16_t vf_dev_id, 36 uint16_t init_vfs, uint16_t total_vfs, 37 uint16_t vf_offset, uint16_t vf_stride, 38 Error **errp) 39 { 40 BusState *bus = qdev_get_parent_bus(&dev->qdev); 41 int32_t devfn = dev->devfn + vf_offset; 42 uint8_t *cfg = dev->config + offset; 43 uint8_t *wmask; 44 45 if (!pci_is_express(dev)) { 46 error_setg(errp, "PCI Express is required for SR-IOV PF"); 47 return false; 48 } 49 50 if (pci_is_vf(dev)) { 51 error_setg(errp, "a device cannot be a SR-IOV PF and a VF at the same time"); 52 return false; 53 } 54 55 if (total_vfs && 56 (uint32_t)devfn + (uint32_t)(total_vfs - 1) * vf_stride >= PCI_DEVFN_MAX) { 57 error_setg(errp, "VF addr overflows"); 58 return false; 59 } 60 61 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 62 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 63 dev->exp.sriov_cap = offset; 64 dev->exp.sriov_pf.vf = NULL; 65 66 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 67 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 68 69 /* 70 * Mandatory page sizes to support. 71 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 72 * to set more bits: 73 */ 74 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 75 76 /* 77 * Default is to use 4K pages, software can modify it 78 * to any of the supported bits 79 */ 80 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 81 82 /* Set up device ID and initial/total number of VFs available */ 83 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 84 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 85 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 86 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 87 88 /* Write enable control bits */ 89 wmask = dev->wmask + offset; 90 pci_set_word(wmask + PCI_SRIOV_CTRL, 91 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 92 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 93 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 94 95 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 96 97 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 98 99 for (uint16_t i = 0; i < total_vfs; i++) { 100 PCIDevice *vf = pci_new(devfn, vfname); 101 vf->exp.sriov_vf.pf = dev; 102 vf->exp.sriov_vf.vf_number = i; 103 104 if (!qdev_realize(&vf->qdev, bus, errp)) { 105 object_unparent(OBJECT(vf)); 106 object_unref(vf); 107 unparent_vfs(dev, i); 108 return false; 109 } 110 111 /* set vid/did according to sr/iov spec - they are not used */ 112 pci_config_set_vendor_id(vf->config, 0xffff); 113 pci_config_set_device_id(vf->config, 0xffff); 114 115 dev->exp.sriov_pf.vf[i] = vf; 116 devfn += vf_stride; 117 } 118 119 return true; 120 } 121 122 void pcie_sriov_pf_exit(PCIDevice *dev) 123 { 124 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 125 126 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 127 } 128 129 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 130 uint8_t type, dma_addr_t size) 131 { 132 uint32_t addr; 133 uint64_t wmask; 134 uint16_t sriov_cap = dev->exp.sriov_cap; 135 136 assert(sriov_cap > 0); 137 assert(region_num >= 0); 138 assert(region_num < PCI_NUM_REGIONS); 139 assert(region_num != PCI_ROM_SLOT); 140 141 wmask = ~(size - 1); 142 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 143 144 pci_set_long(dev->config + addr, type); 145 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 146 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 147 pci_set_quad(dev->wmask + addr, wmask); 148 pci_set_quad(dev->cmask + addr, ~0ULL); 149 } else { 150 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 151 pci_set_long(dev->cmask + addr, 0xffffffff); 152 } 153 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 154 } 155 156 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, 157 MemoryRegion *memory) 158 { 159 PCIIORegion *r; 160 PCIBus *bus = pci_get_bus(dev); 161 uint8_t type; 162 pcibus_t size = memory_region_size(memory); 163 164 assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */ 165 assert(region_num >= 0); 166 assert(region_num < PCI_NUM_REGIONS); 167 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; 168 169 if (!is_power_of_2(size)) { 170 error_report("%s: PCI region size must be a power" 171 " of two - type=0x%x, size=0x%"FMT_PCIBUS, 172 __func__, type, size); 173 exit(1); 174 } 175 176 r = &dev->io_regions[region_num]; 177 r->memory = memory; 178 r->address_space = 179 type & PCI_BASE_ADDRESS_SPACE_IO 180 ? bus->address_space_io 181 : bus->address_space_mem; 182 r->size = size; 183 r->type = type; 184 185 r->addr = pci_bar_address(dev, region_num, r->type, r->size); 186 if (r->addr != PCI_BAR_UNMAPPED) { 187 memory_region_add_subregion_overlap(r->address_space, 188 r->addr, r->memory, 1); 189 } 190 } 191 192 static void register_vfs(PCIDevice *dev) 193 { 194 uint16_t num_vfs; 195 uint16_t i; 196 uint16_t sriov_cap = dev->exp.sriov_cap; 197 198 assert(sriov_cap > 0); 199 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 200 201 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 202 PCI_FUNC(dev->devfn), num_vfs); 203 for (i = 0; i < num_vfs; i++) { 204 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 205 } 206 207 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0); 208 } 209 210 static void unregister_vfs(PCIDevice *dev) 211 { 212 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 213 uint16_t i; 214 215 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 216 PCI_FUNC(dev->devfn)); 217 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) { 218 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 219 } 220 221 pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xffff); 222 } 223 224 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 225 uint32_t val, int len) 226 { 227 uint32_t off; 228 uint16_t sriov_cap = dev->exp.sriov_cap; 229 230 if (!sriov_cap || address < sriov_cap) { 231 return; 232 } 233 off = address - sriov_cap; 234 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 235 return; 236 } 237 238 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 239 PCI_FUNC(dev->devfn), off, val, len); 240 241 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 242 if (val & PCI_SRIOV_CTRL_VFE) { 243 register_vfs(dev); 244 } else { 245 unregister_vfs(dev); 246 } 247 } else if (range_covers_byte(off, len, PCI_SRIOV_NUM_VF)) { 248 uint8_t *cfg = dev->config + sriov_cap; 249 uint8_t *wmask = dev->wmask + sriov_cap; 250 uint16_t num_vfs = pci_get_word(cfg + PCI_SRIOV_NUM_VF); 251 uint16_t wmask_val = PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI; 252 253 if (num_vfs <= pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)) { 254 wmask_val |= PCI_SRIOV_CTRL_VFE; 255 } 256 257 pci_set_word(wmask + PCI_SRIOV_CTRL, wmask_val); 258 } 259 } 260 261 void pcie_sriov_pf_post_load(PCIDevice *dev) 262 { 263 if (dev->exp.sriov_cap) { 264 register_vfs(dev); 265 } 266 } 267 268 269 /* Reset SR/IOV */ 270 void pcie_sriov_pf_reset(PCIDevice *dev) 271 { 272 uint16_t sriov_cap = dev->exp.sriov_cap; 273 if (!sriov_cap) { 274 return; 275 } 276 277 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 278 unregister_vfs(dev); 279 280 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 281 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_CTRL, 282 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 283 284 /* 285 * Default is to use 4K pages, software can modify it 286 * to any of the supported bits 287 */ 288 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 289 290 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 291 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 292 dev->exp.sriov_pf.vf_bar_type[i]); 293 } 294 } 295 296 /* Add optional supported page sizes to the mask of supported page sizes */ 297 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 298 { 299 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 300 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 301 302 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 303 304 sup_pgsize |= opt_sup_pgsize; 305 306 /* 307 * Make sure the new bits are set, and that system page size 308 * also can be set to any of the new values according to spec: 309 */ 310 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 311 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 312 } 313 314 315 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 316 { 317 assert(pci_is_vf(dev)); 318 return dev->exp.sriov_vf.vf_number; 319 } 320 321 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 322 { 323 return dev->exp.sriov_vf.pf; 324 } 325 326 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 327 { 328 assert(!pci_is_vf(dev)); 329 if (n < pcie_sriov_num_vfs(dev)) { 330 return dev->exp.sriov_pf.vf[n]; 331 } 332 return NULL; 333 } 334 335 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 336 { 337 uint16_t sriov_cap = dev->exp.sriov_cap; 338 uint8_t *cfg = dev->config + sriov_cap; 339 340 return sriov_cap && 341 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ? 342 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0; 343 } 344