1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/error-report.h" 19 #include "qemu/range.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 23 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 24 { 25 for (uint16_t i = 0; i < total_vfs; i++) { 26 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 27 object_unparent(OBJECT(vf)); 28 object_unref(OBJECT(vf)); 29 } 30 g_free(dev->exp.sriov_pf.vf); 31 dev->exp.sriov_pf.vf = NULL; 32 } 33 34 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 35 const char *vfname, uint16_t vf_dev_id, 36 uint16_t init_vfs, uint16_t total_vfs, 37 uint16_t vf_offset, uint16_t vf_stride, 38 Error **errp) 39 { 40 BusState *bus = qdev_get_parent_bus(&dev->qdev); 41 int32_t devfn = dev->devfn + vf_offset; 42 uint8_t *cfg = dev->config + offset; 43 uint8_t *wmask; 44 45 if (total_vfs && 46 (uint32_t)devfn + (uint32_t)(total_vfs - 1) * vf_stride >= PCI_DEVFN_MAX) { 47 error_setg(errp, "VF addr overflows"); 48 return false; 49 } 50 51 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 52 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 53 dev->exp.sriov_cap = offset; 54 dev->exp.sriov_pf.num_vfs = 0; 55 dev->exp.sriov_pf.vf = NULL; 56 57 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 58 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 59 60 /* 61 * Mandatory page sizes to support. 62 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 63 * to set more bits: 64 */ 65 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 66 67 /* 68 * Default is to use 4K pages, software can modify it 69 * to any of the supported bits 70 */ 71 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 72 73 /* Set up device ID and initial/total number of VFs available */ 74 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 75 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 76 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 77 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 78 79 /* Write enable control bits */ 80 wmask = dev->wmask + offset; 81 pci_set_word(wmask + PCI_SRIOV_CTRL, 82 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 83 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 84 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 85 86 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 87 88 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 89 90 for (uint16_t i = 0; i < total_vfs; i++) { 91 PCIDevice *vf = pci_new(devfn, vfname); 92 vf->exp.sriov_vf.pf = dev; 93 vf->exp.sriov_vf.vf_number = i; 94 95 if (!qdev_realize(&vf->qdev, bus, errp)) { 96 unparent_vfs(dev, i); 97 return false; 98 } 99 100 /* set vid/did according to sr/iov spec - they are not used */ 101 pci_config_set_vendor_id(vf->config, 0xffff); 102 pci_config_set_device_id(vf->config, 0xffff); 103 104 dev->exp.sriov_pf.vf[i] = vf; 105 devfn += vf_stride; 106 } 107 108 return true; 109 } 110 111 void pcie_sriov_pf_exit(PCIDevice *dev) 112 { 113 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 114 115 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 116 } 117 118 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 119 uint8_t type, dma_addr_t size) 120 { 121 uint32_t addr; 122 uint64_t wmask; 123 uint16_t sriov_cap = dev->exp.sriov_cap; 124 125 assert(sriov_cap > 0); 126 assert(region_num >= 0); 127 assert(region_num < PCI_NUM_REGIONS); 128 assert(region_num != PCI_ROM_SLOT); 129 130 wmask = ~(size - 1); 131 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 132 133 pci_set_long(dev->config + addr, type); 134 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 135 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 136 pci_set_quad(dev->wmask + addr, wmask); 137 pci_set_quad(dev->cmask + addr, ~0ULL); 138 } else { 139 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 140 pci_set_long(dev->cmask + addr, 0xffffffff); 141 } 142 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 143 } 144 145 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, 146 MemoryRegion *memory) 147 { 148 PCIIORegion *r; 149 PCIBus *bus = pci_get_bus(dev); 150 uint8_t type; 151 pcibus_t size = memory_region_size(memory); 152 153 assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */ 154 assert(region_num >= 0); 155 assert(region_num < PCI_NUM_REGIONS); 156 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; 157 158 if (!is_power_of_2(size)) { 159 error_report("%s: PCI region size must be a power" 160 " of two - type=0x%x, size=0x%"FMT_PCIBUS, 161 __func__, type, size); 162 exit(1); 163 } 164 165 r = &dev->io_regions[region_num]; 166 r->memory = memory; 167 r->address_space = 168 type & PCI_BASE_ADDRESS_SPACE_IO 169 ? bus->address_space_io 170 : bus->address_space_mem; 171 r->size = size; 172 r->type = type; 173 174 r->addr = pci_bar_address(dev, region_num, r->type, r->size); 175 if (r->addr != PCI_BAR_UNMAPPED) { 176 memory_region_add_subregion_overlap(r->address_space, 177 r->addr, r->memory, 1); 178 } 179 } 180 181 static void register_vfs(PCIDevice *dev) 182 { 183 uint16_t num_vfs; 184 uint16_t i; 185 uint16_t sriov_cap = dev->exp.sriov_cap; 186 187 assert(sriov_cap > 0); 188 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 189 if (num_vfs > pci_get_word(dev->config + sriov_cap + PCI_SRIOV_TOTAL_VF)) { 190 return; 191 } 192 193 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 194 PCI_FUNC(dev->devfn), num_vfs); 195 for (i = 0; i < num_vfs; i++) { 196 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 197 } 198 dev->exp.sriov_pf.num_vfs = num_vfs; 199 } 200 201 static void unregister_vfs(PCIDevice *dev) 202 { 203 uint16_t num_vfs = dev->exp.sriov_pf.num_vfs; 204 uint16_t i; 205 206 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 207 PCI_FUNC(dev->devfn), num_vfs); 208 for (i = 0; i < num_vfs; i++) { 209 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 210 } 211 dev->exp.sriov_pf.num_vfs = 0; 212 } 213 214 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 215 uint32_t val, int len) 216 { 217 uint32_t off; 218 uint16_t sriov_cap = dev->exp.sriov_cap; 219 220 if (!sriov_cap || address < sriov_cap) { 221 return; 222 } 223 off = address - sriov_cap; 224 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 225 return; 226 } 227 228 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 229 PCI_FUNC(dev->devfn), off, val, len); 230 231 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 232 if (val & PCI_SRIOV_CTRL_VFE) { 233 register_vfs(dev); 234 } else { 235 unregister_vfs(dev); 236 } 237 } 238 } 239 240 241 /* Reset SR/IOV */ 242 void pcie_sriov_pf_reset(PCIDevice *dev) 243 { 244 uint16_t sriov_cap = dev->exp.sriov_cap; 245 if (!sriov_cap) { 246 return; 247 } 248 249 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 250 unregister_vfs(dev); 251 252 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 253 254 /* 255 * Default is to use 4K pages, software can modify it 256 * to any of the supported bits 257 */ 258 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 259 260 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 261 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 262 dev->exp.sriov_pf.vf_bar_type[i]); 263 } 264 } 265 266 /* Add optional supported page sizes to the mask of supported page sizes */ 267 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 268 { 269 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 270 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 271 272 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 273 274 sup_pgsize |= opt_sup_pgsize; 275 276 /* 277 * Make sure the new bits are set, and that system page size 278 * also can be set to any of the new values according to spec: 279 */ 280 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 281 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 282 } 283 284 285 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 286 { 287 assert(pci_is_vf(dev)); 288 return dev->exp.sriov_vf.vf_number; 289 } 290 291 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 292 { 293 return dev->exp.sriov_vf.pf; 294 } 295 296 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 297 { 298 assert(!pci_is_vf(dev)); 299 if (n < dev->exp.sriov_pf.num_vfs) { 300 return dev->exp.sriov_pf.vf[n]; 301 } 302 return NULL; 303 } 304 305 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 306 { 307 return dev->exp.sriov_pf.num_vfs; 308 } 309