1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/error-report.h" 19 #include "qemu/range.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 23 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 24 { 25 for (uint16_t i = 0; i < total_vfs; i++) { 26 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 27 object_unparent(OBJECT(vf)); 28 object_unref(OBJECT(vf)); 29 } 30 g_free(dev->exp.sriov_pf.vf); 31 dev->exp.sriov_pf.vf = NULL; 32 } 33 34 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 35 const char *vfname, uint16_t vf_dev_id, 36 uint16_t init_vfs, uint16_t total_vfs, 37 uint16_t vf_offset, uint16_t vf_stride, 38 Error **errp) 39 { 40 BusState *bus = qdev_get_parent_bus(&dev->qdev); 41 int32_t devfn = dev->devfn + vf_offset; 42 uint8_t *cfg = dev->config + offset; 43 uint8_t *wmask; 44 45 if (total_vfs) { 46 uint16_t ari_cap = pcie_find_capability(dev, PCI_EXT_CAP_ID_ARI); 47 uint16_t first_vf_devfn = dev->devfn + vf_offset; 48 uint16_t last_vf_devfn = first_vf_devfn + vf_stride * (total_vfs - 1); 49 50 if ((!ari_cap && PCI_SLOT(dev->devfn) != PCI_SLOT(last_vf_devfn)) || 51 last_vf_devfn >= PCI_DEVFN_MAX) { 52 error_setg(errp, "VF function number overflows"); 53 return false; 54 } 55 } 56 57 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 58 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 59 dev->exp.sriov_cap = offset; 60 dev->exp.sriov_pf.num_vfs = 0; 61 dev->exp.sriov_pf.vf = NULL; 62 63 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 64 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 65 66 /* 67 * Mandatory page sizes to support. 68 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 69 * to set more bits: 70 */ 71 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 72 73 /* 74 * Default is to use 4K pages, software can modify it 75 * to any of the supported bits 76 */ 77 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 78 79 /* Set up device ID and initial/total number of VFs available */ 80 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 81 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 82 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 83 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 84 85 /* Write enable control bits */ 86 wmask = dev->wmask + offset; 87 pci_set_word(wmask + PCI_SRIOV_CTRL, 88 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 89 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 90 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 91 92 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 93 94 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 95 96 for (uint16_t i = 0; i < total_vfs; i++) { 97 PCIDevice *vf = pci_new(devfn, vfname); 98 vf->exp.sriov_vf.pf = dev; 99 vf->exp.sriov_vf.vf_number = i; 100 101 if (!qdev_realize(&vf->qdev, bus, errp)) { 102 object_unparent(OBJECT(vf)); 103 object_unref(vf); 104 unparent_vfs(dev, i); 105 return false; 106 } 107 108 /* set vid/did according to sr/iov spec - they are not used */ 109 pci_config_set_vendor_id(vf->config, 0xffff); 110 pci_config_set_device_id(vf->config, 0xffff); 111 112 dev->exp.sriov_pf.vf[i] = vf; 113 devfn += vf_stride; 114 } 115 116 return true; 117 } 118 119 void pcie_sriov_pf_exit(PCIDevice *dev) 120 { 121 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 122 123 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 124 } 125 126 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 127 uint8_t type, dma_addr_t size) 128 { 129 uint32_t addr; 130 uint64_t wmask; 131 uint16_t sriov_cap = dev->exp.sriov_cap; 132 133 assert(sriov_cap > 0); 134 assert(region_num >= 0); 135 assert(region_num < PCI_NUM_REGIONS); 136 assert(region_num != PCI_ROM_SLOT); 137 138 wmask = ~(size - 1); 139 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 140 141 pci_set_long(dev->config + addr, type); 142 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 143 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 144 pci_set_quad(dev->wmask + addr, wmask); 145 pci_set_quad(dev->cmask + addr, ~0ULL); 146 } else { 147 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 148 pci_set_long(dev->cmask + addr, 0xffffffff); 149 } 150 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 151 } 152 153 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, 154 MemoryRegion *memory) 155 { 156 PCIIORegion *r; 157 PCIBus *bus = pci_get_bus(dev); 158 uint8_t type; 159 pcibus_t size = memory_region_size(memory); 160 161 assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */ 162 assert(region_num >= 0); 163 assert(region_num < PCI_NUM_REGIONS); 164 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; 165 166 if (!is_power_of_2(size)) { 167 error_report("%s: PCI region size must be a power" 168 " of two - type=0x%x, size=0x%"FMT_PCIBUS, 169 __func__, type, size); 170 exit(1); 171 } 172 173 r = &dev->io_regions[region_num]; 174 r->memory = memory; 175 r->address_space = 176 type & PCI_BASE_ADDRESS_SPACE_IO 177 ? bus->address_space_io 178 : bus->address_space_mem; 179 r->size = size; 180 r->type = type; 181 182 r->addr = pci_bar_address(dev, region_num, r->type, r->size); 183 if (r->addr != PCI_BAR_UNMAPPED) { 184 memory_region_add_subregion_overlap(r->address_space, 185 r->addr, r->memory, 1); 186 } 187 } 188 189 static void register_vfs(PCIDevice *dev) 190 { 191 uint16_t num_vfs; 192 uint16_t i; 193 uint16_t sriov_cap = dev->exp.sriov_cap; 194 195 assert(sriov_cap > 0); 196 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 197 if (num_vfs > pci_get_word(dev->config + sriov_cap + PCI_SRIOV_TOTAL_VF)) { 198 return; 199 } 200 201 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 202 PCI_FUNC(dev->devfn), num_vfs); 203 for (i = 0; i < num_vfs; i++) { 204 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 205 } 206 dev->exp.sriov_pf.num_vfs = num_vfs; 207 } 208 209 static void unregister_vfs(PCIDevice *dev) 210 { 211 uint16_t num_vfs = dev->exp.sriov_pf.num_vfs; 212 uint16_t i; 213 214 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 215 PCI_FUNC(dev->devfn), num_vfs); 216 for (i = 0; i < num_vfs; i++) { 217 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 218 } 219 dev->exp.sriov_pf.num_vfs = 0; 220 } 221 222 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 223 uint32_t val, int len) 224 { 225 uint32_t off; 226 uint16_t sriov_cap = dev->exp.sriov_cap; 227 228 if (!sriov_cap || address < sriov_cap) { 229 return; 230 } 231 off = address - sriov_cap; 232 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 233 return; 234 } 235 236 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 237 PCI_FUNC(dev->devfn), off, val, len); 238 239 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 240 if (val & PCI_SRIOV_CTRL_VFE) { 241 register_vfs(dev); 242 } else { 243 unregister_vfs(dev); 244 } 245 } 246 } 247 248 249 /* Reset SR/IOV */ 250 void pcie_sriov_pf_reset(PCIDevice *dev) 251 { 252 uint16_t sriov_cap = dev->exp.sriov_cap; 253 if (!sriov_cap) { 254 return; 255 } 256 257 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 258 unregister_vfs(dev); 259 260 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 261 262 /* 263 * Default is to use 4K pages, software can modify it 264 * to any of the supported bits 265 */ 266 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 267 268 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 269 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 270 dev->exp.sriov_pf.vf_bar_type[i]); 271 } 272 } 273 274 /* Add optional supported page sizes to the mask of supported page sizes */ 275 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 276 { 277 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 278 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 279 280 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 281 282 sup_pgsize |= opt_sup_pgsize; 283 284 /* 285 * Make sure the new bits are set, and that system page size 286 * also can be set to any of the new values according to spec: 287 */ 288 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 289 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 290 } 291 292 293 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 294 { 295 assert(pci_is_vf(dev)); 296 return dev->exp.sriov_vf.vf_number; 297 } 298 299 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 300 { 301 return dev->exp.sriov_vf.pf; 302 } 303 304 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 305 { 306 assert(!pci_is_vf(dev)); 307 if (n < dev->exp.sriov_pf.num_vfs) { 308 return dev->exp.sriov_pf.vf[n]; 309 } 310 return NULL; 311 } 312 313 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 314 { 315 return dev->exp.sriov_pf.num_vfs; 316 } 317