1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/error-report.h" 19 #include "qemu/range.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 23 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 24 { 25 for (uint16_t i = 0; i < total_vfs; i++) { 26 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 27 object_unparent(OBJECT(vf)); 28 object_unref(OBJECT(vf)); 29 } 30 g_free(dev->exp.sriov_pf.vf); 31 dev->exp.sriov_pf.vf = NULL; 32 } 33 34 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 35 const char *vfname, uint16_t vf_dev_id, 36 uint16_t init_vfs, uint16_t total_vfs, 37 uint16_t vf_offset, uint16_t vf_stride, 38 Error **errp) 39 { 40 BusState *bus = qdev_get_parent_bus(&dev->qdev); 41 int32_t devfn = dev->devfn + vf_offset; 42 uint8_t *cfg = dev->config + offset; 43 uint8_t *wmask; 44 45 if (!pci_is_express(dev)) { 46 error_setg(errp, "PCI Express is required for SR-IOV PF"); 47 return false; 48 } 49 50 if (pci_is_vf(dev)) { 51 error_setg(errp, "a device cannot be both an SR-IOV PF and a VF"); 52 return false; 53 } 54 55 if (total_vfs) { 56 uint16_t ari_cap = pcie_find_capability(dev, PCI_EXT_CAP_ID_ARI); 57 uint16_t first_vf_devfn = dev->devfn + vf_offset; 58 uint16_t last_vf_devfn = first_vf_devfn + vf_stride * (total_vfs - 1); 59 60 if ((!ari_cap && PCI_SLOT(dev->devfn) != PCI_SLOT(last_vf_devfn)) || 61 last_vf_devfn >= PCI_DEVFN_MAX) { 62 error_setg(errp, "VF function number overflows"); 63 return false; 64 } 65 } 66 67 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 68 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 69 dev->exp.sriov_cap = offset; 70 dev->exp.sriov_pf.vf = NULL; 71 72 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 73 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 74 75 /* 76 * Mandatory page sizes to support. 77 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 78 * to set more bits: 79 */ 80 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 81 82 /* 83 * Default is to use 4K pages, software can modify it 84 * to any of the supported bits 85 */ 86 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 87 88 /* Set up device ID and initial/total number of VFs available */ 89 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 90 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 91 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 92 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 93 94 /* Write enable control bits */ 95 wmask = dev->wmask + offset; 96 pci_set_word(wmask + PCI_SRIOV_CTRL, 97 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 98 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 99 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 100 101 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 102 103 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 104 105 for (uint16_t i = 0; i < total_vfs; i++) { 106 PCIDevice *vf = pci_new(devfn, vfname); 107 vf->exp.sriov_vf.pf = dev; 108 vf->exp.sriov_vf.vf_number = i; 109 110 if (!qdev_realize(&vf->qdev, bus, errp)) { 111 object_unparent(OBJECT(vf)); 112 object_unref(vf); 113 unparent_vfs(dev, i); 114 return false; 115 } 116 117 /* set vid/did according to sr/iov spec - they are not used */ 118 pci_config_set_vendor_id(vf->config, 0xffff); 119 pci_config_set_device_id(vf->config, 0xffff); 120 121 dev->exp.sriov_pf.vf[i] = vf; 122 devfn += vf_stride; 123 } 124 125 return true; 126 } 127 128 void pcie_sriov_pf_exit(PCIDevice *dev) 129 { 130 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 131 132 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 133 } 134 135 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 136 uint8_t type, dma_addr_t size) 137 { 138 uint32_t addr; 139 uint64_t wmask; 140 uint16_t sriov_cap = dev->exp.sriov_cap; 141 142 assert(sriov_cap > 0); 143 assert(region_num >= 0); 144 assert(region_num < PCI_NUM_REGIONS); 145 assert(region_num != PCI_ROM_SLOT); 146 147 wmask = ~(size - 1); 148 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 149 150 pci_set_long(dev->config + addr, type); 151 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 152 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 153 pci_set_quad(dev->wmask + addr, wmask); 154 pci_set_quad(dev->cmask + addr, ~0ULL); 155 } else { 156 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 157 pci_set_long(dev->cmask + addr, 0xffffffff); 158 } 159 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 160 } 161 162 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, 163 MemoryRegion *memory) 164 { 165 PCIIORegion *r; 166 PCIBus *bus = pci_get_bus(dev); 167 uint8_t type; 168 pcibus_t size = memory_region_size(memory); 169 170 assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */ 171 assert(region_num >= 0); 172 assert(region_num < PCI_NUM_REGIONS); 173 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; 174 175 if (!is_power_of_2(size)) { 176 error_report("%s: PCI region size must be a power" 177 " of two - type=0x%x, size=0x%"FMT_PCIBUS, 178 __func__, type, size); 179 exit(1); 180 } 181 182 r = &dev->io_regions[region_num]; 183 r->memory = memory; 184 r->address_space = 185 type & PCI_BASE_ADDRESS_SPACE_IO 186 ? bus->address_space_io 187 : bus->address_space_mem; 188 r->size = size; 189 r->type = type; 190 191 r->addr = pci_bar_address(dev, region_num, r->type, r->size); 192 if (r->addr != PCI_BAR_UNMAPPED) { 193 memory_region_add_subregion_overlap(r->address_space, 194 r->addr, r->memory, 1); 195 } 196 } 197 198 static void clear_ctrl_vfe(PCIDevice *dev) 199 { 200 uint8_t *ctrl = dev->config + dev->exp.sriov_cap + PCI_SRIOV_CTRL; 201 pci_set_word(ctrl, pci_get_word(ctrl) & ~PCI_SRIOV_CTRL_VFE); 202 } 203 204 static void register_vfs(PCIDevice *dev) 205 { 206 uint16_t num_vfs; 207 uint16_t i; 208 uint16_t sriov_cap = dev->exp.sriov_cap; 209 210 assert(sriov_cap > 0); 211 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 212 if (num_vfs > pci_get_word(dev->config + sriov_cap + PCI_SRIOV_TOTAL_VF)) { 213 clear_ctrl_vfe(dev); 214 return; 215 } 216 217 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 218 PCI_FUNC(dev->devfn), num_vfs); 219 for (i = 0; i < num_vfs; i++) { 220 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 221 } 222 } 223 224 static void unregister_vfs(PCIDevice *dev) 225 { 226 uint16_t i; 227 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 228 229 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 230 PCI_FUNC(dev->devfn)); 231 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) { 232 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 233 } 234 } 235 236 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 237 uint32_t val, int len) 238 { 239 uint32_t off; 240 uint16_t sriov_cap = dev->exp.sriov_cap; 241 242 if (!sriov_cap || address < sriov_cap) { 243 return; 244 } 245 off = address - sriov_cap; 246 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 247 return; 248 } 249 250 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 251 PCI_FUNC(dev->devfn), off, val, len); 252 253 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 254 if (val & PCI_SRIOV_CTRL_VFE) { 255 register_vfs(dev); 256 } else { 257 unregister_vfs(dev); 258 } 259 } else if (range_covers_byte(off, len, PCI_SRIOV_NUM_VF)) { 260 clear_ctrl_vfe(dev); 261 unregister_vfs(dev); 262 } 263 } 264 265 void pcie_sriov_pf_post_load(PCIDevice *dev) 266 { 267 if (dev->exp.sriov_cap) { 268 register_vfs(dev); 269 } 270 } 271 272 273 /* Reset SR/IOV */ 274 void pcie_sriov_pf_reset(PCIDevice *dev) 275 { 276 uint16_t sriov_cap = dev->exp.sriov_cap; 277 if (!sriov_cap) { 278 return; 279 } 280 281 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 282 unregister_vfs(dev); 283 284 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 285 286 /* 287 * Default is to use 4K pages, software can modify it 288 * to any of the supported bits 289 */ 290 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 291 292 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 293 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 294 dev->exp.sriov_pf.vf_bar_type[i]); 295 } 296 } 297 298 /* Add optional supported page sizes to the mask of supported page sizes */ 299 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 300 { 301 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 302 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 303 304 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 305 306 sup_pgsize |= opt_sup_pgsize; 307 308 /* 309 * Make sure the new bits are set, and that system page size 310 * also can be set to any of the new values according to spec: 311 */ 312 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 313 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 314 } 315 316 317 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 318 { 319 assert(pci_is_vf(dev)); 320 return dev->exp.sriov_vf.vf_number; 321 } 322 323 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 324 { 325 return dev->exp.sriov_vf.pf; 326 } 327 328 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 329 { 330 assert(!pci_is_vf(dev)); 331 if (n < pcie_sriov_num_vfs(dev)) { 332 return dev->exp.sriov_pf.vf[n]; 333 } 334 return NULL; 335 } 336 337 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 338 { 339 uint16_t sriov_cap = dev->exp.sriov_cap; 340 uint8_t *cfg = dev->config + sriov_cap; 341 342 return sriov_cap && 343 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ? 344 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0; 345 } 346