1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/error-report.h" 19 #include "qemu/range.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 23 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 24 { 25 for (uint16_t i = 0; i < total_vfs; i++) { 26 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 27 object_unparent(OBJECT(vf)); 28 object_unref(OBJECT(vf)); 29 } 30 g_free(dev->exp.sriov_pf.vf); 31 dev->exp.sriov_pf.vf = NULL; 32 } 33 34 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 35 const char *vfname, uint16_t vf_dev_id, 36 uint16_t init_vfs, uint16_t total_vfs, 37 uint16_t vf_offset, uint16_t vf_stride, 38 Error **errp) 39 { 40 BusState *bus = qdev_get_parent_bus(&dev->qdev); 41 int32_t devfn = dev->devfn + vf_offset; 42 uint8_t *cfg = dev->config + offset; 43 uint8_t *wmask; 44 45 if (total_vfs && 46 (uint32_t)devfn + (uint32_t)(total_vfs - 1) * vf_stride >= PCI_DEVFN_MAX) { 47 error_setg(errp, "VF addr overflows"); 48 return false; 49 } 50 51 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 52 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 53 dev->exp.sriov_cap = offset; 54 dev->exp.sriov_pf.vf = NULL; 55 56 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 57 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 58 59 /* 60 * Mandatory page sizes to support. 61 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 62 * to set more bits: 63 */ 64 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 65 66 /* 67 * Default is to use 4K pages, software can modify it 68 * to any of the supported bits 69 */ 70 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 71 72 /* Set up device ID and initial/total number of VFs available */ 73 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 74 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 75 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 76 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 77 78 /* Write enable control bits */ 79 wmask = dev->wmask + offset; 80 pci_set_word(wmask + PCI_SRIOV_CTRL, 81 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 82 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 83 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 84 85 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 86 87 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 88 89 for (uint16_t i = 0; i < total_vfs; i++) { 90 PCIDevice *vf = pci_new(devfn, vfname); 91 vf->exp.sriov_vf.pf = dev; 92 vf->exp.sriov_vf.vf_number = i; 93 94 if (!qdev_realize(&vf->qdev, bus, errp)) { 95 object_unparent(OBJECT(vf)); 96 object_unref(vf); 97 unparent_vfs(dev, i); 98 return false; 99 } 100 101 /* set vid/did according to sr/iov spec - they are not used */ 102 pci_config_set_vendor_id(vf->config, 0xffff); 103 pci_config_set_device_id(vf->config, 0xffff); 104 105 dev->exp.sriov_pf.vf[i] = vf; 106 devfn += vf_stride; 107 } 108 109 return true; 110 } 111 112 void pcie_sriov_pf_exit(PCIDevice *dev) 113 { 114 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 115 116 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 117 } 118 119 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 120 uint8_t type, dma_addr_t size) 121 { 122 uint32_t addr; 123 uint64_t wmask; 124 uint16_t sriov_cap = dev->exp.sriov_cap; 125 126 assert(sriov_cap > 0); 127 assert(region_num >= 0); 128 assert(region_num < PCI_NUM_REGIONS); 129 assert(region_num != PCI_ROM_SLOT); 130 131 wmask = ~(size - 1); 132 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 133 134 pci_set_long(dev->config + addr, type); 135 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 136 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 137 pci_set_quad(dev->wmask + addr, wmask); 138 pci_set_quad(dev->cmask + addr, ~0ULL); 139 } else { 140 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 141 pci_set_long(dev->cmask + addr, 0xffffffff); 142 } 143 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 144 } 145 146 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, 147 MemoryRegion *memory) 148 { 149 PCIIORegion *r; 150 PCIBus *bus = pci_get_bus(dev); 151 uint8_t type; 152 pcibus_t size = memory_region_size(memory); 153 154 assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */ 155 assert(region_num >= 0); 156 assert(region_num < PCI_NUM_REGIONS); 157 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; 158 159 if (!is_power_of_2(size)) { 160 error_report("%s: PCI region size must be a power" 161 " of two - type=0x%x, size=0x%"FMT_PCIBUS, 162 __func__, type, size); 163 exit(1); 164 } 165 166 r = &dev->io_regions[region_num]; 167 r->memory = memory; 168 r->address_space = 169 type & PCI_BASE_ADDRESS_SPACE_IO 170 ? bus->address_space_io 171 : bus->address_space_mem; 172 r->size = size; 173 r->type = type; 174 175 r->addr = pci_bar_address(dev, region_num, r->type, r->size); 176 if (r->addr != PCI_BAR_UNMAPPED) { 177 memory_region_add_subregion_overlap(r->address_space, 178 r->addr, r->memory, 1); 179 } 180 } 181 182 static void register_vfs(PCIDevice *dev) 183 { 184 uint16_t num_vfs; 185 uint16_t i; 186 uint16_t sriov_cap = dev->exp.sriov_cap; 187 188 assert(sriov_cap > 0); 189 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 190 191 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 192 PCI_FUNC(dev->devfn), num_vfs); 193 for (i = 0; i < num_vfs; i++) { 194 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 195 } 196 197 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0); 198 } 199 200 static void unregister_vfs(PCIDevice *dev) 201 { 202 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 203 uint16_t i; 204 205 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 206 PCI_FUNC(dev->devfn)); 207 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) { 208 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 209 } 210 211 pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xffff); 212 } 213 214 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 215 uint32_t val, int len) 216 { 217 uint32_t off; 218 uint16_t sriov_cap = dev->exp.sriov_cap; 219 220 if (!sriov_cap || address < sriov_cap) { 221 return; 222 } 223 off = address - sriov_cap; 224 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 225 return; 226 } 227 228 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 229 PCI_FUNC(dev->devfn), off, val, len); 230 231 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 232 if (val & PCI_SRIOV_CTRL_VFE) { 233 register_vfs(dev); 234 } else { 235 unregister_vfs(dev); 236 } 237 } else if (range_covers_byte(off, len, PCI_SRIOV_NUM_VF)) { 238 uint8_t *cfg = dev->config + sriov_cap; 239 uint8_t *wmask = dev->wmask + sriov_cap; 240 uint16_t num_vfs = pci_get_word(cfg + PCI_SRIOV_NUM_VF); 241 uint16_t wmask_val = PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI; 242 243 if (num_vfs <= pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)) { 244 wmask_val |= PCI_SRIOV_CTRL_VFE; 245 } 246 247 pci_set_word(wmask + PCI_SRIOV_CTRL, wmask_val); 248 } 249 } 250 251 void pcie_sriov_pf_post_load(PCIDevice *dev) 252 { 253 if (dev->exp.sriov_cap) { 254 register_vfs(dev); 255 } 256 } 257 258 259 /* Reset SR/IOV */ 260 void pcie_sriov_pf_reset(PCIDevice *dev) 261 { 262 uint16_t sriov_cap = dev->exp.sriov_cap; 263 if (!sriov_cap) { 264 return; 265 } 266 267 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 268 unregister_vfs(dev); 269 270 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 271 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_CTRL, 272 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 273 274 /* 275 * Default is to use 4K pages, software can modify it 276 * to any of the supported bits 277 */ 278 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 279 280 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 281 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 282 dev->exp.sriov_pf.vf_bar_type[i]); 283 } 284 } 285 286 /* Add optional supported page sizes to the mask of supported page sizes */ 287 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 288 { 289 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 290 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 291 292 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 293 294 sup_pgsize |= opt_sup_pgsize; 295 296 /* 297 * Make sure the new bits are set, and that system page size 298 * also can be set to any of the new values according to spec: 299 */ 300 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 301 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 302 } 303 304 305 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 306 { 307 assert(pci_is_vf(dev)); 308 return dev->exp.sriov_vf.vf_number; 309 } 310 311 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 312 { 313 return dev->exp.sriov_vf.pf; 314 } 315 316 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 317 { 318 assert(!pci_is_vf(dev)); 319 if (n < pcie_sriov_num_vfs(dev)) { 320 return dev->exp.sriov_pf.vf[n]; 321 } 322 return NULL; 323 } 324 325 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 326 { 327 uint16_t sriov_cap = dev->exp.sriov_cap; 328 uint8_t *cfg = dev->config + sriov_cap; 329 330 return sriov_cap && 331 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ? 332 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0; 333 } 334