1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_bus.h" 28 #include "hw/pci/pci_host.h" 29 #include "monitor/monitor.h" 30 #include "net/net.h" 31 #include "sysemu/sysemu.h" 32 #include "hw/loader.h" 33 #include "qemu/range.h" 34 #include "qmp-commands.h" 35 #include "hw/pci/msi.h" 36 #include "hw/pci/msix.h" 37 #include "exec/address-spaces.h" 38 39 //#define DEBUG_PCI 40 #ifdef DEBUG_PCI 41 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 42 #else 43 # define PCI_DPRINTF(format, ...) do { } while (0) 44 #endif 45 46 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); 47 static char *pcibus_get_dev_path(DeviceState *dev); 48 static char *pcibus_get_fw_dev_path(DeviceState *dev); 49 static int pcibus_reset(BusState *qbus); 50 51 static Property pci_props[] = { 52 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 53 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 54 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), 55 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 56 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 57 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present, 58 QEMU_PCI_CAP_SERR_BITNR, true), 59 DEFINE_PROP_END_OF_LIST() 60 }; 61 62 static void pci_bus_class_init(ObjectClass *klass, void *data) 63 { 64 BusClass *k = BUS_CLASS(klass); 65 66 k->print_dev = pcibus_dev_print; 67 k->get_dev_path = pcibus_get_dev_path; 68 k->get_fw_dev_path = pcibus_get_fw_dev_path; 69 k->reset = pcibus_reset; 70 } 71 72 static const TypeInfo pci_bus_info = { 73 .name = TYPE_PCI_BUS, 74 .parent = TYPE_BUS, 75 .instance_size = sizeof(PCIBus), 76 .class_init = pci_bus_class_init, 77 }; 78 79 static const TypeInfo pcie_bus_info = { 80 .name = TYPE_PCIE_BUS, 81 .parent = TYPE_PCI_BUS, 82 }; 83 84 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); 85 static void pci_update_mappings(PCIDevice *d); 86 static void pci_irq_handler(void *opaque, int irq_num, int level); 87 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); 88 static void pci_del_option_rom(PCIDevice *pdev); 89 90 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 91 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 92 93 static QLIST_HEAD(, PCIHostState) pci_host_bridges; 94 95 static const VMStateDescription vmstate_pcibus = { 96 .name = "PCIBUS", 97 .version_id = 1, 98 .minimum_version_id = 1, 99 .minimum_version_id_old = 1, 100 .fields = (VMStateField []) { 101 VMSTATE_INT32_EQUAL(nirq, PCIBus), 102 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t), 103 VMSTATE_END_OF_LIST() 104 } 105 }; 106 static int pci_bar(PCIDevice *d, int reg) 107 { 108 uint8_t type; 109 110 if (reg != PCI_ROM_SLOT) 111 return PCI_BASE_ADDRESS_0 + reg * 4; 112 113 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 114 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 115 } 116 117 static inline int pci_irq_state(PCIDevice *d, int irq_num) 118 { 119 return (d->irq_state >> irq_num) & 0x1; 120 } 121 122 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 123 { 124 d->irq_state &= ~(0x1 << irq_num); 125 d->irq_state |= level << irq_num; 126 } 127 128 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 129 { 130 PCIBus *bus; 131 for (;;) { 132 bus = pci_dev->bus; 133 irq_num = bus->map_irq(pci_dev, irq_num); 134 if (bus->set_irq) 135 break; 136 pci_dev = bus->parent_dev; 137 } 138 bus->irq_count[irq_num] += change; 139 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 140 } 141 142 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 143 { 144 assert(irq_num >= 0); 145 assert(irq_num < bus->nirq); 146 return !!bus->irq_count[irq_num]; 147 } 148 149 /* Update interrupt status bit in config space on interrupt 150 * state change. */ 151 static void pci_update_irq_status(PCIDevice *dev) 152 { 153 if (dev->irq_state) { 154 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 155 } else { 156 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 157 } 158 } 159 160 void pci_device_deassert_intx(PCIDevice *dev) 161 { 162 int i; 163 for (i = 0; i < PCI_NUM_PINS; ++i) { 164 pci_irq_handler(dev, i, 0); 165 } 166 } 167 168 /* 169 * This function is called on #RST and FLR. 170 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 171 */ 172 void pci_device_reset(PCIDevice *dev) 173 { 174 int r; 175 176 qdev_reset_all(&dev->qdev); 177 178 dev->irq_state = 0; 179 pci_update_irq_status(dev); 180 pci_device_deassert_intx(dev); 181 /* Clear all writable bits */ 182 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 183 pci_get_word(dev->wmask + PCI_COMMAND) | 184 pci_get_word(dev->w1cmask + PCI_COMMAND)); 185 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 186 pci_get_word(dev->wmask + PCI_STATUS) | 187 pci_get_word(dev->w1cmask + PCI_STATUS)); 188 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 189 dev->config[PCI_INTERRUPT_LINE] = 0x0; 190 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 191 PCIIORegion *region = &dev->io_regions[r]; 192 if (!region->size) { 193 continue; 194 } 195 196 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 197 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 198 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 199 } else { 200 pci_set_long(dev->config + pci_bar(dev, r), region->type); 201 } 202 } 203 pci_update_mappings(dev); 204 205 msi_reset(dev); 206 msix_reset(dev); 207 } 208 209 /* 210 * Trigger pci bus reset under a given bus. 211 * To be called on RST# assert. 212 */ 213 void pci_bus_reset(PCIBus *bus) 214 { 215 int i; 216 217 for (i = 0; i < bus->nirq; i++) { 218 bus->irq_count[i] = 0; 219 } 220 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 221 if (bus->devices[i]) { 222 pci_device_reset(bus->devices[i]); 223 } 224 } 225 } 226 227 static int pcibus_reset(BusState *qbus) 228 { 229 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); 230 231 /* topology traverse is done by pci_bus_reset(). 232 Tell qbus/qdev walker not to traverse the tree */ 233 return 1; 234 } 235 236 static void pci_host_bus_register(PCIBus *bus, DeviceState *parent) 237 { 238 PCIHostState *host_bridge = PCI_HOST_BRIDGE(parent); 239 240 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 241 } 242 243 PCIBus *pci_find_primary_bus(void) 244 { 245 PCIBus *primary_bus = NULL; 246 PCIHostState *host; 247 248 QLIST_FOREACH(host, &pci_host_bridges, next) { 249 if (primary_bus) { 250 /* We have multiple root buses, refuse to select a primary */ 251 return NULL; 252 } 253 primary_bus = host->bus; 254 } 255 256 return primary_bus; 257 } 258 259 PCIBus *pci_device_root_bus(const PCIDevice *d) 260 { 261 PCIBus *bus = d->bus; 262 263 while ((d = bus->parent_dev) != NULL) { 264 bus = d->bus; 265 } 266 267 return bus; 268 } 269 270 const char *pci_root_bus_path(PCIDevice *dev) 271 { 272 PCIBus *rootbus = pci_device_root_bus(dev); 273 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 274 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 275 276 assert(!rootbus->parent_dev); 277 assert(host_bridge->bus == rootbus); 278 279 if (hc->root_bus_path) { 280 return (*hc->root_bus_path)(host_bridge, rootbus); 281 } 282 283 return rootbus->qbus.name; 284 } 285 286 static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned size) 287 { 288 return -1ULL; 289 } 290 291 static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val, 292 unsigned size) 293 { 294 } 295 296 static const MemoryRegionOps master_abort_mem_ops = { 297 .read = master_abort_mem_read, 298 .write = master_abort_mem_write, 299 .endianness = DEVICE_LITTLE_ENDIAN, 300 }; 301 302 #define MASTER_ABORT_MEM_PRIORITY INT_MIN 303 304 static void pci_bus_init(PCIBus *bus, DeviceState *parent, 305 const char *name, 306 MemoryRegion *address_space_mem, 307 MemoryRegion *address_space_io, 308 uint8_t devfn_min) 309 { 310 assert(PCI_FUNC(devfn_min) == 0); 311 bus->devfn_min = devfn_min; 312 bus->address_space_mem = address_space_mem; 313 bus->address_space_io = address_space_io; 314 315 316 memory_region_init_io(&bus->master_abort_mem, OBJECT(bus), 317 &master_abort_mem_ops, bus, "pci-master-abort", 318 memory_region_size(bus->address_space_mem)); 319 memory_region_add_subregion_overlap(bus->address_space_mem, 320 0, &bus->master_abort_mem, 321 MASTER_ABORT_MEM_PRIORITY); 322 323 /* host bridge */ 324 QLIST_INIT(&bus->child); 325 326 pci_host_bus_register(bus, parent); 327 328 vmstate_register(NULL, -1, &vmstate_pcibus, bus); 329 } 330 331 bool pci_bus_is_express(PCIBus *bus) 332 { 333 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 334 } 335 336 bool pci_bus_is_root(PCIBus *bus) 337 { 338 return !bus->parent_dev; 339 } 340 341 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, 342 const char *name, 343 MemoryRegion *address_space_mem, 344 MemoryRegion *address_space_io, 345 uint8_t devfn_min, const char *typename) 346 { 347 qbus_create_inplace(bus, bus_size, typename, parent, name); 348 pci_bus_init(bus, parent, name, address_space_mem, 349 address_space_io, devfn_min); 350 } 351 352 PCIBus *pci_bus_new(DeviceState *parent, const char *name, 353 MemoryRegion *address_space_mem, 354 MemoryRegion *address_space_io, 355 uint8_t devfn_min, const char *typename) 356 { 357 PCIBus *bus; 358 359 bus = PCI_BUS(qbus_create(typename, parent, name)); 360 pci_bus_init(bus, parent, name, address_space_mem, 361 address_space_io, devfn_min); 362 return bus; 363 } 364 365 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 366 void *irq_opaque, int nirq) 367 { 368 bus->set_irq = set_irq; 369 bus->map_irq = map_irq; 370 bus->irq_opaque = irq_opaque; 371 bus->nirq = nirq; 372 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 373 } 374 375 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev) 376 { 377 bus->qbus.allow_hotplug = 1; 378 bus->hotplug = hotplug; 379 bus->hotplug_qdev = qdev; 380 } 381 382 PCIBus *pci_register_bus(DeviceState *parent, const char *name, 383 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 384 void *irq_opaque, 385 MemoryRegion *address_space_mem, 386 MemoryRegion *address_space_io, 387 uint8_t devfn_min, int nirq, const char *typename) 388 { 389 PCIBus *bus; 390 391 bus = pci_bus_new(parent, name, address_space_mem, 392 address_space_io, devfn_min, typename); 393 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); 394 return bus; 395 } 396 397 int pci_bus_num(PCIBus *s) 398 { 399 if (pci_bus_is_root(s)) 400 return 0; /* pci host bridge */ 401 return s->parent_dev->config[PCI_SECONDARY_BUS]; 402 } 403 404 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) 405 { 406 PCIDevice *s = container_of(pv, PCIDevice, config); 407 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); 408 uint8_t *config; 409 int i; 410 411 assert(size == pci_config_size(s)); 412 config = g_malloc(size); 413 414 qemu_get_buffer(f, config, size); 415 for (i = 0; i < size; ++i) { 416 if ((config[i] ^ s->config[i]) & 417 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 418 g_free(config); 419 return -EINVAL; 420 } 421 } 422 memcpy(s->config, config, size); 423 424 pci_update_mappings(s); 425 if (pc->is_bridge) { 426 PCIBridge *b = PCI_BRIDGE(s); 427 pci_bridge_update_mappings(b); 428 } 429 430 memory_region_set_enabled(&s->bus_master_enable_region, 431 pci_get_word(s->config + PCI_COMMAND) 432 & PCI_COMMAND_MASTER); 433 434 g_free(config); 435 return 0; 436 } 437 438 /* just put buffer */ 439 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) 440 { 441 const uint8_t **v = pv; 442 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 443 qemu_put_buffer(f, *v, size); 444 } 445 446 static VMStateInfo vmstate_info_pci_config = { 447 .name = "pci config", 448 .get = get_pci_config_device, 449 .put = put_pci_config_device, 450 }; 451 452 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) 453 { 454 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 455 uint32_t irq_state[PCI_NUM_PINS]; 456 int i; 457 for (i = 0; i < PCI_NUM_PINS; ++i) { 458 irq_state[i] = qemu_get_be32(f); 459 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 460 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 461 irq_state[i]); 462 return -EINVAL; 463 } 464 } 465 466 for (i = 0; i < PCI_NUM_PINS; ++i) { 467 pci_set_irq_state(s, i, irq_state[i]); 468 } 469 470 return 0; 471 } 472 473 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) 474 { 475 int i; 476 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 477 478 for (i = 0; i < PCI_NUM_PINS; ++i) { 479 qemu_put_be32(f, pci_irq_state(s, i)); 480 } 481 } 482 483 static VMStateInfo vmstate_info_pci_irq_state = { 484 .name = "pci irq state", 485 .get = get_pci_irq_state, 486 .put = put_pci_irq_state, 487 }; 488 489 const VMStateDescription vmstate_pci_device = { 490 .name = "PCIDevice", 491 .version_id = 2, 492 .minimum_version_id = 1, 493 .minimum_version_id_old = 1, 494 .fields = (VMStateField []) { 495 VMSTATE_INT32_LE(version_id, PCIDevice), 496 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 497 vmstate_info_pci_config, 498 PCI_CONFIG_SPACE_SIZE), 499 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 500 vmstate_info_pci_irq_state, 501 PCI_NUM_PINS * sizeof(int32_t)), 502 VMSTATE_END_OF_LIST() 503 } 504 }; 505 506 const VMStateDescription vmstate_pcie_device = { 507 .name = "PCIEDevice", 508 .version_id = 2, 509 .minimum_version_id = 1, 510 .minimum_version_id_old = 1, 511 .fields = (VMStateField []) { 512 VMSTATE_INT32_LE(version_id, PCIDevice), 513 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0, 514 vmstate_info_pci_config, 515 PCIE_CONFIG_SPACE_SIZE), 516 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 517 vmstate_info_pci_irq_state, 518 PCI_NUM_PINS * sizeof(int32_t)), 519 VMSTATE_END_OF_LIST() 520 } 521 }; 522 523 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) 524 { 525 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device; 526 } 527 528 void pci_device_save(PCIDevice *s, QEMUFile *f) 529 { 530 /* Clear interrupt status bit: it is implicit 531 * in irq_state which we are saving. 532 * This makes us compatible with old devices 533 * which never set or clear this bit. */ 534 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 535 vmstate_save_state(f, pci_get_vmstate(s), s); 536 /* Restore the interrupt status bit. */ 537 pci_update_irq_status(s); 538 } 539 540 int pci_device_load(PCIDevice *s, QEMUFile *f) 541 { 542 int ret; 543 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); 544 /* Restore the interrupt status bit. */ 545 pci_update_irq_status(s); 546 return ret; 547 } 548 549 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 550 { 551 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 552 pci_default_sub_vendor_id); 553 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 554 pci_default_sub_device_id); 555 } 556 557 /* 558 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 559 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 560 */ 561 int pci_parse_devaddr(const char *addr, int *domp, int *busp, 562 unsigned int *slotp, unsigned int *funcp) 563 { 564 const char *p; 565 char *e; 566 unsigned long val; 567 unsigned long dom = 0, bus = 0; 568 unsigned int slot = 0; 569 unsigned int func = 0; 570 571 p = addr; 572 val = strtoul(p, &e, 16); 573 if (e == p) 574 return -1; 575 if (*e == ':') { 576 bus = val; 577 p = e + 1; 578 val = strtoul(p, &e, 16); 579 if (e == p) 580 return -1; 581 if (*e == ':') { 582 dom = bus; 583 bus = val; 584 p = e + 1; 585 val = strtoul(p, &e, 16); 586 if (e == p) 587 return -1; 588 } 589 } 590 591 slot = val; 592 593 if (funcp != NULL) { 594 if (*e != '.') 595 return -1; 596 597 p = e + 1; 598 val = strtoul(p, &e, 16); 599 if (e == p) 600 return -1; 601 602 func = val; 603 } 604 605 /* if funcp == NULL func is 0 */ 606 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 607 return -1; 608 609 if (*e) 610 return -1; 611 612 *domp = dom; 613 *busp = bus; 614 *slotp = slot; 615 if (funcp != NULL) 616 *funcp = func; 617 return 0; 618 } 619 620 PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root, const char *devaddr) 621 { 622 int dom, bus; 623 unsigned slot; 624 625 assert(!root->parent_dev); 626 627 if (!root) { 628 fprintf(stderr, "No primary PCI bus\n"); 629 return NULL; 630 } 631 632 if (!devaddr) { 633 *devfnp = -1; 634 return pci_find_bus_nr(root, 0); 635 } 636 637 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { 638 return NULL; 639 } 640 641 if (dom != 0) { 642 fprintf(stderr, "No support for non-zero PCI domains\n"); 643 return NULL; 644 } 645 646 *devfnp = PCI_DEVFN(slot, 0); 647 return pci_find_bus_nr(root, bus); 648 } 649 650 static void pci_init_cmask(PCIDevice *dev) 651 { 652 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 653 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 654 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 655 dev->cmask[PCI_REVISION_ID] = 0xff; 656 dev->cmask[PCI_CLASS_PROG] = 0xff; 657 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 658 dev->cmask[PCI_HEADER_TYPE] = 0xff; 659 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 660 } 661 662 static void pci_init_wmask(PCIDevice *dev) 663 { 664 int config_size = pci_config_size(dev); 665 666 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 667 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 668 pci_set_word(dev->wmask + PCI_COMMAND, 669 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 670 PCI_COMMAND_INTX_DISABLE); 671 if (dev->cap_present & QEMU_PCI_CAP_SERR) { 672 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 673 } 674 675 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 676 config_size - PCI_CONFIG_HEADER_SIZE); 677 } 678 679 static void pci_init_w1cmask(PCIDevice *dev) 680 { 681 /* 682 * Note: It's okay to set w1cmask even for readonly bits as 683 * long as their value is hardwired to 0. 684 */ 685 pci_set_word(dev->w1cmask + PCI_STATUS, 686 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 687 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 688 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 689 } 690 691 static void pci_init_mask_bridge(PCIDevice *d) 692 { 693 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 694 PCI_SEC_LETENCY_TIMER */ 695 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 696 697 /* base and limit */ 698 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 699 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 700 pci_set_word(d->wmask + PCI_MEMORY_BASE, 701 PCI_MEMORY_RANGE_MASK & 0xffff); 702 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 703 PCI_MEMORY_RANGE_MASK & 0xffff); 704 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 705 PCI_PREF_RANGE_MASK & 0xffff); 706 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 707 PCI_PREF_RANGE_MASK & 0xffff); 708 709 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 710 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 711 712 /* Supported memory and i/o types */ 713 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 714 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 715 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 716 PCI_PREF_RANGE_TYPE_64); 717 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 718 PCI_PREF_RANGE_TYPE_64); 719 720 /* 721 * TODO: Bridges default to 10-bit VGA decoding but we currently only 722 * implement 16-bit decoding (no alias support). 723 */ 724 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 725 PCI_BRIDGE_CTL_PARITY | 726 PCI_BRIDGE_CTL_SERR | 727 PCI_BRIDGE_CTL_ISA | 728 PCI_BRIDGE_CTL_VGA | 729 PCI_BRIDGE_CTL_VGA_16BIT | 730 PCI_BRIDGE_CTL_MASTER_ABORT | 731 PCI_BRIDGE_CTL_BUS_RESET | 732 PCI_BRIDGE_CTL_FAST_BACK | 733 PCI_BRIDGE_CTL_DISCARD | 734 PCI_BRIDGE_CTL_SEC_DISCARD | 735 PCI_BRIDGE_CTL_DISCARD_SERR); 736 /* Below does not do anything as we never set this bit, put here for 737 * completeness. */ 738 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 739 PCI_BRIDGE_CTL_DISCARD_STATUS); 740 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 741 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 742 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 743 PCI_PREF_RANGE_TYPE_MASK); 744 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 745 PCI_PREF_RANGE_TYPE_MASK); 746 } 747 748 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) 749 { 750 uint8_t slot = PCI_SLOT(dev->devfn); 751 uint8_t func; 752 753 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 754 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 755 } 756 757 /* 758 * multifunction bit is interpreted in two ways as follows. 759 * - all functions must set the bit to 1. 760 * Example: Intel X53 761 * - function 0 must set the bit, but the rest function (> 0) 762 * is allowed to leave the bit to 0. 763 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 764 * 765 * So OS (at least Linux) checks the bit of only function 0, 766 * and doesn't see the bit of function > 0. 767 * 768 * The below check allows both interpretation. 769 */ 770 if (PCI_FUNC(dev->devfn)) { 771 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 772 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 773 /* function 0 should set multifunction bit */ 774 error_report("PCI: single function device can't be populated " 775 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 776 return -1; 777 } 778 return 0; 779 } 780 781 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 782 return 0; 783 } 784 /* function 0 indicates single function, so function > 0 must be NULL */ 785 for (func = 1; func < PCI_FUNC_MAX; ++func) { 786 if (bus->devices[PCI_DEVFN(slot, func)]) { 787 error_report("PCI: %x.0 indicates single function, " 788 "but %x.%x is already populated.", 789 slot, slot, func); 790 return -1; 791 } 792 } 793 return 0; 794 } 795 796 static void pci_config_alloc(PCIDevice *pci_dev) 797 { 798 int config_size = pci_config_size(pci_dev); 799 800 pci_dev->config = g_malloc0(config_size); 801 pci_dev->cmask = g_malloc0(config_size); 802 pci_dev->wmask = g_malloc0(config_size); 803 pci_dev->w1cmask = g_malloc0(config_size); 804 pci_dev->used = g_malloc0(config_size); 805 } 806 807 static void pci_config_free(PCIDevice *pci_dev) 808 { 809 g_free(pci_dev->config); 810 g_free(pci_dev->cmask); 811 g_free(pci_dev->wmask); 812 g_free(pci_dev->w1cmask); 813 g_free(pci_dev->used); 814 } 815 816 /* -1 for devfn means auto assign */ 817 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus, 818 const char *name, int devfn) 819 { 820 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 821 PCIConfigReadFunc *config_read = pc->config_read; 822 PCIConfigWriteFunc *config_write = pc->config_write; 823 AddressSpace *dma_as; 824 825 if (devfn < 0) { 826 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 827 devfn += PCI_FUNC_MAX) { 828 if (!bus->devices[devfn]) 829 goto found; 830 } 831 error_report("PCI: no slot/function available for %s, all in use", name); 832 return NULL; 833 found: ; 834 } else if (bus->devices[devfn]) { 835 error_report("PCI: slot %d function %d not available for %s, in use by %s", 836 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); 837 return NULL; 838 } 839 840 pci_dev->bus = bus; 841 dma_as = pci_device_iommu_address_space(pci_dev); 842 843 memory_region_init_alias(&pci_dev->bus_master_enable_region, 844 OBJECT(pci_dev), "bus master", 845 dma_as->root, 0, memory_region_size(dma_as->root)); 846 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 847 address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region, 848 name); 849 850 pci_dev->devfn = devfn; 851 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 852 pci_dev->irq_state = 0; 853 pci_config_alloc(pci_dev); 854 855 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 856 pci_config_set_device_id(pci_dev->config, pc->device_id); 857 pci_config_set_revision(pci_dev->config, pc->revision); 858 pci_config_set_class(pci_dev->config, pc->class_id); 859 860 if (!pc->is_bridge) { 861 if (pc->subsystem_vendor_id || pc->subsystem_id) { 862 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 863 pc->subsystem_vendor_id); 864 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 865 pc->subsystem_id); 866 } else { 867 pci_set_default_subsystem_id(pci_dev); 868 } 869 } else { 870 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 871 assert(!pc->subsystem_vendor_id); 872 assert(!pc->subsystem_id); 873 } 874 pci_init_cmask(pci_dev); 875 pci_init_wmask(pci_dev); 876 pci_init_w1cmask(pci_dev); 877 if (pc->is_bridge) { 878 pci_init_mask_bridge(pci_dev); 879 } 880 if (pci_init_multifunction(bus, pci_dev)) { 881 pci_config_free(pci_dev); 882 return NULL; 883 } 884 885 if (!config_read) 886 config_read = pci_default_read_config; 887 if (!config_write) 888 config_write = pci_default_write_config; 889 pci_dev->config_read = config_read; 890 pci_dev->config_write = config_write; 891 bus->devices[devfn] = pci_dev; 892 pci_dev->version_id = 2; /* Current pci device vmstate version */ 893 return pci_dev; 894 } 895 896 static void do_pci_unregister_device(PCIDevice *pci_dev) 897 { 898 pci_dev->bus->devices[pci_dev->devfn] = NULL; 899 pci_config_free(pci_dev); 900 901 address_space_destroy(&pci_dev->bus_master_as); 902 memory_region_destroy(&pci_dev->bus_master_enable_region); 903 } 904 905 static void pci_unregister_io_regions(PCIDevice *pci_dev) 906 { 907 PCIIORegion *r; 908 int i; 909 910 for(i = 0; i < PCI_NUM_REGIONS; i++) { 911 r = &pci_dev->io_regions[i]; 912 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 913 continue; 914 memory_region_del_subregion(r->address_space, r->memory); 915 } 916 917 pci_unregister_vga(pci_dev); 918 } 919 920 static int pci_unregister_device(DeviceState *dev) 921 { 922 PCIDevice *pci_dev = PCI_DEVICE(dev); 923 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 924 925 pci_unregister_io_regions(pci_dev); 926 pci_del_option_rom(pci_dev); 927 928 if (pc->exit) { 929 pc->exit(pci_dev); 930 } 931 932 do_pci_unregister_device(pci_dev); 933 return 0; 934 } 935 936 void pci_register_bar(PCIDevice *pci_dev, int region_num, 937 uint8_t type, MemoryRegion *memory) 938 { 939 PCIIORegion *r; 940 uint32_t addr; 941 uint64_t wmask; 942 pcibus_t size = memory_region_size(memory); 943 944 assert(region_num >= 0); 945 assert(region_num < PCI_NUM_REGIONS); 946 if (size & (size-1)) { 947 fprintf(stderr, "ERROR: PCI region size must be pow2 " 948 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); 949 exit(1); 950 } 951 952 r = &pci_dev->io_regions[region_num]; 953 r->addr = PCI_BAR_UNMAPPED; 954 r->size = size; 955 r->type = type; 956 r->memory = NULL; 957 958 wmask = ~(size - 1); 959 addr = pci_bar(pci_dev, region_num); 960 if (region_num == PCI_ROM_SLOT) { 961 /* ROM enable bit is writable */ 962 wmask |= PCI_ROM_ADDRESS_ENABLE; 963 } 964 pci_set_long(pci_dev->config + addr, type); 965 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 966 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 967 pci_set_quad(pci_dev->wmask + addr, wmask); 968 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 969 } else { 970 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 971 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 972 } 973 pci_dev->io_regions[region_num].memory = memory; 974 pci_dev->io_regions[region_num].address_space 975 = type & PCI_BASE_ADDRESS_SPACE_IO 976 ? pci_dev->bus->address_space_io 977 : pci_dev->bus->address_space_mem; 978 } 979 980 static void pci_update_vga(PCIDevice *pci_dev) 981 { 982 uint16_t cmd; 983 984 if (!pci_dev->has_vga) { 985 return; 986 } 987 988 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 989 990 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 991 cmd & PCI_COMMAND_MEMORY); 992 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 993 cmd & PCI_COMMAND_IO); 994 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 995 cmd & PCI_COMMAND_IO); 996 } 997 998 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 999 MemoryRegion *io_lo, MemoryRegion *io_hi) 1000 { 1001 assert(!pci_dev->has_vga); 1002 1003 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1004 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1005 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, 1006 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1007 1008 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1009 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1010 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1011 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1012 1013 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1014 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1015 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, 1016 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1017 pci_dev->has_vga = true; 1018 1019 pci_update_vga(pci_dev); 1020 } 1021 1022 void pci_unregister_vga(PCIDevice *pci_dev) 1023 { 1024 if (!pci_dev->has_vga) { 1025 return; 1026 } 1027 1028 memory_region_del_subregion(pci_dev->bus->address_space_mem, 1029 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1030 memory_region_del_subregion(pci_dev->bus->address_space_io, 1031 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1032 memory_region_del_subregion(pci_dev->bus->address_space_io, 1033 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1034 pci_dev->has_vga = false; 1035 } 1036 1037 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1038 { 1039 return pci_dev->io_regions[region_num].addr; 1040 } 1041 1042 static pcibus_t pci_bar_address(PCIDevice *d, 1043 int reg, uint8_t type, pcibus_t size) 1044 { 1045 pcibus_t new_addr, last_addr; 1046 int bar = pci_bar(d, reg); 1047 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1048 1049 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1050 if (!(cmd & PCI_COMMAND_IO)) { 1051 return PCI_BAR_UNMAPPED; 1052 } 1053 new_addr = pci_get_long(d->config + bar) & ~(size - 1); 1054 last_addr = new_addr + size - 1; 1055 /* Check if 32 bit BAR wraps around explicitly. 1056 * TODO: make priorities correct and remove this work around. 1057 */ 1058 if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX) { 1059 return PCI_BAR_UNMAPPED; 1060 } 1061 return new_addr; 1062 } 1063 1064 if (!(cmd & PCI_COMMAND_MEMORY)) { 1065 return PCI_BAR_UNMAPPED; 1066 } 1067 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1068 new_addr = pci_get_quad(d->config + bar); 1069 } else { 1070 new_addr = pci_get_long(d->config + bar); 1071 } 1072 /* the ROM slot has a specific enable bit */ 1073 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1074 return PCI_BAR_UNMAPPED; 1075 } 1076 new_addr &= ~(size - 1); 1077 last_addr = new_addr + size - 1; 1078 /* NOTE: we do not support wrapping */ 1079 /* XXX: as we cannot support really dynamic 1080 mappings, we handle specific values as invalid 1081 mappings. */ 1082 if (last_addr <= new_addr || new_addr == 0 || 1083 last_addr == PCI_BAR_UNMAPPED) { 1084 return PCI_BAR_UNMAPPED; 1085 } 1086 1087 /* Now pcibus_t is 64bit. 1088 * Check if 32 bit BAR wraps around explicitly. 1089 * Without this, PC ide doesn't work well. 1090 * TODO: remove this work around. 1091 */ 1092 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1093 return PCI_BAR_UNMAPPED; 1094 } 1095 1096 /* 1097 * OS is allowed to set BAR beyond its addressable 1098 * bits. For example, 32 bit OS can set 64bit bar 1099 * to >4G. Check it. TODO: we might need to support 1100 * it in the future for e.g. PAE. 1101 */ 1102 if (last_addr >= HWADDR_MAX) { 1103 return PCI_BAR_UNMAPPED; 1104 } 1105 1106 return new_addr; 1107 } 1108 1109 static void pci_update_mappings(PCIDevice *d) 1110 { 1111 PCIIORegion *r; 1112 int i; 1113 pcibus_t new_addr; 1114 1115 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1116 r = &d->io_regions[i]; 1117 1118 /* this region isn't registered */ 1119 if (!r->size) 1120 continue; 1121 1122 new_addr = pci_bar_address(d, i, r->type, r->size); 1123 1124 /* This bar isn't changed */ 1125 if (new_addr == r->addr) 1126 continue; 1127 1128 /* now do the real mapping */ 1129 if (r->addr != PCI_BAR_UNMAPPED) { 1130 memory_region_del_subregion(r->address_space, r->memory); 1131 } 1132 r->addr = new_addr; 1133 if (r->addr != PCI_BAR_UNMAPPED) { 1134 memory_region_add_subregion_overlap(r->address_space, 1135 r->addr, r->memory, 1); 1136 } 1137 } 1138 1139 pci_update_vga(d); 1140 } 1141 1142 static inline int pci_irq_disabled(PCIDevice *d) 1143 { 1144 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1145 } 1146 1147 /* Called after interrupt disabled field update in config space, 1148 * assert/deassert interrupts if necessary. 1149 * Gets original interrupt disable bit value (before update). */ 1150 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1151 { 1152 int i, disabled = pci_irq_disabled(d); 1153 if (disabled == was_irq_disabled) 1154 return; 1155 for (i = 0; i < PCI_NUM_PINS; ++i) { 1156 int state = pci_irq_state(d, i); 1157 pci_change_irq_level(d, i, disabled ? -state : state); 1158 } 1159 } 1160 1161 uint32_t pci_default_read_config(PCIDevice *d, 1162 uint32_t address, int len) 1163 { 1164 uint32_t val = 0; 1165 1166 memcpy(&val, d->config + address, len); 1167 return le32_to_cpu(val); 1168 } 1169 1170 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) 1171 { 1172 int i, was_irq_disabled = pci_irq_disabled(d); 1173 1174 for (i = 0; i < l; val >>= 8, ++i) { 1175 uint8_t wmask = d->wmask[addr + i]; 1176 uint8_t w1cmask = d->w1cmask[addr + i]; 1177 assert(!(wmask & w1cmask)); 1178 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1179 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1180 } 1181 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1182 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1183 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1184 range_covers_byte(addr, l, PCI_COMMAND)) 1185 pci_update_mappings(d); 1186 1187 if (range_covers_byte(addr, l, PCI_COMMAND)) { 1188 pci_update_irq_disabled(d, was_irq_disabled); 1189 memory_region_set_enabled(&d->bus_master_enable_region, 1190 pci_get_word(d->config + PCI_COMMAND) 1191 & PCI_COMMAND_MASTER); 1192 } 1193 1194 msi_write_config(d, addr, val, l); 1195 msix_write_config(d, addr, val, l); 1196 } 1197 1198 /***********************************************************/ 1199 /* generic PCI irq support */ 1200 1201 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1202 static void pci_irq_handler(void *opaque, int irq_num, int level) 1203 { 1204 PCIDevice *pci_dev = opaque; 1205 int change; 1206 1207 change = level - pci_irq_state(pci_dev, irq_num); 1208 if (!change) 1209 return; 1210 1211 pci_set_irq_state(pci_dev, irq_num, level); 1212 pci_update_irq_status(pci_dev); 1213 if (pci_irq_disabled(pci_dev)) 1214 return; 1215 pci_change_irq_level(pci_dev, irq_num, change); 1216 } 1217 1218 static inline int pci_intx(PCIDevice *pci_dev) 1219 { 1220 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 1221 } 1222 1223 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1224 { 1225 int intx = pci_intx(pci_dev); 1226 1227 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1228 } 1229 1230 void pci_set_irq(PCIDevice *pci_dev, int level) 1231 { 1232 int intx = pci_intx(pci_dev); 1233 pci_irq_handler(pci_dev, intx, level); 1234 } 1235 1236 /* Special hooks used by device assignment */ 1237 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1238 { 1239 assert(pci_bus_is_root(bus)); 1240 bus->route_intx_to_irq = route_intx_to_irq; 1241 } 1242 1243 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1244 { 1245 PCIBus *bus; 1246 1247 do { 1248 bus = dev->bus; 1249 pin = bus->map_irq(dev, pin); 1250 dev = bus->parent_dev; 1251 } while (dev); 1252 1253 if (!bus->route_intx_to_irq) { 1254 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1255 object_get_typename(OBJECT(bus->qbus.parent))); 1256 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1257 } 1258 1259 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1260 } 1261 1262 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1263 { 1264 return old->mode != new->mode || old->irq != new->irq; 1265 } 1266 1267 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1268 { 1269 PCIDevice *dev; 1270 PCIBus *sec; 1271 int i; 1272 1273 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1274 dev = bus->devices[i]; 1275 if (dev && dev->intx_routing_notifier) { 1276 dev->intx_routing_notifier(dev); 1277 } 1278 } 1279 1280 QLIST_FOREACH(sec, &bus->child, sibling) { 1281 pci_bus_fire_intx_routing_notifier(sec); 1282 } 1283 } 1284 1285 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1286 PCIINTxRoutingNotifier notifier) 1287 { 1288 dev->intx_routing_notifier = notifier; 1289 } 1290 1291 /* 1292 * PCI-to-PCI bridge specification 1293 * 9.1: Interrupt routing. Table 9-1 1294 * 1295 * the PCI Express Base Specification, Revision 2.1 1296 * 2.2.8.1: INTx interrutp signaling - Rules 1297 * the Implementation Note 1298 * Table 2-20 1299 */ 1300 /* 1301 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1302 * 0-origin unlike PCI interrupt pin register. 1303 */ 1304 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1305 { 1306 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS; 1307 } 1308 1309 /***********************************************************/ 1310 /* monitor info on PCI */ 1311 1312 typedef struct { 1313 uint16_t class; 1314 const char *desc; 1315 const char *fw_name; 1316 uint16_t fw_ign_bits; 1317 } pci_class_desc; 1318 1319 static const pci_class_desc pci_class_descriptions[] = 1320 { 1321 { 0x0001, "VGA controller", "display"}, 1322 { 0x0100, "SCSI controller", "scsi"}, 1323 { 0x0101, "IDE controller", "ide"}, 1324 { 0x0102, "Floppy controller", "fdc"}, 1325 { 0x0103, "IPI controller", "ipi"}, 1326 { 0x0104, "RAID controller", "raid"}, 1327 { 0x0106, "SATA controller"}, 1328 { 0x0107, "SAS controller"}, 1329 { 0x0180, "Storage controller"}, 1330 { 0x0200, "Ethernet controller", "ethernet"}, 1331 { 0x0201, "Token Ring controller", "token-ring"}, 1332 { 0x0202, "FDDI controller", "fddi"}, 1333 { 0x0203, "ATM controller", "atm"}, 1334 { 0x0280, "Network controller"}, 1335 { 0x0300, "VGA controller", "display", 0x00ff}, 1336 { 0x0301, "XGA controller"}, 1337 { 0x0302, "3D controller"}, 1338 { 0x0380, "Display controller"}, 1339 { 0x0400, "Video controller", "video"}, 1340 { 0x0401, "Audio controller", "sound"}, 1341 { 0x0402, "Phone"}, 1342 { 0x0403, "Audio controller", "sound"}, 1343 { 0x0480, "Multimedia controller"}, 1344 { 0x0500, "RAM controller", "memory"}, 1345 { 0x0501, "Flash controller", "flash"}, 1346 { 0x0580, "Memory controller"}, 1347 { 0x0600, "Host bridge", "host"}, 1348 { 0x0601, "ISA bridge", "isa"}, 1349 { 0x0602, "EISA bridge", "eisa"}, 1350 { 0x0603, "MC bridge", "mca"}, 1351 { 0x0604, "PCI bridge", "pci"}, 1352 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1353 { 0x0606, "NUBUS bridge", "nubus"}, 1354 { 0x0607, "CARDBUS bridge", "cardbus"}, 1355 { 0x0608, "RACEWAY bridge"}, 1356 { 0x0680, "Bridge"}, 1357 { 0x0700, "Serial port", "serial"}, 1358 { 0x0701, "Parallel port", "parallel"}, 1359 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1360 { 0x0801, "DMA controller", "dma-controller"}, 1361 { 0x0802, "Timer", "timer"}, 1362 { 0x0803, "RTC", "rtc"}, 1363 { 0x0900, "Keyboard", "keyboard"}, 1364 { 0x0901, "Pen", "pen"}, 1365 { 0x0902, "Mouse", "mouse"}, 1366 { 0x0A00, "Dock station", "dock", 0x00ff}, 1367 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1368 { 0x0c00, "Fireware contorller", "fireware"}, 1369 { 0x0c01, "Access bus controller", "access-bus"}, 1370 { 0x0c02, "SSA controller", "ssa"}, 1371 { 0x0c03, "USB controller", "usb"}, 1372 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1373 { 0x0c05, "SMBus"}, 1374 { 0, NULL} 1375 }; 1376 1377 static void pci_for_each_device_under_bus(PCIBus *bus, 1378 void (*fn)(PCIBus *b, PCIDevice *d, 1379 void *opaque), 1380 void *opaque) 1381 { 1382 PCIDevice *d; 1383 int devfn; 1384 1385 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1386 d = bus->devices[devfn]; 1387 if (d) { 1388 fn(bus, d, opaque); 1389 } 1390 } 1391 } 1392 1393 void pci_for_each_device(PCIBus *bus, int bus_num, 1394 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), 1395 void *opaque) 1396 { 1397 bus = pci_find_bus_nr(bus, bus_num); 1398 1399 if (bus) { 1400 pci_for_each_device_under_bus(bus, fn, opaque); 1401 } 1402 } 1403 1404 static const pci_class_desc *get_class_desc(int class) 1405 { 1406 const pci_class_desc *desc; 1407 1408 desc = pci_class_descriptions; 1409 while (desc->desc && class != desc->class) { 1410 desc++; 1411 } 1412 1413 return desc; 1414 } 1415 1416 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); 1417 1418 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) 1419 { 1420 PciMemoryRegionList *head = NULL, *cur_item = NULL; 1421 int i; 1422 1423 for (i = 0; i < PCI_NUM_REGIONS; i++) { 1424 const PCIIORegion *r = &dev->io_regions[i]; 1425 PciMemoryRegionList *region; 1426 1427 if (!r->size) { 1428 continue; 1429 } 1430 1431 region = g_malloc0(sizeof(*region)); 1432 region->value = g_malloc0(sizeof(*region->value)); 1433 1434 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { 1435 region->value->type = g_strdup("io"); 1436 } else { 1437 region->value->type = g_strdup("memory"); 1438 region->value->has_prefetch = true; 1439 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); 1440 region->value->has_mem_type_64 = true; 1441 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); 1442 } 1443 1444 region->value->bar = i; 1445 region->value->address = r->addr; 1446 region->value->size = r->size; 1447 1448 /* XXX: waiting for the qapi to support GSList */ 1449 if (!cur_item) { 1450 head = cur_item = region; 1451 } else { 1452 cur_item->next = region; 1453 cur_item = region; 1454 } 1455 } 1456 1457 return head; 1458 } 1459 1460 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, 1461 int bus_num) 1462 { 1463 PciBridgeInfo *info; 1464 1465 info = g_malloc0(sizeof(*info)); 1466 1467 info->bus.number = dev->config[PCI_PRIMARY_BUS]; 1468 info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; 1469 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; 1470 1471 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range)); 1472 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); 1473 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); 1474 1475 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range)); 1476 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1477 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); 1478 1479 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range)); 1480 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1481 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 1482 1483 if (dev->config[PCI_SECONDARY_BUS] != 0) { 1484 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); 1485 if (child_bus) { 1486 info->has_devices = true; 1487 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); 1488 } 1489 } 1490 1491 return info; 1492 } 1493 1494 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, 1495 int bus_num) 1496 { 1497 const pci_class_desc *desc; 1498 PciDeviceInfo *info; 1499 uint8_t type; 1500 int class; 1501 1502 info = g_malloc0(sizeof(*info)); 1503 info->bus = bus_num; 1504 info->slot = PCI_SLOT(dev->devfn); 1505 info->function = PCI_FUNC(dev->devfn); 1506 1507 class = pci_get_word(dev->config + PCI_CLASS_DEVICE); 1508 info->class_info.q_class = class; 1509 desc = get_class_desc(class); 1510 if (desc->desc) { 1511 info->class_info.has_desc = true; 1512 info->class_info.desc = g_strdup(desc->desc); 1513 } 1514 1515 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); 1516 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); 1517 info->regions = qmp_query_pci_regions(dev); 1518 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : ""); 1519 1520 if (dev->config[PCI_INTERRUPT_PIN] != 0) { 1521 info->has_irq = true; 1522 info->irq = dev->config[PCI_INTERRUPT_LINE]; 1523 } 1524 1525 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1526 if (type == PCI_HEADER_TYPE_BRIDGE) { 1527 info->has_pci_bridge = true; 1528 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); 1529 } 1530 1531 return info; 1532 } 1533 1534 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) 1535 { 1536 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; 1537 PCIDevice *dev; 1538 int devfn; 1539 1540 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1541 dev = bus->devices[devfn]; 1542 if (dev) { 1543 info = g_malloc0(sizeof(*info)); 1544 info->value = qmp_query_pci_device(dev, bus, bus_num); 1545 1546 /* XXX: waiting for the qapi to support GSList */ 1547 if (!cur_item) { 1548 head = cur_item = info; 1549 } else { 1550 cur_item->next = info; 1551 cur_item = info; 1552 } 1553 } 1554 } 1555 1556 return head; 1557 } 1558 1559 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) 1560 { 1561 PciInfo *info = NULL; 1562 1563 bus = pci_find_bus_nr(bus, bus_num); 1564 if (bus) { 1565 info = g_malloc0(sizeof(*info)); 1566 info->bus = bus_num; 1567 info->devices = qmp_query_pci_devices(bus, bus_num); 1568 } 1569 1570 return info; 1571 } 1572 1573 PciInfoList *qmp_query_pci(Error **errp) 1574 { 1575 PciInfoList *info, *head = NULL, *cur_item = NULL; 1576 PCIHostState *host_bridge; 1577 1578 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 1579 info = g_malloc0(sizeof(*info)); 1580 info->value = qmp_query_pci_bus(host_bridge->bus, 0); 1581 1582 /* XXX: waiting for the qapi to support GSList */ 1583 if (!cur_item) { 1584 head = cur_item = info; 1585 } else { 1586 cur_item->next = info; 1587 cur_item = info; 1588 } 1589 } 1590 1591 return head; 1592 } 1593 1594 static const char * const pci_nic_models[] = { 1595 "ne2k_pci", 1596 "i82551", 1597 "i82557b", 1598 "i82559er", 1599 "rtl8139", 1600 "e1000", 1601 "pcnet", 1602 "virtio", 1603 NULL 1604 }; 1605 1606 static const char * const pci_nic_names[] = { 1607 "ne2k_pci", 1608 "i82551", 1609 "i82557b", 1610 "i82559er", 1611 "rtl8139", 1612 "e1000", 1613 "pcnet", 1614 "virtio-net-pci", 1615 NULL 1616 }; 1617 1618 /* Initialize a PCI NIC. */ 1619 /* FIXME callers should check for failure, but don't */ 1620 PCIDevice *pci_nic_init(NICInfo *nd, PCIBus *rootbus, 1621 const char *default_model, 1622 const char *default_devaddr) 1623 { 1624 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; 1625 PCIBus *bus; 1626 int devfn; 1627 PCIDevice *pci_dev; 1628 DeviceState *dev; 1629 int i; 1630 1631 i = qemu_find_nic_model(nd, pci_nic_models, default_model); 1632 if (i < 0) 1633 return NULL; 1634 1635 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr); 1636 if (!bus) { 1637 error_report("Invalid PCI device address %s for device %s", 1638 devaddr, pci_nic_names[i]); 1639 return NULL; 1640 } 1641 1642 pci_dev = pci_create(bus, devfn, pci_nic_names[i]); 1643 dev = &pci_dev->qdev; 1644 qdev_set_nic_properties(dev, nd); 1645 if (qdev_init(dev) < 0) 1646 return NULL; 1647 return pci_dev; 1648 } 1649 1650 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, 1651 const char *default_model, 1652 const char *default_devaddr) 1653 { 1654 PCIDevice *res; 1655 1656 if (qemu_show_nic_models(nd->model, pci_nic_models)) 1657 exit(0); 1658 1659 res = pci_nic_init(nd, rootbus, default_model, default_devaddr); 1660 if (!res) 1661 exit(1); 1662 return res; 1663 } 1664 1665 PCIDevice *pci_vga_init(PCIBus *bus) 1666 { 1667 switch (vga_interface_type) { 1668 case VGA_CIRRUS: 1669 return pci_create_simple(bus, -1, "cirrus-vga"); 1670 case VGA_QXL: 1671 return pci_create_simple(bus, -1, "qxl-vga"); 1672 case VGA_STD: 1673 return pci_create_simple(bus, -1, "VGA"); 1674 case VGA_VMWARE: 1675 return pci_create_simple(bus, -1, "vmware-svga"); 1676 case VGA_NONE: 1677 default: /* Other non-PCI types. Checking for unsupported types is already 1678 done in vl.c. */ 1679 return NULL; 1680 } 1681 } 1682 1683 /* Whether a given bus number is in range of the secondary 1684 * bus of the given bridge device. */ 1685 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 1686 { 1687 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 1688 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 1689 dev->config[PCI_SECONDARY_BUS] < bus_num && 1690 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 1691 } 1692 1693 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 1694 { 1695 PCIBus *sec; 1696 1697 if (!bus) { 1698 return NULL; 1699 } 1700 1701 if (pci_bus_num(bus) == bus_num) { 1702 return bus; 1703 } 1704 1705 /* Consider all bus numbers in range for the host pci bridge. */ 1706 if (!pci_bus_is_root(bus) && 1707 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 1708 return NULL; 1709 } 1710 1711 /* try child bus */ 1712 for (; bus; bus = sec) { 1713 QLIST_FOREACH(sec, &bus->child, sibling) { 1714 assert(!pci_bus_is_root(sec)); 1715 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) { 1716 return sec; 1717 } 1718 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 1719 break; 1720 } 1721 } 1722 } 1723 1724 return NULL; 1725 } 1726 1727 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 1728 { 1729 bus = pci_find_bus_nr(bus, bus_num); 1730 1731 if (!bus) 1732 return NULL; 1733 1734 return bus->devices[devfn]; 1735 } 1736 1737 static int pci_qdev_init(DeviceState *qdev) 1738 { 1739 PCIDevice *pci_dev = (PCIDevice *)qdev; 1740 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1741 PCIBus *bus; 1742 int rc; 1743 bool is_default_rom; 1744 1745 /* initialize cap_present for pci_is_express() and pci_config_size() */ 1746 if (pc->is_express) { 1747 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1748 } 1749 1750 bus = PCI_BUS(qdev_get_parent_bus(qdev)); 1751 pci_dev = do_pci_register_device(pci_dev, bus, 1752 object_get_typename(OBJECT(qdev)), 1753 pci_dev->devfn); 1754 if (pci_dev == NULL) 1755 return -1; 1756 if (qdev->hotplugged && pc->no_hotplug) { 1757 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); 1758 do_pci_unregister_device(pci_dev); 1759 return -1; 1760 } 1761 if (pc->init) { 1762 rc = pc->init(pci_dev); 1763 if (rc != 0) { 1764 do_pci_unregister_device(pci_dev); 1765 return rc; 1766 } 1767 } 1768 1769 /* rom loading */ 1770 is_default_rom = false; 1771 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 1772 pci_dev->romfile = g_strdup(pc->romfile); 1773 is_default_rom = true; 1774 } 1775 pci_add_option_rom(pci_dev, is_default_rom); 1776 1777 if (bus->hotplug) { 1778 /* Let buses differentiate between hotplug and when device is 1779 * enabled during qemu machine creation. */ 1780 rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1781 qdev->hotplugged ? PCI_HOTPLUG_ENABLED: 1782 PCI_COLDPLUG_ENABLED); 1783 if (rc != 0) { 1784 int r = pci_unregister_device(&pci_dev->qdev); 1785 assert(!r); 1786 return rc; 1787 } 1788 } 1789 return 0; 1790 } 1791 1792 static int pci_unplug_device(DeviceState *qdev) 1793 { 1794 PCIDevice *dev = PCI_DEVICE(qdev); 1795 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1796 1797 if (pc->no_hotplug) { 1798 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); 1799 return -1; 1800 } 1801 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 1802 PCI_HOTPLUG_DISABLED); 1803 } 1804 1805 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, 1806 const char *name) 1807 { 1808 DeviceState *dev; 1809 1810 dev = qdev_create(&bus->qbus, name); 1811 qdev_prop_set_int32(dev, "addr", devfn); 1812 qdev_prop_set_bit(dev, "multifunction", multifunction); 1813 return PCI_DEVICE(dev); 1814 } 1815 1816 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 1817 bool multifunction, 1818 const char *name) 1819 { 1820 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); 1821 qdev_init_nofail(&dev->qdev); 1822 return dev; 1823 } 1824 1825 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) 1826 { 1827 return pci_create_multifunction(bus, devfn, false, name); 1828 } 1829 1830 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 1831 { 1832 return pci_create_simple_multifunction(bus, devfn, false, name); 1833 } 1834 1835 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 1836 { 1837 int offset = PCI_CONFIG_HEADER_SIZE; 1838 int i; 1839 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 1840 if (pdev->used[i]) 1841 offset = i + 1; 1842 else if (i - offset + 1 == size) 1843 return offset; 1844 } 1845 return 0; 1846 } 1847 1848 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 1849 uint8_t *prev_p) 1850 { 1851 uint8_t next, prev; 1852 1853 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 1854 return 0; 1855 1856 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1857 prev = next + PCI_CAP_LIST_NEXT) 1858 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 1859 break; 1860 1861 if (prev_p) 1862 *prev_p = prev; 1863 return next; 1864 } 1865 1866 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 1867 { 1868 uint8_t next, prev, found = 0; 1869 1870 if (!(pdev->used[offset])) { 1871 return 0; 1872 } 1873 1874 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 1875 1876 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 1877 prev = next + PCI_CAP_LIST_NEXT) { 1878 if (next <= offset && next > found) { 1879 found = next; 1880 } 1881 } 1882 return found; 1883 } 1884 1885 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 1886 This is needed for an option rom which is used for more than one device. */ 1887 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) 1888 { 1889 uint16_t vendor_id; 1890 uint16_t device_id; 1891 uint16_t rom_vendor_id; 1892 uint16_t rom_device_id; 1893 uint16_t rom_magic; 1894 uint16_t pcir_offset; 1895 uint8_t checksum; 1896 1897 /* Words in rom data are little endian (like in PCI configuration), 1898 so they can be read / written with pci_get_word / pci_set_word. */ 1899 1900 /* Only a valid rom will be patched. */ 1901 rom_magic = pci_get_word(ptr); 1902 if (rom_magic != 0xaa55) { 1903 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 1904 return; 1905 } 1906 pcir_offset = pci_get_word(ptr + 0x18); 1907 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 1908 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 1909 return; 1910 } 1911 1912 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 1913 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 1914 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 1915 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 1916 1917 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 1918 vendor_id, device_id, rom_vendor_id, rom_device_id); 1919 1920 checksum = ptr[6]; 1921 1922 if (vendor_id != rom_vendor_id) { 1923 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 1924 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 1925 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 1926 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1927 ptr[6] = checksum; 1928 pci_set_word(ptr + pcir_offset + 4, vendor_id); 1929 } 1930 1931 if (device_id != rom_device_id) { 1932 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 1933 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 1934 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 1935 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 1936 ptr[6] = checksum; 1937 pci_set_word(ptr + pcir_offset + 6, device_id); 1938 } 1939 } 1940 1941 /* Add an option rom for the device */ 1942 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) 1943 { 1944 int size; 1945 char *path; 1946 void *ptr; 1947 char name[32]; 1948 const VMStateDescription *vmsd; 1949 1950 if (!pdev->romfile) 1951 return 0; 1952 if (strlen(pdev->romfile) == 0) 1953 return 0; 1954 1955 if (!pdev->rom_bar) { 1956 /* 1957 * Load rom via fw_cfg instead of creating a rom bar, 1958 * for 0.11 compatibility. 1959 */ 1960 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 1961 if (class == 0x0300) { 1962 rom_add_vga(pdev->romfile); 1963 } else { 1964 rom_add_option(pdev->romfile, -1); 1965 } 1966 return 0; 1967 } 1968 1969 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 1970 if (path == NULL) { 1971 path = g_strdup(pdev->romfile); 1972 } 1973 1974 size = get_image_size(path); 1975 if (size < 0) { 1976 error_report("%s: failed to find romfile \"%s\"", 1977 __func__, pdev->romfile); 1978 g_free(path); 1979 return -1; 1980 } else if (size == 0) { 1981 error_report("%s: ignoring empty romfile \"%s\"", 1982 __func__, pdev->romfile); 1983 g_free(path); 1984 return -1; 1985 } 1986 if (size & (size - 1)) { 1987 size = 1 << qemu_fls(size); 1988 } 1989 1990 vmsd = qdev_get_vmsd(DEVICE(pdev)); 1991 1992 if (vmsd) { 1993 snprintf(name, sizeof(name), "%s.rom", vmsd->name); 1994 } else { 1995 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); 1996 } 1997 pdev->has_rom = true; 1998 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size); 1999 vmstate_register_ram(&pdev->rom, &pdev->qdev); 2000 ptr = memory_region_get_ram_ptr(&pdev->rom); 2001 load_image(path, ptr); 2002 g_free(path); 2003 2004 if (is_default_rom) { 2005 /* Only the default rom images will be patched (if needed). */ 2006 pci_patch_ids(pdev, ptr, size); 2007 } 2008 2009 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2010 2011 return 0; 2012 } 2013 2014 static void pci_del_option_rom(PCIDevice *pdev) 2015 { 2016 if (!pdev->has_rom) 2017 return; 2018 2019 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2020 memory_region_destroy(&pdev->rom); 2021 pdev->has_rom = false; 2022 } 2023 2024 /* 2025 * if !offset 2026 * Reserve space and add capability to the linked list in pci config space 2027 * 2028 * if offset = 0, 2029 * Find and reserve space and add capability to the linked list 2030 * in pci config space */ 2031 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2032 uint8_t offset, uint8_t size) 2033 { 2034 uint8_t *config; 2035 int i, overlapping_cap; 2036 2037 if (!offset) { 2038 offset = pci_find_space(pdev, size); 2039 if (!offset) { 2040 return -ENOSPC; 2041 } 2042 } else { 2043 /* Verify that capabilities don't overlap. Note: device assignment 2044 * depends on this check to verify that the device is not broken. 2045 * Should never trigger for emulated devices, but it's helpful 2046 * for debugging these. */ 2047 for (i = offset; i < offset + size; i++) { 2048 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2049 if (overlapping_cap) { 2050 fprintf(stderr, "ERROR: %s:%02x:%02x.%x " 2051 "Attempt to add PCI capability %x at offset " 2052 "%x overlaps existing capability %x at offset %x\n", 2053 pci_root_bus_path(pdev), pci_bus_num(pdev->bus), 2054 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2055 cap_id, offset, overlapping_cap, i); 2056 return -EINVAL; 2057 } 2058 } 2059 } 2060 2061 config = pdev->config + offset; 2062 config[PCI_CAP_LIST_ID] = cap_id; 2063 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2064 pdev->config[PCI_CAPABILITY_LIST] = offset; 2065 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2066 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2067 /* Make capability read-only by default */ 2068 memset(pdev->wmask + offset, 0, size); 2069 /* Check capability by default */ 2070 memset(pdev->cmask + offset, 0xFF, size); 2071 return offset; 2072 } 2073 2074 /* Unlink capability from the pci config space. */ 2075 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2076 { 2077 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2078 if (!offset) 2079 return; 2080 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2081 /* Make capability writable again */ 2082 memset(pdev->wmask + offset, 0xff, size); 2083 memset(pdev->w1cmask + offset, 0, size); 2084 /* Clear cmask as device-specific registers can't be checked */ 2085 memset(pdev->cmask + offset, 0, size); 2086 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2087 2088 if (!pdev->config[PCI_CAPABILITY_LIST]) 2089 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2090 } 2091 2092 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2093 { 2094 return pci_find_capability_list(pdev, cap_id, NULL); 2095 } 2096 2097 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) 2098 { 2099 PCIDevice *d = (PCIDevice *)dev; 2100 const pci_class_desc *desc; 2101 char ctxt[64]; 2102 PCIIORegion *r; 2103 int i, class; 2104 2105 class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2106 desc = pci_class_descriptions; 2107 while (desc->desc && class != desc->class) 2108 desc++; 2109 if (desc->desc) { 2110 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); 2111 } else { 2112 snprintf(ctxt, sizeof(ctxt), "Class %04x", class); 2113 } 2114 2115 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " 2116 "pci id %04x:%04x (sub %04x:%04x)\n", 2117 indent, "", ctxt, pci_bus_num(d->bus), 2118 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 2119 pci_get_word(d->config + PCI_VENDOR_ID), 2120 pci_get_word(d->config + PCI_DEVICE_ID), 2121 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), 2122 pci_get_word(d->config + PCI_SUBSYSTEM_ID)); 2123 for (i = 0; i < PCI_NUM_REGIONS; i++) { 2124 r = &d->io_regions[i]; 2125 if (!r->size) 2126 continue; 2127 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS 2128 " [0x%"FMT_PCIBUS"]\n", 2129 indent, "", 2130 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", 2131 r->addr, r->addr + r->size - 1); 2132 } 2133 } 2134 2135 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2136 { 2137 PCIDevice *d = (PCIDevice *)dev; 2138 const char *name = NULL; 2139 const pci_class_desc *desc = pci_class_descriptions; 2140 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2141 2142 while (desc->desc && 2143 (class & ~desc->fw_ign_bits) != 2144 (desc->class & ~desc->fw_ign_bits)) { 2145 desc++; 2146 } 2147 2148 if (desc->desc) { 2149 name = desc->fw_name; 2150 } 2151 2152 if (name) { 2153 pstrcpy(buf, len, name); 2154 } else { 2155 snprintf(buf, len, "pci%04x,%04x", 2156 pci_get_word(d->config + PCI_VENDOR_ID), 2157 pci_get_word(d->config + PCI_DEVICE_ID)); 2158 } 2159 2160 return buf; 2161 } 2162 2163 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2164 { 2165 PCIDevice *d = (PCIDevice *)dev; 2166 char path[50], name[33]; 2167 int off; 2168 2169 off = snprintf(path, sizeof(path), "%s@%x", 2170 pci_dev_fw_name(dev, name, sizeof name), 2171 PCI_SLOT(d->devfn)); 2172 if (PCI_FUNC(d->devfn)) 2173 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); 2174 return g_strdup(path); 2175 } 2176 2177 static char *pcibus_get_dev_path(DeviceState *dev) 2178 { 2179 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2180 PCIDevice *t; 2181 int slot_depth; 2182 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2183 * 00 is added here to make this format compatible with 2184 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2185 * Slot.Function list specifies the slot and function numbers for all 2186 * devices on the path from root to the specific device. */ 2187 const char *root_bus_path; 2188 int root_bus_len; 2189 char slot[] = ":SS.F"; 2190 int slot_len = sizeof slot - 1 /* For '\0' */; 2191 int path_len; 2192 char *path, *p; 2193 int s; 2194 2195 root_bus_path = pci_root_bus_path(d); 2196 root_bus_len = strlen(root_bus_path); 2197 2198 /* Calculate # of slots on path between device and root. */; 2199 slot_depth = 0; 2200 for (t = d; t; t = t->bus->parent_dev) { 2201 ++slot_depth; 2202 } 2203 2204 path_len = root_bus_len + slot_len * slot_depth; 2205 2206 /* Allocate memory, fill in the terminating null byte. */ 2207 path = g_malloc(path_len + 1 /* For '\0' */); 2208 path[path_len] = '\0'; 2209 2210 memcpy(path, root_bus_path, root_bus_len); 2211 2212 /* Fill in slot numbers. We walk up from device to root, so need to print 2213 * them in the reverse order, last to first. */ 2214 p = path + path_len; 2215 for (t = d; t; t = t->bus->parent_dev) { 2216 p -= slot_len; 2217 s = snprintf(slot, sizeof slot, ":%02x.%x", 2218 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2219 assert(s == slot_len); 2220 memcpy(p, slot, slot_len); 2221 } 2222 2223 return path; 2224 } 2225 2226 static int pci_qdev_find_recursive(PCIBus *bus, 2227 const char *id, PCIDevice **pdev) 2228 { 2229 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2230 if (!qdev) { 2231 return -ENODEV; 2232 } 2233 2234 /* roughly check if given qdev is pci device */ 2235 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2236 *pdev = PCI_DEVICE(qdev); 2237 return 0; 2238 } 2239 return -EINVAL; 2240 } 2241 2242 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2243 { 2244 PCIHostState *host_bridge; 2245 int rc = -ENODEV; 2246 2247 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2248 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2249 if (!tmp) { 2250 rc = 0; 2251 break; 2252 } 2253 if (tmp != -ENODEV) { 2254 rc = tmp; 2255 } 2256 } 2257 2258 return rc; 2259 } 2260 2261 MemoryRegion *pci_address_space(PCIDevice *dev) 2262 { 2263 return dev->bus->address_space_mem; 2264 } 2265 2266 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2267 { 2268 return dev->bus->address_space_io; 2269 } 2270 2271 static void pci_device_class_init(ObjectClass *klass, void *data) 2272 { 2273 DeviceClass *k = DEVICE_CLASS(klass); 2274 k->init = pci_qdev_init; 2275 k->unplug = pci_unplug_device; 2276 k->exit = pci_unregister_device; 2277 k->bus_type = TYPE_PCI_BUS; 2278 k->props = pci_props; 2279 } 2280 2281 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2282 { 2283 PCIBus *bus = PCI_BUS(dev->bus); 2284 2285 if (bus->iommu_fn) { 2286 return bus->iommu_fn(bus, bus->iommu_opaque, dev->devfn); 2287 } 2288 2289 if (bus->parent_dev) { 2290 /** We are ignoring the bus master DMA bit of the bridge 2291 * as it would complicate things such as VFIO for no good reason */ 2292 return pci_device_iommu_address_space(bus->parent_dev); 2293 } 2294 2295 return &address_space_memory; 2296 } 2297 2298 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) 2299 { 2300 bus->iommu_fn = fn; 2301 bus->iommu_opaque = opaque; 2302 } 2303 2304 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2305 { 2306 Range *range = opaque; 2307 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 2308 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2309 int i; 2310 2311 if (!(cmd & PCI_COMMAND_MEMORY)) { 2312 return; 2313 } 2314 2315 if (pc->is_bridge) { 2316 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2317 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2318 2319 base = MAX(base, 0x1ULL << 32); 2320 2321 if (limit >= base) { 2322 Range pref_range; 2323 pref_range.begin = base; 2324 pref_range.end = limit + 1; 2325 range_extend(range, &pref_range); 2326 } 2327 } 2328 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2329 PCIIORegion *r = &dev->io_regions[i]; 2330 Range region_range; 2331 2332 if (!r->size || 2333 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2334 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2335 continue; 2336 } 2337 region_range.begin = pci_bar_address(dev, i, r->type, r->size); 2338 region_range.end = region_range.begin + r->size; 2339 2340 if (region_range.begin == PCI_BAR_UNMAPPED) { 2341 continue; 2342 } 2343 2344 region_range.begin = MAX(region_range.begin, 0x1ULL << 32); 2345 2346 if (region_range.end - 1 >= region_range.begin) { 2347 range_extend(range, ®ion_range); 2348 } 2349 } 2350 } 2351 2352 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 2353 { 2354 range->begin = range->end = 0; 2355 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 2356 } 2357 2358 static const TypeInfo pci_device_type_info = { 2359 .name = TYPE_PCI_DEVICE, 2360 .parent = TYPE_DEVICE, 2361 .instance_size = sizeof(PCIDevice), 2362 .abstract = true, 2363 .class_size = sizeof(PCIDeviceClass), 2364 .class_init = pci_device_class_init, 2365 }; 2366 2367 static void pci_register_types(void) 2368 { 2369 type_register_static(&pci_bus_info); 2370 type_register_static(&pcie_bus_info); 2371 type_register_static(&pci_device_type_info); 2372 } 2373 2374 type_init(pci_register_types) 2375