1 /* 2 * QEMU PCI bus manager 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/datadir.h" 27 #include "qemu/units.h" 28 #include "hw/irq.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bridge.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "migration/qemu-file-types.h" 36 #include "migration/vmstate.h" 37 #include "net/net.h" 38 #include "system/numa.h" 39 #include "system/runstate.h" 40 #include "system/system.h" 41 #include "hw/loader.h" 42 #include "qemu/error-report.h" 43 #include "qemu/range.h" 44 #include "trace.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci/msix.h" 47 #include "hw/hotplug.h" 48 #include "hw/boards.h" 49 #include "hw/nvram/fw_cfg.h" 50 #include "qapi/error.h" 51 #include "qemu/cutils.h" 52 #include "pci-internal.h" 53 54 #include "hw/xen/xen.h" 55 #include "hw/i386/kvm/xen_evtchn.h" 56 57 //#define DEBUG_PCI 58 #ifdef DEBUG_PCI 59 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) 60 #else 61 # define PCI_DPRINTF(format, ...) do { } while (0) 62 #endif 63 64 bool pci_available = true; 65 66 static char *pcibus_get_dev_path(DeviceState *dev); 67 static char *pcibus_get_fw_dev_path(DeviceState *dev); 68 static void pcibus_reset_hold(Object *obj, ResetType type); 69 static bool pcie_has_upstream_port(PCIDevice *dev); 70 71 static void prop_pci_busnr_get(Object *obj, Visitor *v, const char *name, 72 void *opaque, Error **errp) 73 { 74 uint8_t busnr = pci_dev_bus_num(PCI_DEVICE(obj)); 75 76 visit_type_uint8(v, name, &busnr, errp); 77 } 78 79 static const PropertyInfo prop_pci_busnr = { 80 .type = "busnr", 81 .get = prop_pci_busnr_get, 82 }; 83 84 static const Property pci_props[] = { 85 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 86 DEFINE_PROP_STRING("romfile", PCIDevice, romfile), 87 DEFINE_PROP_UINT32("romsize", PCIDevice, romsize, UINT32_MAX), 88 DEFINE_PROP_INT32("rombar", PCIDevice, rom_bar, -1), 89 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present, 90 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), 91 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 92 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), 93 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 94 QEMU_PCIE_EXTCAP_INIT_BITNR, true), 95 DEFINE_PROP_STRING("failover_pair_id", PCIDevice, 96 failover_pair_id), 97 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), 98 DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present, 99 QEMU_PCIE_ERR_UNC_MASK_BITNR, true), 100 DEFINE_PROP_BIT("x-pcie-ari-nextfn-1", PCIDevice, cap_present, 101 QEMU_PCIE_ARI_NEXTFN_1_BITNR, false), 102 DEFINE_PROP_SIZE32("x-max-bounce-buffer-size", PCIDevice, 103 max_bounce_buffer_size, DEFAULT_MAX_BOUNCE_BUFFER_SIZE), 104 DEFINE_PROP_BIT("x-pcie-ext-tag", PCIDevice, cap_present, 105 QEMU_PCIE_EXT_TAG_BITNR, true), 106 { .name = "busnr", .info = &prop_pci_busnr }, 107 }; 108 109 static const VMStateDescription vmstate_pcibus = { 110 .name = "PCIBUS", 111 .version_id = 1, 112 .minimum_version_id = 1, 113 .fields = (const VMStateField[]) { 114 VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), 115 VMSTATE_VARRAY_INT32(irq_count, PCIBus, 116 nirq, 0, vmstate_info_int32, 117 int32_t), 118 VMSTATE_END_OF_LIST() 119 } 120 }; 121 122 static gint g_cmp_uint32(gconstpointer a, gconstpointer b, gpointer user_data) 123 { 124 return a - b; 125 } 126 127 static GSequence *pci_acpi_index_list(void) 128 { 129 static GSequence *used_acpi_index_list; 130 131 if (!used_acpi_index_list) { 132 used_acpi_index_list = g_sequence_new(NULL); 133 } 134 return used_acpi_index_list; 135 } 136 137 static void pci_init_bus_master(PCIDevice *pci_dev) 138 { 139 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); 140 141 memory_region_init_alias(&pci_dev->bus_master_enable_region, 142 OBJECT(pci_dev), "bus master", 143 dma_as->root, 0, memory_region_size(dma_as->root)); 144 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); 145 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, 146 &pci_dev->bus_master_enable_region); 147 } 148 149 static void pcibus_machine_done(Notifier *notifier, void *data) 150 { 151 PCIBus *bus = container_of(notifier, PCIBus, machine_done); 152 int i; 153 154 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 155 if (bus->devices[i]) { 156 pci_init_bus_master(bus->devices[i]); 157 } 158 } 159 } 160 161 static void pci_bus_realize(BusState *qbus, Error **errp) 162 { 163 PCIBus *bus = PCI_BUS(qbus); 164 165 bus->machine_done.notify = pcibus_machine_done; 166 qemu_add_machine_init_done_notifier(&bus->machine_done); 167 168 vmstate_register_any(NULL, &vmstate_pcibus, bus); 169 } 170 171 static void pcie_bus_realize(BusState *qbus, Error **errp) 172 { 173 PCIBus *bus = PCI_BUS(qbus); 174 Error *local_err = NULL; 175 176 pci_bus_realize(qbus, &local_err); 177 if (local_err) { 178 error_propagate(errp, local_err); 179 return; 180 } 181 182 /* 183 * A PCI-E bus can support extended config space if it's the root 184 * bus, or if the bus/bridge above it does as well 185 */ 186 if (pci_bus_is_root(bus)) { 187 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 188 } else { 189 PCIBus *parent_bus = pci_get_bus(bus->parent_dev); 190 191 if (pci_bus_allows_extended_config_space(parent_bus)) { 192 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 193 } 194 } 195 } 196 197 static void pci_bus_unrealize(BusState *qbus) 198 { 199 PCIBus *bus = PCI_BUS(qbus); 200 201 qemu_remove_machine_init_done_notifier(&bus->machine_done); 202 203 vmstate_unregister(NULL, &vmstate_pcibus, bus); 204 } 205 206 static int pcibus_num(PCIBus *bus) 207 { 208 if (pci_bus_is_root(bus)) { 209 return 0; /* pci host bridge */ 210 } 211 return bus->parent_dev->config[PCI_SECONDARY_BUS]; 212 } 213 214 static uint16_t pcibus_numa_node(PCIBus *bus) 215 { 216 return NUMA_NODE_UNASSIGNED; 217 } 218 219 bool pci_bus_add_fw_cfg_extra_pci_roots(FWCfgState *fw_cfg, 220 PCIBus *bus, 221 Error **errp) 222 { 223 Object *obj; 224 225 if (!bus) { 226 return true; 227 } 228 obj = OBJECT(bus); 229 230 return fw_cfg_add_file_from_generator(fw_cfg, obj->parent, 231 object_get_canonical_path_component(obj), 232 "etc/extra-pci-roots", errp); 233 } 234 235 static GByteArray *pci_bus_fw_cfg_gen_data(Object *obj, Error **errp) 236 { 237 PCIBus *bus = PCI_BUS(obj); 238 GByteArray *byte_array; 239 uint64_t extra_hosts = 0; 240 241 if (!bus) { 242 return NULL; 243 } 244 245 QLIST_FOREACH(bus, &bus->child, sibling) { 246 /* look for expander root buses */ 247 if (pci_bus_is_root(bus)) { 248 extra_hosts++; 249 } 250 } 251 252 if (!extra_hosts) { 253 return NULL; 254 } 255 extra_hosts = cpu_to_le64(extra_hosts); 256 257 byte_array = g_byte_array_new(); 258 g_byte_array_append(byte_array, 259 (const void *)&extra_hosts, sizeof(extra_hosts)); 260 261 return byte_array; 262 } 263 264 static void pci_bus_class_init(ObjectClass *klass, void *data) 265 { 266 BusClass *k = BUS_CLASS(klass); 267 PCIBusClass *pbc = PCI_BUS_CLASS(klass); 268 ResettableClass *rc = RESETTABLE_CLASS(klass); 269 FWCfgDataGeneratorClass *fwgc = FW_CFG_DATA_GENERATOR_CLASS(klass); 270 271 k->print_dev = pcibus_dev_print; 272 k->get_dev_path = pcibus_get_dev_path; 273 k->get_fw_dev_path = pcibus_get_fw_dev_path; 274 k->realize = pci_bus_realize; 275 k->unrealize = pci_bus_unrealize; 276 277 rc->phases.hold = pcibus_reset_hold; 278 279 pbc->bus_num = pcibus_num; 280 pbc->numa_node = pcibus_numa_node; 281 282 fwgc->get_data = pci_bus_fw_cfg_gen_data; 283 } 284 285 static const TypeInfo pci_bus_info = { 286 .name = TYPE_PCI_BUS, 287 .parent = TYPE_BUS, 288 .instance_size = sizeof(PCIBus), 289 .class_size = sizeof(PCIBusClass), 290 .class_init = pci_bus_class_init, 291 .interfaces = (InterfaceInfo[]) { 292 { TYPE_FW_CFG_DATA_GENERATOR_INTERFACE }, 293 { } 294 } 295 }; 296 297 static const TypeInfo cxl_interface_info = { 298 .name = INTERFACE_CXL_DEVICE, 299 .parent = TYPE_INTERFACE, 300 }; 301 302 static const TypeInfo pcie_interface_info = { 303 .name = INTERFACE_PCIE_DEVICE, 304 .parent = TYPE_INTERFACE, 305 }; 306 307 static const TypeInfo conventional_pci_interface_info = { 308 .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, 309 .parent = TYPE_INTERFACE, 310 }; 311 312 static void pcie_bus_class_init(ObjectClass *klass, void *data) 313 { 314 BusClass *k = BUS_CLASS(klass); 315 316 k->realize = pcie_bus_realize; 317 } 318 319 static const TypeInfo pcie_bus_info = { 320 .name = TYPE_PCIE_BUS, 321 .parent = TYPE_PCI_BUS, 322 .class_init = pcie_bus_class_init, 323 }; 324 325 static const TypeInfo cxl_bus_info = { 326 .name = TYPE_CXL_BUS, 327 .parent = TYPE_PCIE_BUS, 328 .class_init = pcie_bus_class_init, 329 }; 330 331 static void pci_update_mappings(PCIDevice *d); 332 static void pci_irq_handler(void *opaque, int irq_num, int level); 333 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); 334 static void pci_del_option_rom(PCIDevice *pdev); 335 336 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; 337 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; 338 339 PCIHostStateList pci_host_bridges; 340 341 int pci_bar(PCIDevice *d, int reg) 342 { 343 uint8_t type; 344 345 /* PCIe virtual functions do not have their own BARs */ 346 assert(!pci_is_vf(d)); 347 348 if (reg != PCI_ROM_SLOT) 349 return PCI_BASE_ADDRESS_0 + reg * 4; 350 351 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 352 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; 353 } 354 355 static inline int pci_irq_state(PCIDevice *d, int irq_num) 356 { 357 return (d->irq_state >> irq_num) & 0x1; 358 } 359 360 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) 361 { 362 d->irq_state &= ~(0x1 << irq_num); 363 d->irq_state |= level << irq_num; 364 } 365 366 static void pci_bus_change_irq_level(PCIBus *bus, int irq_num, int change) 367 { 368 assert(irq_num >= 0); 369 assert(irq_num < bus->nirq); 370 bus->irq_count[irq_num] += change; 371 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); 372 } 373 374 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) 375 { 376 PCIBus *bus; 377 for (;;) { 378 int dev_irq = irq_num; 379 bus = pci_get_bus(pci_dev); 380 assert(bus->map_irq); 381 irq_num = bus->map_irq(pci_dev, irq_num); 382 trace_pci_route_irq(dev_irq, DEVICE(pci_dev)->canonical_path, irq_num, 383 pci_bus_is_root(bus) ? "root-complex" 384 : DEVICE(bus->parent_dev)->canonical_path); 385 if (bus->set_irq) 386 break; 387 pci_dev = bus->parent_dev; 388 } 389 pci_bus_change_irq_level(bus, irq_num, change); 390 } 391 392 int pci_bus_get_irq_level(PCIBus *bus, int irq_num) 393 { 394 assert(irq_num >= 0); 395 assert(irq_num < bus->nirq); 396 return !!bus->irq_count[irq_num]; 397 } 398 399 /* Update interrupt status bit in config space on interrupt 400 * state change. */ 401 static void pci_update_irq_status(PCIDevice *dev) 402 { 403 if (dev->irq_state) { 404 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; 405 } else { 406 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 407 } 408 } 409 410 void pci_device_deassert_intx(PCIDevice *dev) 411 { 412 int i; 413 for (i = 0; i < PCI_NUM_PINS; ++i) { 414 pci_irq_handler(dev, i, 0); 415 } 416 } 417 418 static void pci_msi_trigger(PCIDevice *dev, MSIMessage msg) 419 { 420 MemTxAttrs attrs = {}; 421 422 /* 423 * Xen uses the high bits of the address to contain some of the bits 424 * of the PIRQ#. Therefore we can't just send the write cycle and 425 * trust that it's caught by the APIC at 0xfee00000 because the 426 * target of the write might be e.g. 0x0x1000fee46000 for PIRQ#4166. 427 * So we intercept the delivery here instead of in kvm_send_msi(). 428 */ 429 if (xen_mode == XEN_EMULATE && 430 xen_evtchn_deliver_pirq_msi(msg.address, msg.data)) { 431 return; 432 } 433 attrs.requester_id = pci_requester_id(dev); 434 address_space_stl_le(&dev->bus_master_as, msg.address, msg.data, 435 attrs, NULL); 436 } 437 438 /* 439 * Register and track a PM capability. If wmask is also enabled for the power 440 * state field of the pmcsr register, guest writes may change the device PM 441 * state. BAR access is only enabled while the device is in the D0 state. 442 * Return the capability offset or negative error code. 443 */ 444 int pci_pm_init(PCIDevice *d, uint8_t offset, Error **errp) 445 { 446 int cap = pci_add_capability(d, PCI_CAP_ID_PM, offset, PCI_PM_SIZEOF, errp); 447 448 if (cap < 0) { 449 return cap; 450 } 451 452 d->pm_cap = cap; 453 d->cap_present |= QEMU_PCI_CAP_PM; 454 455 return cap; 456 } 457 458 static uint8_t pci_pm_state(PCIDevice *d) 459 { 460 uint16_t pmcsr; 461 462 if (!(d->cap_present & QEMU_PCI_CAP_PM)) { 463 return 0; 464 } 465 466 pmcsr = pci_get_word(d->config + d->pm_cap + PCI_PM_CTRL); 467 468 return pmcsr & PCI_PM_CTRL_STATE_MASK; 469 } 470 471 /* 472 * Update the PM capability state based on the new value stored in config 473 * space respective to the old, pre-write state provided. If the new value 474 * is rejected (unsupported or invalid transition) restore the old value. 475 * Return the resulting PM state. 476 */ 477 static uint8_t pci_pm_update(PCIDevice *d, uint32_t addr, int l, uint8_t old) 478 { 479 uint16_t pmc; 480 uint8_t new; 481 482 if (!(d->cap_present & QEMU_PCI_CAP_PM) || 483 !range_covers_byte(addr, l, d->pm_cap + PCI_PM_CTRL)) { 484 return old; 485 } 486 487 new = pci_pm_state(d); 488 if (new == old) { 489 return old; 490 } 491 492 pmc = pci_get_word(d->config + d->pm_cap + PCI_PM_PMC); 493 494 /* 495 * Transitions to D1 & D2 are only allowed if supported. Devices may 496 * only transition to higher D-states or to D0. 497 */ 498 if ((!(pmc & PCI_PM_CAP_D1) && new == 1) || 499 (!(pmc & PCI_PM_CAP_D2) && new == 2) || 500 (old && new && new < old)) { 501 pci_word_test_and_clear_mask(d->config + d->pm_cap + PCI_PM_CTRL, 502 PCI_PM_CTRL_STATE_MASK); 503 pci_word_test_and_set_mask(d->config + d->pm_cap + PCI_PM_CTRL, 504 old); 505 trace_pci_pm_bad_transition(d->name, pci_dev_bus_num(d), 506 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), 507 old, new); 508 return old; 509 } 510 511 trace_pci_pm_transition(d->name, pci_dev_bus_num(d), PCI_SLOT(d->devfn), 512 PCI_FUNC(d->devfn), old, new); 513 return new; 514 } 515 516 static void pci_reset_regions(PCIDevice *dev) 517 { 518 int r; 519 if (pci_is_vf(dev)) { 520 return; 521 } 522 523 for (r = 0; r < PCI_NUM_REGIONS; ++r) { 524 PCIIORegion *region = &dev->io_regions[r]; 525 if (!region->size) { 526 continue; 527 } 528 529 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && 530 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 531 pci_set_quad(dev->config + pci_bar(dev, r), region->type); 532 } else { 533 pci_set_long(dev->config + pci_bar(dev, r), region->type); 534 } 535 } 536 } 537 538 static void pci_do_device_reset(PCIDevice *dev) 539 { 540 pci_device_deassert_intx(dev); 541 assert(dev->irq_state == 0); 542 543 /* Clear all writable bits */ 544 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, 545 pci_get_word(dev->wmask + PCI_COMMAND) | 546 pci_get_word(dev->w1cmask + PCI_COMMAND)); 547 pci_word_test_and_clear_mask(dev->config + PCI_STATUS, 548 pci_get_word(dev->wmask + PCI_STATUS) | 549 pci_get_word(dev->w1cmask + PCI_STATUS)); 550 /* Some devices make bits of PCI_INTERRUPT_LINE read only */ 551 pci_byte_test_and_clear_mask(dev->config + PCI_INTERRUPT_LINE, 552 pci_get_word(dev->wmask + PCI_INTERRUPT_LINE) | 553 pci_get_word(dev->w1cmask + PCI_INTERRUPT_LINE)); 554 dev->config[PCI_CACHE_LINE_SIZE] = 0x0; 555 /* Default PM state is D0 */ 556 if (dev->cap_present & QEMU_PCI_CAP_PM) { 557 pci_word_test_and_clear_mask(dev->config + dev->pm_cap + PCI_PM_CTRL, 558 PCI_PM_CTRL_STATE_MASK); 559 } 560 pci_reset_regions(dev); 561 pci_update_mappings(dev); 562 563 msi_reset(dev); 564 msix_reset(dev); 565 pcie_sriov_pf_reset(dev); 566 } 567 568 /* 569 * This function is called on #RST and FLR. 570 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set 571 */ 572 void pci_device_reset(PCIDevice *dev) 573 { 574 device_cold_reset(&dev->qdev); 575 pci_do_device_reset(dev); 576 } 577 578 /* 579 * Trigger pci bus reset under a given bus. 580 * Called via bus_cold_reset on RST# assert, after the devices 581 * have been reset device_cold_reset-ed already. 582 */ 583 static void pcibus_reset_hold(Object *obj, ResetType type) 584 { 585 PCIBus *bus = PCI_BUS(obj); 586 int i; 587 588 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 589 if (bus->devices[i]) { 590 pci_do_device_reset(bus->devices[i]); 591 } 592 } 593 594 for (i = 0; i < bus->nirq; i++) { 595 assert(bus->irq_count[i] == 0); 596 } 597 } 598 599 static void pci_host_bus_register(DeviceState *host) 600 { 601 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 602 603 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); 604 } 605 606 static void pci_host_bus_unregister(DeviceState *host) 607 { 608 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); 609 610 QLIST_REMOVE(host_bridge, next); 611 } 612 613 PCIBus *pci_device_root_bus(const PCIDevice *d) 614 { 615 PCIBus *bus = pci_get_bus(d); 616 617 while (!pci_bus_is_root(bus)) { 618 d = bus->parent_dev; 619 assert(d != NULL); 620 621 bus = pci_get_bus(d); 622 } 623 624 return bus; 625 } 626 627 const char *pci_root_bus_path(PCIDevice *dev) 628 { 629 PCIBus *rootbus = pci_device_root_bus(dev); 630 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 631 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); 632 633 assert(host_bridge->bus == rootbus); 634 635 if (hc->root_bus_path) { 636 return (*hc->root_bus_path)(host_bridge, rootbus); 637 } 638 639 return rootbus->qbus.name; 640 } 641 642 bool pci_bus_bypass_iommu(PCIBus *bus) 643 { 644 PCIBus *rootbus = bus; 645 PCIHostState *host_bridge; 646 647 if (!pci_bus_is_root(bus)) { 648 rootbus = pci_device_root_bus(bus->parent_dev); 649 } 650 651 host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); 652 653 assert(host_bridge->bus == rootbus); 654 655 return host_bridge->bypass_iommu; 656 } 657 658 static void pci_root_bus_internal_init(PCIBus *bus, DeviceState *parent, 659 MemoryRegion *mem, MemoryRegion *io, 660 uint8_t devfn_min) 661 { 662 assert(PCI_FUNC(devfn_min) == 0); 663 bus->devfn_min = devfn_min; 664 bus->slot_reserved_mask = 0x0; 665 bus->address_space_mem = mem; 666 bus->address_space_io = io; 667 bus->flags |= PCI_BUS_IS_ROOT; 668 669 /* host bridge */ 670 QLIST_INIT(&bus->child); 671 672 pci_host_bus_register(parent); 673 } 674 675 static void pci_bus_uninit(PCIBus *bus) 676 { 677 pci_host_bus_unregister(BUS(bus)->parent); 678 } 679 680 bool pci_bus_is_express(const PCIBus *bus) 681 { 682 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); 683 } 684 685 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent, 686 const char *name, 687 MemoryRegion *mem, MemoryRegion *io, 688 uint8_t devfn_min, const char *typename) 689 { 690 qbus_init(bus, bus_size, typename, parent, name); 691 pci_root_bus_internal_init(bus, parent, mem, io, devfn_min); 692 } 693 694 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, 695 MemoryRegion *mem, MemoryRegion *io, 696 uint8_t devfn_min, const char *typename) 697 { 698 PCIBus *bus; 699 700 bus = PCI_BUS(qbus_new(typename, parent, name)); 701 pci_root_bus_internal_init(bus, parent, mem, io, devfn_min); 702 return bus; 703 } 704 705 void pci_root_bus_cleanup(PCIBus *bus) 706 { 707 pci_bus_uninit(bus); 708 /* the caller of the unplug hotplug handler will delete this device */ 709 qbus_unrealize(BUS(bus)); 710 } 711 712 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, 713 void *irq_opaque, int nirq) 714 { 715 bus->set_irq = set_irq; 716 bus->irq_opaque = irq_opaque; 717 bus->nirq = nirq; 718 g_free(bus->irq_count); 719 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); 720 } 721 722 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq) 723 { 724 bus->map_irq = map_irq; 725 } 726 727 void pci_bus_irqs_cleanup(PCIBus *bus) 728 { 729 bus->set_irq = NULL; 730 bus->map_irq = NULL; 731 bus->irq_opaque = NULL; 732 bus->nirq = 0; 733 g_free(bus->irq_count); 734 bus->irq_count = NULL; 735 } 736 737 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, 738 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, 739 void *irq_opaque, 740 MemoryRegion *mem, MemoryRegion *io, 741 uint8_t devfn_min, int nirq, 742 const char *typename) 743 { 744 PCIBus *bus; 745 746 bus = pci_root_bus_new(parent, name, mem, io, devfn_min, typename); 747 pci_bus_irqs(bus, set_irq, irq_opaque, nirq); 748 pci_bus_map_irqs(bus, map_irq); 749 return bus; 750 } 751 752 void pci_unregister_root_bus(PCIBus *bus) 753 { 754 pci_bus_irqs_cleanup(bus); 755 pci_root_bus_cleanup(bus); 756 } 757 758 int pci_bus_num(PCIBus *s) 759 { 760 return PCI_BUS_GET_CLASS(s)->bus_num(s); 761 } 762 763 /* Returns the min and max bus numbers of a PCI bus hierarchy */ 764 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus) 765 { 766 int i; 767 *min_bus = *max_bus = pci_bus_num(bus); 768 769 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 770 PCIDevice *dev = bus->devices[i]; 771 772 if (dev && IS_PCI_BRIDGE(dev)) { 773 *min_bus = MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); 774 *max_bus = MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); 775 } 776 } 777 } 778 779 int pci_bus_numa_node(PCIBus *bus) 780 { 781 return PCI_BUS_GET_CLASS(bus)->numa_node(bus); 782 } 783 784 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, 785 const VMStateField *field) 786 { 787 PCIDevice *s = container_of(pv, PCIDevice, config); 788 uint8_t *config; 789 int i; 790 791 assert(size == pci_config_size(s)); 792 config = g_malloc(size); 793 794 qemu_get_buffer(f, config, size); 795 for (i = 0; i < size; ++i) { 796 if ((config[i] ^ s->config[i]) & 797 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { 798 error_report("%s: Bad config data: i=0x%x read: %x device: %x " 799 "cmask: %x wmask: %x w1cmask:%x", __func__, 800 i, config[i], s->config[i], 801 s->cmask[i], s->wmask[i], s->w1cmask[i]); 802 g_free(config); 803 return -EINVAL; 804 } 805 } 806 memcpy(s->config, config, size); 807 808 pci_update_mappings(s); 809 if (IS_PCI_BRIDGE(s)) { 810 pci_bridge_update_mappings(PCI_BRIDGE(s)); 811 } 812 813 memory_region_set_enabled(&s->bus_master_enable_region, 814 pci_get_word(s->config + PCI_COMMAND) 815 & PCI_COMMAND_MASTER); 816 817 g_free(config); 818 return 0; 819 } 820 821 /* just put buffer */ 822 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, 823 const VMStateField *field, JSONWriter *vmdesc) 824 { 825 const uint8_t **v = pv; 826 assert(size == pci_config_size(container_of(pv, PCIDevice, config))); 827 qemu_put_buffer(f, *v, size); 828 829 return 0; 830 } 831 832 static const VMStateInfo vmstate_info_pci_config = { 833 .name = "pci config", 834 .get = get_pci_config_device, 835 .put = put_pci_config_device, 836 }; 837 838 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, 839 const VMStateField *field) 840 { 841 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 842 uint32_t irq_state[PCI_NUM_PINS]; 843 int i; 844 for (i = 0; i < PCI_NUM_PINS; ++i) { 845 irq_state[i] = qemu_get_be32(f); 846 if (irq_state[i] != 0x1 && irq_state[i] != 0) { 847 fprintf(stderr, "irq state %d: must be 0 or 1.\n", 848 irq_state[i]); 849 return -EINVAL; 850 } 851 } 852 853 for (i = 0; i < PCI_NUM_PINS; ++i) { 854 pci_set_irq_state(s, i, irq_state[i]); 855 } 856 857 return 0; 858 } 859 860 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, 861 const VMStateField *field, JSONWriter *vmdesc) 862 { 863 int i; 864 PCIDevice *s = container_of(pv, PCIDevice, irq_state); 865 866 for (i = 0; i < PCI_NUM_PINS; ++i) { 867 qemu_put_be32(f, pci_irq_state(s, i)); 868 } 869 870 return 0; 871 } 872 873 static const VMStateInfo vmstate_info_pci_irq_state = { 874 .name = "pci irq state", 875 .get = get_pci_irq_state, 876 .put = put_pci_irq_state, 877 }; 878 879 static bool migrate_is_pcie(void *opaque, int version_id) 880 { 881 return pci_is_express((PCIDevice *)opaque); 882 } 883 884 static bool migrate_is_not_pcie(void *opaque, int version_id) 885 { 886 return !pci_is_express((PCIDevice *)opaque); 887 } 888 889 static int pci_post_load(void *opaque, int version_id) 890 { 891 pcie_sriov_pf_post_load(opaque); 892 return 0; 893 } 894 895 const VMStateDescription vmstate_pci_device = { 896 .name = "PCIDevice", 897 .version_id = 2, 898 .minimum_version_id = 1, 899 .post_load = pci_post_load, 900 .fields = (const VMStateField[]) { 901 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), 902 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 903 migrate_is_not_pcie, 904 0, vmstate_info_pci_config, 905 PCI_CONFIG_SPACE_SIZE), 906 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, 907 migrate_is_pcie, 908 0, vmstate_info_pci_config, 909 PCIE_CONFIG_SPACE_SIZE), 910 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, 911 vmstate_info_pci_irq_state, 912 PCI_NUM_PINS * sizeof(int32_t)), 913 VMSTATE_END_OF_LIST() 914 } 915 }; 916 917 918 void pci_device_save(PCIDevice *s, QEMUFile *f) 919 { 920 /* Clear interrupt status bit: it is implicit 921 * in irq_state which we are saving. 922 * This makes us compatible with old devices 923 * which never set or clear this bit. */ 924 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; 925 vmstate_save_state(f, &vmstate_pci_device, s, NULL); 926 /* Restore the interrupt status bit. */ 927 pci_update_irq_status(s); 928 } 929 930 int pci_device_load(PCIDevice *s, QEMUFile *f) 931 { 932 int ret; 933 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); 934 /* Restore the interrupt status bit. */ 935 pci_update_irq_status(s); 936 return ret; 937 } 938 939 static void pci_set_default_subsystem_id(PCIDevice *pci_dev) 940 { 941 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 942 pci_default_sub_vendor_id); 943 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 944 pci_default_sub_device_id); 945 } 946 947 /* 948 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL 949 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error 950 */ 951 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, 952 unsigned int *slotp, unsigned int *funcp) 953 { 954 const char *p; 955 char *e; 956 unsigned long val; 957 unsigned long dom = 0, bus = 0; 958 unsigned int slot = 0; 959 unsigned int func = 0; 960 961 p = addr; 962 val = strtoul(p, &e, 16); 963 if (e == p) 964 return -1; 965 if (*e == ':') { 966 bus = val; 967 p = e + 1; 968 val = strtoul(p, &e, 16); 969 if (e == p) 970 return -1; 971 if (*e == ':') { 972 dom = bus; 973 bus = val; 974 p = e + 1; 975 val = strtoul(p, &e, 16); 976 if (e == p) 977 return -1; 978 } 979 } 980 981 slot = val; 982 983 if (funcp != NULL) { 984 if (*e != '.') 985 return -1; 986 987 p = e + 1; 988 val = strtoul(p, &e, 16); 989 if (e == p) 990 return -1; 991 992 func = val; 993 } 994 995 /* if funcp == NULL func is 0 */ 996 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) 997 return -1; 998 999 if (*e) 1000 return -1; 1001 1002 *domp = dom; 1003 *busp = bus; 1004 *slotp = slot; 1005 if (funcp != NULL) 1006 *funcp = func; 1007 return 0; 1008 } 1009 1010 static void pci_init_cmask(PCIDevice *dev) 1011 { 1012 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); 1013 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); 1014 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; 1015 dev->cmask[PCI_REVISION_ID] = 0xff; 1016 dev->cmask[PCI_CLASS_PROG] = 0xff; 1017 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); 1018 dev->cmask[PCI_HEADER_TYPE] = 0xff; 1019 dev->cmask[PCI_CAPABILITY_LIST] = 0xff; 1020 } 1021 1022 static void pci_init_wmask(PCIDevice *dev) 1023 { 1024 int config_size = pci_config_size(dev); 1025 1026 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; 1027 dev->wmask[PCI_INTERRUPT_LINE] = 0xff; 1028 pci_set_word(dev->wmask + PCI_COMMAND, 1029 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 1030 PCI_COMMAND_INTX_DISABLE); 1031 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); 1032 1033 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, 1034 config_size - PCI_CONFIG_HEADER_SIZE); 1035 } 1036 1037 static void pci_init_w1cmask(PCIDevice *dev) 1038 { 1039 /* 1040 * Note: It's okay to set w1cmask even for readonly bits as 1041 * long as their value is hardwired to 0. 1042 */ 1043 pci_set_word(dev->w1cmask + PCI_STATUS, 1044 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | 1045 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | 1046 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); 1047 } 1048 1049 static void pci_init_mask_bridge(PCIDevice *d) 1050 { 1051 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and 1052 PCI_SEC_LATENCY_TIMER */ 1053 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); 1054 1055 /* base and limit */ 1056 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; 1057 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; 1058 pci_set_word(d->wmask + PCI_MEMORY_BASE, 1059 PCI_MEMORY_RANGE_MASK & 0xffff); 1060 pci_set_word(d->wmask + PCI_MEMORY_LIMIT, 1061 PCI_MEMORY_RANGE_MASK & 0xffff); 1062 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, 1063 PCI_PREF_RANGE_MASK & 0xffff); 1064 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, 1065 PCI_PREF_RANGE_MASK & 0xffff); 1066 1067 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ 1068 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); 1069 1070 /* Supported memory and i/o types */ 1071 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; 1072 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; 1073 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, 1074 PCI_PREF_RANGE_TYPE_64); 1075 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, 1076 PCI_PREF_RANGE_TYPE_64); 1077 1078 /* 1079 * TODO: Bridges default to 10-bit VGA decoding but we currently only 1080 * implement 16-bit decoding (no alias support). 1081 */ 1082 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 1083 PCI_BRIDGE_CTL_PARITY | 1084 PCI_BRIDGE_CTL_SERR | 1085 PCI_BRIDGE_CTL_ISA | 1086 PCI_BRIDGE_CTL_VGA | 1087 PCI_BRIDGE_CTL_VGA_16BIT | 1088 PCI_BRIDGE_CTL_MASTER_ABORT | 1089 PCI_BRIDGE_CTL_BUS_RESET | 1090 PCI_BRIDGE_CTL_FAST_BACK | 1091 PCI_BRIDGE_CTL_DISCARD | 1092 PCI_BRIDGE_CTL_SEC_DISCARD | 1093 PCI_BRIDGE_CTL_DISCARD_SERR); 1094 /* Below does not do anything as we never set this bit, put here for 1095 * completeness. */ 1096 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, 1097 PCI_BRIDGE_CTL_DISCARD_STATUS); 1098 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; 1099 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; 1100 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, 1101 PCI_PREF_RANGE_TYPE_MASK); 1102 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, 1103 PCI_PREF_RANGE_TYPE_MASK); 1104 } 1105 1106 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) 1107 { 1108 uint8_t slot = PCI_SLOT(dev->devfn); 1109 uint8_t func; 1110 1111 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 1112 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; 1113 } 1114 1115 /* 1116 * With SR/IOV and ARI, a device at function 0 need not be a multifunction 1117 * device, as it may just be a VF that ended up with function 0 in 1118 * the legacy PCI interpretation. Avoid failing in such cases: 1119 */ 1120 if (pci_is_vf(dev) && 1121 dev->exp.sriov_vf.pf->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 1122 return; 1123 } 1124 1125 /* 1126 * multifunction bit is interpreted in two ways as follows. 1127 * - all functions must set the bit to 1. 1128 * Example: Intel X53 1129 * - function 0 must set the bit, but the rest function (> 0) 1130 * is allowed to leave the bit to 0. 1131 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, 1132 * 1133 * So OS (at least Linux) checks the bit of only function 0, 1134 * and doesn't see the bit of function > 0. 1135 * 1136 * The below check allows both interpretation. 1137 */ 1138 if (PCI_FUNC(dev->devfn)) { 1139 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; 1140 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { 1141 /* function 0 should set multifunction bit */ 1142 error_setg(errp, "PCI: single function device can't be populated " 1143 "in function %x.%x", slot, PCI_FUNC(dev->devfn)); 1144 return; 1145 } 1146 return; 1147 } 1148 1149 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { 1150 return; 1151 } 1152 /* function 0 indicates single function, so function > 0 must be NULL */ 1153 for (func = 1; func < PCI_FUNC_MAX; ++func) { 1154 if (bus->devices[PCI_DEVFN(slot, func)]) { 1155 error_setg(errp, "PCI: %x.0 indicates single function, " 1156 "but %x.%x is already populated.", 1157 slot, slot, func); 1158 return; 1159 } 1160 } 1161 } 1162 1163 static void pci_config_alloc(PCIDevice *pci_dev) 1164 { 1165 int config_size = pci_config_size(pci_dev); 1166 1167 pci_dev->config = g_malloc0(config_size); 1168 pci_dev->cmask = g_malloc0(config_size); 1169 pci_dev->wmask = g_malloc0(config_size); 1170 pci_dev->w1cmask = g_malloc0(config_size); 1171 pci_dev->used = g_malloc0(config_size); 1172 } 1173 1174 static void pci_config_free(PCIDevice *pci_dev) 1175 { 1176 g_free(pci_dev->config); 1177 g_free(pci_dev->cmask); 1178 g_free(pci_dev->wmask); 1179 g_free(pci_dev->w1cmask); 1180 g_free(pci_dev->used); 1181 } 1182 1183 static void do_pci_unregister_device(PCIDevice *pci_dev) 1184 { 1185 pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; 1186 pci_config_free(pci_dev); 1187 1188 if (xen_mode == XEN_EMULATE) { 1189 xen_evtchn_remove_pci_device(pci_dev); 1190 } 1191 if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { 1192 memory_region_del_subregion(&pci_dev->bus_master_container_region, 1193 &pci_dev->bus_master_enable_region); 1194 } 1195 address_space_destroy(&pci_dev->bus_master_as); 1196 } 1197 1198 /* Extract PCIReqIDCache into BDF format */ 1199 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache) 1200 { 1201 uint8_t bus_n; 1202 uint16_t result; 1203 1204 switch (cache->type) { 1205 case PCI_REQ_ID_BDF: 1206 result = pci_get_bdf(cache->dev); 1207 break; 1208 case PCI_REQ_ID_SECONDARY_BUS: 1209 bus_n = pci_dev_bus_num(cache->dev); 1210 result = PCI_BUILD_BDF(bus_n, 0); 1211 break; 1212 default: 1213 error_report("Invalid PCI requester ID cache type: %d", 1214 cache->type); 1215 exit(1); 1216 break; 1217 } 1218 1219 return result; 1220 } 1221 1222 /* Parse bridges up to the root complex and return requester ID 1223 * cache for specific device. For full PCIe topology, the cache 1224 * result would be exactly the same as getting BDF of the device. 1225 * However, several tricks are required when system mixed up with 1226 * legacy PCI devices and PCIe-to-PCI bridges. 1227 * 1228 * Here we cache the proxy device (and type) not requester ID since 1229 * bus number might change from time to time. 1230 */ 1231 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) 1232 { 1233 PCIDevice *parent; 1234 PCIReqIDCache cache = { 1235 .dev = dev, 1236 .type = PCI_REQ_ID_BDF, 1237 }; 1238 1239 while (!pci_bus_is_root(pci_get_bus(dev))) { 1240 /* We are under PCI/PCIe bridges */ 1241 parent = pci_get_bus(dev)->parent_dev; 1242 if (pci_is_express(parent)) { 1243 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 1244 /* When we pass through PCIe-to-PCI/PCIX bridges, we 1245 * override the requester ID using secondary bus 1246 * number of parent bridge with zeroed devfn 1247 * (pcie-to-pci bridge spec chap 2.3). */ 1248 cache.type = PCI_REQ_ID_SECONDARY_BUS; 1249 cache.dev = dev; 1250 } 1251 } else { 1252 /* Legacy PCI, override requester ID with the bridge's 1253 * BDF upstream. When the root complex connects to 1254 * legacy PCI devices (including buses), it can only 1255 * obtain requester ID info from directly attached 1256 * devices. If devices are attached under bridges, only 1257 * the requester ID of the bridge that is directly 1258 * attached to the root complex can be recognized. */ 1259 cache.type = PCI_REQ_ID_BDF; 1260 cache.dev = parent; 1261 } 1262 dev = parent; 1263 } 1264 1265 return cache; 1266 } 1267 1268 uint16_t pci_requester_id(PCIDevice *dev) 1269 { 1270 return pci_req_id_cache_extract(&dev->requester_id_cache); 1271 } 1272 1273 static bool pci_bus_devfn_available(PCIBus *bus, int devfn) 1274 { 1275 return !(bus->devices[devfn]); 1276 } 1277 1278 static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) 1279 { 1280 return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); 1281 } 1282 1283 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus) 1284 { 1285 return bus->slot_reserved_mask; 1286 } 1287 1288 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask) 1289 { 1290 bus->slot_reserved_mask |= mask; 1291 } 1292 1293 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask) 1294 { 1295 bus->slot_reserved_mask &= ~mask; 1296 } 1297 1298 /* -1 for devfn means auto assign */ 1299 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, 1300 const char *name, int devfn, 1301 Error **errp) 1302 { 1303 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1304 PCIConfigReadFunc *config_read = pc->config_read; 1305 PCIConfigWriteFunc *config_write = pc->config_write; 1306 Error *local_err = NULL; 1307 DeviceState *dev = DEVICE(pci_dev); 1308 PCIBus *bus = pci_get_bus(pci_dev); 1309 bool is_bridge = IS_PCI_BRIDGE(pci_dev); 1310 1311 /* Only pci bridges can be attached to extra PCI root buses */ 1312 if (pci_bus_is_root(bus) && bus->parent_dev && !is_bridge) { 1313 error_setg(errp, 1314 "PCI: Only PCI/PCIe bridges can be plugged into %s", 1315 bus->parent_dev->name); 1316 return NULL; 1317 } 1318 1319 if (devfn < 0) { 1320 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); 1321 devfn += PCI_FUNC_MAX) { 1322 if (pci_bus_devfn_available(bus, devfn) && 1323 !pci_bus_devfn_reserved(bus, devfn)) { 1324 goto found; 1325 } 1326 } 1327 error_setg(errp, "PCI: no slot/function available for %s, all in use " 1328 "or reserved", name); 1329 return NULL; 1330 found: ; 1331 } else if (pci_bus_devfn_reserved(bus, devfn)) { 1332 error_setg(errp, "PCI: slot %d function %d not available for %s," 1333 " reserved", 1334 PCI_SLOT(devfn), PCI_FUNC(devfn), name); 1335 return NULL; 1336 } else if (!pci_bus_devfn_available(bus, devfn)) { 1337 error_setg(errp, "PCI: slot %d function %d not available for %s," 1338 " in use by %s,id=%s", 1339 PCI_SLOT(devfn), PCI_FUNC(devfn), name, 1340 bus->devices[devfn]->name, bus->devices[devfn]->qdev.id); 1341 return NULL; 1342 } 1343 1344 /* 1345 * Populating function 0 triggers a scan from the guest that 1346 * exposes other non-zero functions. Hence we need to ensure that 1347 * function 0 wasn't added yet. 1348 */ 1349 if (dev->hotplugged && !pci_is_vf(pci_dev) && 1350 pci_get_function_0(pci_dev)) { 1351 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1352 " new func %s cannot be exposed to guest.", 1353 PCI_SLOT(pci_get_function_0(pci_dev)->devfn), 1354 pci_get_function_0(pci_dev)->name, 1355 name); 1356 1357 return NULL; 1358 } 1359 1360 pci_dev->devfn = devfn; 1361 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); 1362 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); 1363 1364 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), 1365 "bus master container", UINT64_MAX); 1366 address_space_init(&pci_dev->bus_master_as, 1367 &pci_dev->bus_master_container_region, pci_dev->name); 1368 pci_dev->bus_master_as.max_bounce_buffer_size = 1369 pci_dev->max_bounce_buffer_size; 1370 1371 if (phase_check(PHASE_MACHINE_READY)) { 1372 pci_init_bus_master(pci_dev); 1373 } 1374 pci_dev->irq_state = 0; 1375 pci_config_alloc(pci_dev); 1376 1377 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); 1378 pci_config_set_device_id(pci_dev->config, pc->device_id); 1379 pci_config_set_revision(pci_dev->config, pc->revision); 1380 pci_config_set_class(pci_dev->config, pc->class_id); 1381 1382 if (!is_bridge) { 1383 if (pc->subsystem_vendor_id || pc->subsystem_id) { 1384 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1385 pc->subsystem_vendor_id); 1386 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1387 pc->subsystem_id); 1388 } else { 1389 pci_set_default_subsystem_id(pci_dev); 1390 } 1391 } else { 1392 /* subsystem_vendor_id/subsystem_id are only for header type 0 */ 1393 assert(!pc->subsystem_vendor_id); 1394 assert(!pc->subsystem_id); 1395 } 1396 pci_init_cmask(pci_dev); 1397 pci_init_wmask(pci_dev); 1398 pci_init_w1cmask(pci_dev); 1399 if (is_bridge) { 1400 pci_init_mask_bridge(pci_dev); 1401 } 1402 pci_init_multifunction(bus, pci_dev, &local_err); 1403 if (local_err) { 1404 error_propagate(errp, local_err); 1405 do_pci_unregister_device(pci_dev); 1406 return NULL; 1407 } 1408 1409 if (!config_read) 1410 config_read = pci_default_read_config; 1411 if (!config_write) 1412 config_write = pci_default_write_config; 1413 pci_dev->config_read = config_read; 1414 pci_dev->config_write = config_write; 1415 bus->devices[devfn] = pci_dev; 1416 pci_dev->version_id = 2; /* Current pci device vmstate version */ 1417 return pci_dev; 1418 } 1419 1420 static void pci_unregister_io_regions(PCIDevice *pci_dev) 1421 { 1422 PCIIORegion *r; 1423 int i; 1424 1425 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1426 r = &pci_dev->io_regions[i]; 1427 if (!r->size || r->addr == PCI_BAR_UNMAPPED) 1428 continue; 1429 memory_region_del_subregion(r->address_space, r->memory); 1430 } 1431 1432 pci_unregister_vga(pci_dev); 1433 } 1434 1435 static void pci_qdev_unrealize(DeviceState *dev) 1436 { 1437 PCIDevice *pci_dev = PCI_DEVICE(dev); 1438 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 1439 1440 pci_unregister_io_regions(pci_dev); 1441 pci_del_option_rom(pci_dev); 1442 1443 if (pc->exit) { 1444 pc->exit(pci_dev); 1445 } 1446 1447 pci_device_deassert_intx(pci_dev); 1448 do_pci_unregister_device(pci_dev); 1449 1450 pci_dev->msi_trigger = NULL; 1451 1452 /* 1453 * clean up acpi-index so it could reused by another device 1454 */ 1455 if (pci_dev->acpi_index) { 1456 GSequence *used_indexes = pci_acpi_index_list(); 1457 1458 g_sequence_remove(g_sequence_lookup(used_indexes, 1459 GINT_TO_POINTER(pci_dev->acpi_index), 1460 g_cmp_uint32, NULL)); 1461 } 1462 } 1463 1464 void pci_register_bar(PCIDevice *pci_dev, int region_num, 1465 uint8_t type, MemoryRegion *memory) 1466 { 1467 PCIIORegion *r; 1468 uint32_t addr; /* offset in pci config space */ 1469 uint64_t wmask; 1470 pcibus_t size = memory_region_size(memory); 1471 uint8_t hdr_type; 1472 1473 assert(!pci_is_vf(pci_dev)); /* VFs must use pcie_sriov_vf_register_bar */ 1474 assert(region_num >= 0); 1475 assert(region_num < PCI_NUM_REGIONS); 1476 assert(is_power_of_2(size)); 1477 1478 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ 1479 hdr_type = 1480 pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; 1481 assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); 1482 1483 r = &pci_dev->io_regions[region_num]; 1484 assert(!r->size); 1485 r->addr = PCI_BAR_UNMAPPED; 1486 r->size = size; 1487 r->type = type; 1488 r->memory = memory; 1489 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO 1490 ? pci_get_bus(pci_dev)->address_space_io 1491 : pci_get_bus(pci_dev)->address_space_mem; 1492 1493 wmask = ~(size - 1); 1494 if (region_num == PCI_ROM_SLOT) { 1495 /* ROM enable bit is writable */ 1496 wmask |= PCI_ROM_ADDRESS_ENABLE; 1497 } 1498 1499 addr = pci_bar(pci_dev, region_num); 1500 pci_set_long(pci_dev->config + addr, type); 1501 1502 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && 1503 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1504 pci_set_quad(pci_dev->wmask + addr, wmask); 1505 pci_set_quad(pci_dev->cmask + addr, ~0ULL); 1506 } else { 1507 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); 1508 pci_set_long(pci_dev->cmask + addr, 0xffffffff); 1509 } 1510 } 1511 1512 static void pci_update_vga(PCIDevice *pci_dev) 1513 { 1514 uint16_t cmd; 1515 1516 if (!pci_dev->has_vga) { 1517 return; 1518 } 1519 1520 cmd = pci_get_word(pci_dev->config + PCI_COMMAND); 1521 1522 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], 1523 cmd & PCI_COMMAND_MEMORY); 1524 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], 1525 cmd & PCI_COMMAND_IO); 1526 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], 1527 cmd & PCI_COMMAND_IO); 1528 } 1529 1530 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, 1531 MemoryRegion *io_lo, MemoryRegion *io_hi) 1532 { 1533 PCIBus *bus = pci_get_bus(pci_dev); 1534 1535 assert(!pci_dev->has_vga); 1536 1537 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); 1538 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; 1539 memory_region_add_subregion_overlap(bus->address_space_mem, 1540 QEMU_PCI_VGA_MEM_BASE, mem, 1); 1541 1542 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); 1543 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; 1544 memory_region_add_subregion_overlap(bus->address_space_io, 1545 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); 1546 1547 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); 1548 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; 1549 memory_region_add_subregion_overlap(bus->address_space_io, 1550 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); 1551 pci_dev->has_vga = true; 1552 1553 pci_update_vga(pci_dev); 1554 } 1555 1556 void pci_unregister_vga(PCIDevice *pci_dev) 1557 { 1558 PCIBus *bus = pci_get_bus(pci_dev); 1559 1560 if (!pci_dev->has_vga) { 1561 return; 1562 } 1563 1564 memory_region_del_subregion(bus->address_space_mem, 1565 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); 1566 memory_region_del_subregion(bus->address_space_io, 1567 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); 1568 memory_region_del_subregion(bus->address_space_io, 1569 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); 1570 pci_dev->has_vga = false; 1571 } 1572 1573 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) 1574 { 1575 return pci_dev->io_regions[region_num].addr; 1576 } 1577 1578 static pcibus_t pci_config_get_bar_addr(PCIDevice *d, int reg, 1579 uint8_t type, pcibus_t size) 1580 { 1581 pcibus_t new_addr; 1582 if (!pci_is_vf(d)) { 1583 int bar = pci_bar(d, reg); 1584 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1585 new_addr = pci_get_quad(d->config + bar); 1586 } else { 1587 new_addr = pci_get_long(d->config + bar); 1588 } 1589 } else { 1590 PCIDevice *pf = d->exp.sriov_vf.pf; 1591 uint16_t sriov_cap = pf->exp.sriov_cap; 1592 int bar = sriov_cap + PCI_SRIOV_BAR + reg * 4; 1593 uint16_t vf_offset = 1594 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_OFFSET); 1595 uint16_t vf_stride = 1596 pci_get_word(pf->config + sriov_cap + PCI_SRIOV_VF_STRIDE); 1597 uint32_t vf_num = (d->devfn - (pf->devfn + vf_offset)) / vf_stride; 1598 1599 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 1600 new_addr = pci_get_quad(pf->config + bar); 1601 } else { 1602 new_addr = pci_get_long(pf->config + bar); 1603 } 1604 new_addr += vf_num * size; 1605 } 1606 /* The ROM slot has a specific enable bit, keep it intact */ 1607 if (reg != PCI_ROM_SLOT) { 1608 new_addr &= ~(size - 1); 1609 } 1610 return new_addr; 1611 } 1612 1613 pcibus_t pci_bar_address(PCIDevice *d, 1614 int reg, uint8_t type, pcibus_t size) 1615 { 1616 pcibus_t new_addr, last_addr; 1617 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); 1618 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 1619 bool allow_0_address = mc->pci_allow_0_address; 1620 1621 if (type & PCI_BASE_ADDRESS_SPACE_IO) { 1622 if (!(cmd & PCI_COMMAND_IO)) { 1623 return PCI_BAR_UNMAPPED; 1624 } 1625 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1626 last_addr = new_addr + size - 1; 1627 /* Check if 32 bit BAR wraps around explicitly. 1628 * TODO: make priorities correct and remove this work around. 1629 */ 1630 if (last_addr <= new_addr || last_addr >= UINT32_MAX || 1631 (!allow_0_address && new_addr == 0)) { 1632 return PCI_BAR_UNMAPPED; 1633 } 1634 return new_addr; 1635 } 1636 1637 if (!(cmd & PCI_COMMAND_MEMORY)) { 1638 return PCI_BAR_UNMAPPED; 1639 } 1640 new_addr = pci_config_get_bar_addr(d, reg, type, size); 1641 /* the ROM slot has a specific enable bit */ 1642 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { 1643 return PCI_BAR_UNMAPPED; 1644 } 1645 new_addr &= ~(size - 1); 1646 last_addr = new_addr + size - 1; 1647 /* NOTE: we do not support wrapping */ 1648 /* XXX: as we cannot support really dynamic 1649 mappings, we handle specific values as invalid 1650 mappings. */ 1651 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || 1652 (!allow_0_address && new_addr == 0)) { 1653 return PCI_BAR_UNMAPPED; 1654 } 1655 1656 /* Now pcibus_t is 64bit. 1657 * Check if 32 bit BAR wraps around explicitly. 1658 * Without this, PC ide doesn't work well. 1659 * TODO: remove this work around. 1660 */ 1661 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { 1662 return PCI_BAR_UNMAPPED; 1663 } 1664 1665 /* 1666 * OS is allowed to set BAR beyond its addressable 1667 * bits. For example, 32 bit OS can set 64bit bar 1668 * to >4G. Check it. TODO: we might need to support 1669 * it in the future for e.g. PAE. 1670 */ 1671 if (last_addr >= HWADDR_MAX) { 1672 return PCI_BAR_UNMAPPED; 1673 } 1674 1675 return new_addr; 1676 } 1677 1678 static void pci_update_mappings(PCIDevice *d) 1679 { 1680 PCIIORegion *r; 1681 int i; 1682 pcibus_t new_addr; 1683 1684 for(i = 0; i < PCI_NUM_REGIONS; i++) { 1685 r = &d->io_regions[i]; 1686 1687 /* this region isn't registered */ 1688 if (!r->size) 1689 continue; 1690 1691 new_addr = pci_bar_address(d, i, r->type, r->size); 1692 if (!d->enabled || pci_pm_state(d)) { 1693 new_addr = PCI_BAR_UNMAPPED; 1694 } 1695 1696 /* This bar isn't changed */ 1697 if (new_addr == r->addr) 1698 continue; 1699 1700 /* now do the real mapping */ 1701 if (r->addr != PCI_BAR_UNMAPPED) { 1702 trace_pci_update_mappings_del(d->name, pci_dev_bus_num(d), 1703 PCI_SLOT(d->devfn), 1704 PCI_FUNC(d->devfn), 1705 i, r->addr, r->size); 1706 memory_region_del_subregion(r->address_space, r->memory); 1707 } 1708 r->addr = new_addr; 1709 if (r->addr != PCI_BAR_UNMAPPED) { 1710 trace_pci_update_mappings_add(d->name, pci_dev_bus_num(d), 1711 PCI_SLOT(d->devfn), 1712 PCI_FUNC(d->devfn), 1713 i, r->addr, r->size); 1714 memory_region_add_subregion_overlap(r->address_space, 1715 r->addr, r->memory, 1); 1716 } 1717 } 1718 1719 pci_update_vga(d); 1720 } 1721 1722 static inline int pci_irq_disabled(PCIDevice *d) 1723 { 1724 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; 1725 } 1726 1727 /* Called after interrupt disabled field update in config space, 1728 * assert/deassert interrupts if necessary. 1729 * Gets original interrupt disable bit value (before update). */ 1730 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) 1731 { 1732 int i, disabled = pci_irq_disabled(d); 1733 if (disabled == was_irq_disabled) 1734 return; 1735 for (i = 0; i < PCI_NUM_PINS; ++i) { 1736 int state = pci_irq_state(d, i); 1737 pci_change_irq_level(d, i, disabled ? -state : state); 1738 } 1739 } 1740 1741 uint32_t pci_default_read_config(PCIDevice *d, 1742 uint32_t address, int len) 1743 { 1744 uint32_t val = 0; 1745 1746 assert(address + len <= pci_config_size(d)); 1747 1748 if (pci_is_express_downstream_port(d) && 1749 ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { 1750 pcie_sync_bridge_lnk(d); 1751 } 1752 memcpy(&val, d->config + address, len); 1753 return le32_to_cpu(val); 1754 } 1755 1756 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) 1757 { 1758 uint8_t new_pm_state, old_pm_state = pci_pm_state(d); 1759 int i, was_irq_disabled = pci_irq_disabled(d); 1760 uint32_t val = val_in; 1761 1762 assert(addr + l <= pci_config_size(d)); 1763 1764 for (i = 0; i < l; val >>= 8, ++i) { 1765 uint8_t wmask = d->wmask[addr + i]; 1766 uint8_t w1cmask = d->w1cmask[addr + i]; 1767 assert(!(wmask & w1cmask)); 1768 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); 1769 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 1770 } 1771 1772 new_pm_state = pci_pm_update(d, addr, l, old_pm_state); 1773 1774 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || 1775 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || 1776 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || 1777 range_covers_byte(addr, l, PCI_COMMAND) || 1778 !!new_pm_state != !!old_pm_state) { 1779 pci_update_mappings(d); 1780 } 1781 1782 if (ranges_overlap(addr, l, PCI_COMMAND, 2)) { 1783 pci_update_irq_disabled(d, was_irq_disabled); 1784 memory_region_set_enabled(&d->bus_master_enable_region, 1785 (pci_get_word(d->config + PCI_COMMAND) 1786 & PCI_COMMAND_MASTER) && d->enabled); 1787 } 1788 1789 msi_write_config(d, addr, val_in, l); 1790 msix_write_config(d, addr, val_in, l); 1791 pcie_sriov_config_write(d, addr, val_in, l); 1792 } 1793 1794 /***********************************************************/ 1795 /* generic PCI irq support */ 1796 1797 /* 0 <= irq_num <= 3. level must be 0 or 1 */ 1798 static void pci_irq_handler(void *opaque, int irq_num, int level) 1799 { 1800 PCIDevice *pci_dev = opaque; 1801 int change; 1802 1803 assert(0 <= irq_num && irq_num < PCI_NUM_PINS); 1804 assert(level == 0 || level == 1); 1805 change = level - pci_irq_state(pci_dev, irq_num); 1806 if (!change) 1807 return; 1808 1809 pci_set_irq_state(pci_dev, irq_num, level); 1810 pci_update_irq_status(pci_dev); 1811 if (pci_irq_disabled(pci_dev)) 1812 return; 1813 pci_change_irq_level(pci_dev, irq_num, change); 1814 } 1815 1816 qemu_irq pci_allocate_irq(PCIDevice *pci_dev) 1817 { 1818 int intx = pci_intx(pci_dev); 1819 assert(0 <= intx && intx < PCI_NUM_PINS); 1820 1821 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); 1822 } 1823 1824 void pci_set_irq(PCIDevice *pci_dev, int level) 1825 { 1826 int intx = pci_intx(pci_dev); 1827 pci_irq_handler(pci_dev, intx, level); 1828 } 1829 1830 /* Special hooks used by device assignment */ 1831 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) 1832 { 1833 assert(pci_bus_is_root(bus)); 1834 bus->route_intx_to_irq = route_intx_to_irq; 1835 } 1836 1837 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) 1838 { 1839 PCIBus *bus; 1840 1841 do { 1842 int dev_irq = pin; 1843 bus = pci_get_bus(dev); 1844 pin = bus->map_irq(dev, pin); 1845 trace_pci_route_irq(dev_irq, DEVICE(dev)->canonical_path, pin, 1846 pci_bus_is_root(bus) ? "root-complex" 1847 : DEVICE(bus->parent_dev)->canonical_path); 1848 dev = bus->parent_dev; 1849 } while (dev); 1850 1851 if (!bus->route_intx_to_irq) { 1852 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)", 1853 object_get_typename(OBJECT(bus->qbus.parent))); 1854 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; 1855 } 1856 1857 return bus->route_intx_to_irq(bus->irq_opaque, pin); 1858 } 1859 1860 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) 1861 { 1862 return old->mode != new->mode || old->irq != new->irq; 1863 } 1864 1865 void pci_bus_fire_intx_routing_notifier(PCIBus *bus) 1866 { 1867 PCIDevice *dev; 1868 PCIBus *sec; 1869 int i; 1870 1871 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 1872 dev = bus->devices[i]; 1873 if (dev && dev->intx_routing_notifier) { 1874 dev->intx_routing_notifier(dev); 1875 } 1876 } 1877 1878 QLIST_FOREACH(sec, &bus->child, sibling) { 1879 pci_bus_fire_intx_routing_notifier(sec); 1880 } 1881 } 1882 1883 void pci_device_set_intx_routing_notifier(PCIDevice *dev, 1884 PCIINTxRoutingNotifier notifier) 1885 { 1886 dev->intx_routing_notifier = notifier; 1887 } 1888 1889 /* 1890 * PCI-to-PCI bridge specification 1891 * 9.1: Interrupt routing. Table 9-1 1892 * 1893 * the PCI Express Base Specification, Revision 2.1 1894 * 2.2.8.1: INTx interrupt signaling - Rules 1895 * the Implementation Note 1896 * Table 2-20 1897 */ 1898 /* 1899 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD 1900 * 0-origin unlike PCI interrupt pin register. 1901 */ 1902 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) 1903 { 1904 return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); 1905 } 1906 1907 /***********************************************************/ 1908 /* monitor info on PCI */ 1909 1910 static const pci_class_desc pci_class_descriptions[] = 1911 { 1912 { 0x0001, "VGA controller", "display"}, 1913 { 0x0100, "SCSI controller", "scsi"}, 1914 { 0x0101, "IDE controller", "ide"}, 1915 { 0x0102, "Floppy controller", "fdc"}, 1916 { 0x0103, "IPI controller", "ipi"}, 1917 { 0x0104, "RAID controller", "raid"}, 1918 { 0x0106, "SATA controller"}, 1919 { 0x0107, "SAS controller"}, 1920 { 0x0180, "Storage controller"}, 1921 { 0x0200, "Ethernet controller", "ethernet"}, 1922 { 0x0201, "Token Ring controller", "token-ring"}, 1923 { 0x0202, "FDDI controller", "fddi"}, 1924 { 0x0203, "ATM controller", "atm"}, 1925 { 0x0280, "Network controller"}, 1926 { 0x0300, "VGA controller", "display", 0x00ff}, 1927 { 0x0301, "XGA controller"}, 1928 { 0x0302, "3D controller"}, 1929 { 0x0380, "Display controller"}, 1930 { 0x0400, "Video controller", "video"}, 1931 { 0x0401, "Audio controller", "sound"}, 1932 { 0x0402, "Phone"}, 1933 { 0x0403, "Audio controller", "sound"}, 1934 { 0x0480, "Multimedia controller"}, 1935 { 0x0500, "RAM controller", "memory"}, 1936 { 0x0501, "Flash controller", "flash"}, 1937 { 0x0580, "Memory controller"}, 1938 { 0x0600, "Host bridge", "host"}, 1939 { 0x0601, "ISA bridge", "isa"}, 1940 { 0x0602, "EISA bridge", "eisa"}, 1941 { 0x0603, "MC bridge", "mca"}, 1942 { 0x0604, "PCI bridge", "pci-bridge"}, 1943 { 0x0605, "PCMCIA bridge", "pcmcia"}, 1944 { 0x0606, "NUBUS bridge", "nubus"}, 1945 { 0x0607, "CARDBUS bridge", "cardbus"}, 1946 { 0x0608, "RACEWAY bridge"}, 1947 { 0x0680, "Bridge"}, 1948 { 0x0700, "Serial port", "serial"}, 1949 { 0x0701, "Parallel port", "parallel"}, 1950 { 0x0800, "Interrupt controller", "interrupt-controller"}, 1951 { 0x0801, "DMA controller", "dma-controller"}, 1952 { 0x0802, "Timer", "timer"}, 1953 { 0x0803, "RTC", "rtc"}, 1954 { 0x0900, "Keyboard", "keyboard"}, 1955 { 0x0901, "Pen", "pen"}, 1956 { 0x0902, "Mouse", "mouse"}, 1957 { 0x0A00, "Dock station", "dock", 0x00ff}, 1958 { 0x0B00, "i386 cpu", "cpu", 0x00ff}, 1959 { 0x0c00, "Firewire controller", "firewire"}, 1960 { 0x0c01, "Access bus controller", "access-bus"}, 1961 { 0x0c02, "SSA controller", "ssa"}, 1962 { 0x0c03, "USB controller", "usb"}, 1963 { 0x0c04, "Fibre channel controller", "fibre-channel"}, 1964 { 0x0c05, "SMBus"}, 1965 { 0, NULL} 1966 }; 1967 1968 void pci_for_each_device_under_bus_reverse(PCIBus *bus, 1969 pci_bus_dev_fn fn, 1970 void *opaque) 1971 { 1972 PCIDevice *d; 1973 int devfn; 1974 1975 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 1976 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; 1977 if (d) { 1978 fn(bus, d, opaque); 1979 } 1980 } 1981 } 1982 1983 void pci_for_each_device_reverse(PCIBus *bus, int bus_num, 1984 pci_bus_dev_fn fn, void *opaque) 1985 { 1986 bus = pci_find_bus_nr(bus, bus_num); 1987 1988 if (bus) { 1989 pci_for_each_device_under_bus_reverse(bus, fn, opaque); 1990 } 1991 } 1992 1993 void pci_for_each_device_under_bus(PCIBus *bus, 1994 pci_bus_dev_fn fn, void *opaque) 1995 { 1996 PCIDevice *d; 1997 int devfn; 1998 1999 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 2000 d = bus->devices[devfn]; 2001 if (d) { 2002 fn(bus, d, opaque); 2003 } 2004 } 2005 } 2006 2007 void pci_for_each_device(PCIBus *bus, int bus_num, 2008 pci_bus_dev_fn fn, void *opaque) 2009 { 2010 bus = pci_find_bus_nr(bus, bus_num); 2011 2012 if (bus) { 2013 pci_for_each_device_under_bus(bus, fn, opaque); 2014 } 2015 } 2016 2017 const pci_class_desc *get_class_desc(int class) 2018 { 2019 const pci_class_desc *desc; 2020 2021 desc = pci_class_descriptions; 2022 while (desc->desc && class != desc->class) { 2023 desc++; 2024 } 2025 2026 return desc; 2027 } 2028 2029 void pci_init_nic_devices(PCIBus *bus, const char *default_model) 2030 { 2031 qemu_create_nic_bus_devices(&bus->qbus, TYPE_PCI_DEVICE, default_model, 2032 "virtio", "virtio-net-pci"); 2033 } 2034 2035 bool pci_init_nic_in_slot(PCIBus *rootbus, const char *model, 2036 const char *alias, const char *devaddr) 2037 { 2038 NICInfo *nd = qemu_find_nic_info(model, true, alias); 2039 int dom, busnr, devfn; 2040 PCIDevice *pci_dev; 2041 unsigned slot; 2042 PCIBus *bus; 2043 2044 if (!nd) { 2045 return false; 2046 } 2047 2048 if (!devaddr || pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { 2049 error_report("Invalid PCI device address %s for device %s", 2050 devaddr, model); 2051 exit(1); 2052 } 2053 2054 if (dom != 0) { 2055 error_report("No support for non-zero PCI domains"); 2056 exit(1); 2057 } 2058 2059 devfn = PCI_DEVFN(slot, 0); 2060 2061 bus = pci_find_bus_nr(rootbus, busnr); 2062 if (!bus) { 2063 error_report("Invalid PCI device address %s for device %s", 2064 devaddr, model); 2065 exit(1); 2066 } 2067 2068 pci_dev = pci_new(devfn, model); 2069 qdev_set_nic_properties(&pci_dev->qdev, nd); 2070 pci_realize_and_unref(pci_dev, bus, &error_fatal); 2071 return true; 2072 } 2073 2074 PCIDevice *pci_vga_init(PCIBus *bus) 2075 { 2076 vga_interface_created = true; 2077 switch (vga_interface_type) { 2078 case VGA_CIRRUS: 2079 return pci_create_simple(bus, -1, "cirrus-vga"); 2080 case VGA_QXL: 2081 return pci_create_simple(bus, -1, "qxl-vga"); 2082 case VGA_STD: 2083 return pci_create_simple(bus, -1, "VGA"); 2084 case VGA_VMWARE: 2085 return pci_create_simple(bus, -1, "vmware-svga"); 2086 case VGA_VIRTIO: 2087 return pci_create_simple(bus, -1, "virtio-vga"); 2088 case VGA_NONE: 2089 default: /* Other non-PCI types. Checking for unsupported types is already 2090 done in vl.c. */ 2091 return NULL; 2092 } 2093 } 2094 2095 /* Whether a given bus number is in range of the secondary 2096 * bus of the given bridge device. */ 2097 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) 2098 { 2099 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & 2100 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && 2101 dev->config[PCI_SECONDARY_BUS] <= bus_num && 2102 bus_num <= dev->config[PCI_SUBORDINATE_BUS]; 2103 } 2104 2105 /* Whether a given bus number is in a range of a root bus */ 2106 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) 2107 { 2108 int i; 2109 2110 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { 2111 PCIDevice *dev = bus->devices[i]; 2112 2113 if (dev && IS_PCI_BRIDGE(dev)) { 2114 if (pci_secondary_bus_in_range(dev, bus_num)) { 2115 return true; 2116 } 2117 } 2118 } 2119 2120 return false; 2121 } 2122 2123 PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) 2124 { 2125 PCIBus *sec; 2126 2127 if (!bus) { 2128 return NULL; 2129 } 2130 2131 if (pci_bus_num(bus) == bus_num) { 2132 return bus; 2133 } 2134 2135 /* Consider all bus numbers in range for the host pci bridge. */ 2136 if (!pci_bus_is_root(bus) && 2137 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { 2138 return NULL; 2139 } 2140 2141 /* try child bus */ 2142 for (; bus; bus = sec) { 2143 QLIST_FOREACH(sec, &bus->child, sibling) { 2144 if (pci_bus_num(sec) == bus_num) { 2145 return sec; 2146 } 2147 /* PXB buses assumed to be children of bus 0 */ 2148 if (pci_bus_is_root(sec)) { 2149 if (pci_root_bus_in_range(sec, bus_num)) { 2150 break; 2151 } 2152 } else { 2153 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { 2154 break; 2155 } 2156 } 2157 } 2158 } 2159 2160 return NULL; 2161 } 2162 2163 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin, 2164 pci_bus_fn end, void *parent_state) 2165 { 2166 PCIBus *sec; 2167 void *state; 2168 2169 if (!bus) { 2170 return; 2171 } 2172 2173 if (begin) { 2174 state = begin(bus, parent_state); 2175 } else { 2176 state = parent_state; 2177 } 2178 2179 QLIST_FOREACH(sec, &bus->child, sibling) { 2180 pci_for_each_bus_depth_first(sec, begin, end, state); 2181 } 2182 2183 if (end) { 2184 end(bus, state); 2185 } 2186 } 2187 2188 2189 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) 2190 { 2191 bus = pci_find_bus_nr(bus, bus_num); 2192 2193 if (!bus) 2194 return NULL; 2195 2196 return bus->devices[devfn]; 2197 } 2198 2199 #define ONBOARD_INDEX_MAX (16 * 1024 - 1) 2200 2201 static void pci_qdev_realize(DeviceState *qdev, Error **errp) 2202 { 2203 PCIDevice *pci_dev = (PCIDevice *)qdev; 2204 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); 2205 ObjectClass *klass = OBJECT_CLASS(pc); 2206 Error *local_err = NULL; 2207 bool is_default_rom; 2208 uint16_t class_id; 2209 2210 /* 2211 * capped by systemd (see: udev-builtin-net_id.c) 2212 * as it's the only known user honor it to avoid users 2213 * misconfigure QEMU and then wonder why acpi-index doesn't work 2214 */ 2215 if (pci_dev->acpi_index > ONBOARD_INDEX_MAX) { 2216 error_setg(errp, "acpi-index should be less or equal to %u", 2217 ONBOARD_INDEX_MAX); 2218 return; 2219 } 2220 2221 /* 2222 * make sure that acpi-index is unique across all present PCI devices 2223 */ 2224 if (pci_dev->acpi_index) { 2225 GSequence *used_indexes = pci_acpi_index_list(); 2226 2227 if (g_sequence_lookup(used_indexes, 2228 GINT_TO_POINTER(pci_dev->acpi_index), 2229 g_cmp_uint32, NULL)) { 2230 error_setg(errp, "a PCI device with acpi-index = %" PRIu32 2231 " already exist", pci_dev->acpi_index); 2232 return; 2233 } 2234 g_sequence_insert_sorted(used_indexes, 2235 GINT_TO_POINTER(pci_dev->acpi_index), 2236 g_cmp_uint32, NULL); 2237 } 2238 2239 if (pci_dev->romsize != UINT32_MAX && !is_power_of_2(pci_dev->romsize)) { 2240 error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize); 2241 return; 2242 } 2243 2244 /* initialize cap_present for pci_is_express() and pci_config_size(), 2245 * Note that hybrid PCIs are not set automatically and need to manage 2246 * QEMU_PCI_CAP_EXPRESS manually */ 2247 if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && 2248 !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { 2249 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 2250 } 2251 2252 if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { 2253 pci_dev->cap_present |= QEMU_PCIE_CAP_CXL; 2254 } 2255 2256 pci_dev = do_pci_register_device(pci_dev, 2257 object_get_typename(OBJECT(qdev)), 2258 pci_dev->devfn, errp); 2259 if (pci_dev == NULL) 2260 return; 2261 2262 if (pc->realize) { 2263 pc->realize(pci_dev, &local_err); 2264 if (local_err) { 2265 error_propagate(errp, local_err); 2266 do_pci_unregister_device(pci_dev); 2267 return; 2268 } 2269 } 2270 2271 /* 2272 * A PCIe Downstream Port that do not have ARI Forwarding enabled must 2273 * associate only Device 0 with the device attached to the bus 2274 * representing the Link from the Port (PCIe base spec rev 4.0 ver 0.3, 2275 * sec 7.3.1). 2276 * With ARI, PCI_SLOT() can return non-zero value as the traditional 2277 * 5-bit Device Number and 3-bit Function Number fields in its associated 2278 * Routing IDs, Requester IDs and Completer IDs are interpreted as a 2279 * single 8-bit Function Number. Hence, ignore ARI capable devices. 2280 */ 2281 if (pci_is_express(pci_dev) && 2282 !pcie_find_capability(pci_dev, PCI_EXT_CAP_ID_ARI) && 2283 pcie_has_upstream_port(pci_dev) && 2284 PCI_SLOT(pci_dev->devfn)) { 2285 warn_report("PCI: slot %d is not valid for %s," 2286 " parent device only allows plugging into slot 0.", 2287 PCI_SLOT(pci_dev->devfn), pci_dev->name); 2288 } 2289 2290 if (pci_dev->failover_pair_id) { 2291 if (!pci_bus_is_express(pci_get_bus(pci_dev))) { 2292 error_setg(errp, "failover primary device must be on " 2293 "PCIExpress bus"); 2294 pci_qdev_unrealize(DEVICE(pci_dev)); 2295 return; 2296 } 2297 class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE); 2298 if (class_id != PCI_CLASS_NETWORK_ETHERNET) { 2299 error_setg(errp, "failover primary device is not an " 2300 "Ethernet device"); 2301 pci_qdev_unrealize(DEVICE(pci_dev)); 2302 return; 2303 } 2304 if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) 2305 || (PCI_FUNC(pci_dev->devfn) != 0)) { 2306 error_setg(errp, "failover: primary device must be in its own " 2307 "PCI slot"); 2308 pci_qdev_unrealize(DEVICE(pci_dev)); 2309 return; 2310 } 2311 qdev->allow_unplug_during_migration = true; 2312 } 2313 2314 /* rom loading */ 2315 is_default_rom = false; 2316 if (pci_dev->romfile == NULL && pc->romfile != NULL) { 2317 pci_dev->romfile = g_strdup(pc->romfile); 2318 is_default_rom = true; 2319 } 2320 2321 pci_add_option_rom(pci_dev, is_default_rom, &local_err); 2322 if (local_err) { 2323 error_propagate(errp, local_err); 2324 pci_qdev_unrealize(DEVICE(pci_dev)); 2325 return; 2326 } 2327 2328 pci_set_power(pci_dev, true); 2329 2330 pci_dev->msi_trigger = pci_msi_trigger; 2331 } 2332 2333 static PCIDevice *pci_new_internal(int devfn, bool multifunction, 2334 const char *name) 2335 { 2336 DeviceState *dev; 2337 2338 dev = qdev_new(name); 2339 qdev_prop_set_int32(dev, "addr", devfn); 2340 qdev_prop_set_bit(dev, "multifunction", multifunction); 2341 return PCI_DEVICE(dev); 2342 } 2343 2344 PCIDevice *pci_new_multifunction(int devfn, const char *name) 2345 { 2346 return pci_new_internal(devfn, true, name); 2347 } 2348 2349 PCIDevice *pci_new(int devfn, const char *name) 2350 { 2351 return pci_new_internal(devfn, false, name); 2352 } 2353 2354 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) 2355 { 2356 return qdev_realize_and_unref(&dev->qdev, &bus->qbus, errp); 2357 } 2358 2359 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, 2360 const char *name) 2361 { 2362 PCIDevice *dev = pci_new_multifunction(devfn, name); 2363 pci_realize_and_unref(dev, bus, &error_fatal); 2364 return dev; 2365 } 2366 2367 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) 2368 { 2369 PCIDevice *dev = pci_new(devfn, name); 2370 pci_realize_and_unref(dev, bus, &error_fatal); 2371 return dev; 2372 } 2373 2374 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) 2375 { 2376 int offset = PCI_CONFIG_HEADER_SIZE; 2377 int i; 2378 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { 2379 if (pdev->used[i]) 2380 offset = i + 1; 2381 else if (i - offset + 1 == size) 2382 return offset; 2383 } 2384 return 0; 2385 } 2386 2387 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, 2388 uint8_t *prev_p) 2389 { 2390 uint8_t next, prev; 2391 2392 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) 2393 return 0; 2394 2395 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2396 prev = next + PCI_CAP_LIST_NEXT) 2397 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) 2398 break; 2399 2400 if (prev_p) 2401 *prev_p = prev; 2402 return next; 2403 } 2404 2405 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) 2406 { 2407 uint8_t next, prev, found = 0; 2408 2409 if (!(pdev->used[offset])) { 2410 return 0; 2411 } 2412 2413 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); 2414 2415 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); 2416 prev = next + PCI_CAP_LIST_NEXT) { 2417 if (next <= offset && next > found) { 2418 found = next; 2419 } 2420 } 2421 return found; 2422 } 2423 2424 /* Patch the PCI vendor and device ids in a PCI rom image if necessary. 2425 This is needed for an option rom which is used for more than one device. */ 2426 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, uint32_t size) 2427 { 2428 uint16_t vendor_id; 2429 uint16_t device_id; 2430 uint16_t rom_vendor_id; 2431 uint16_t rom_device_id; 2432 uint16_t rom_magic; 2433 uint16_t pcir_offset; 2434 uint8_t checksum; 2435 2436 /* Words in rom data are little endian (like in PCI configuration), 2437 so they can be read / written with pci_get_word / pci_set_word. */ 2438 2439 /* Only a valid rom will be patched. */ 2440 rom_magic = pci_get_word(ptr); 2441 if (rom_magic != 0xaa55) { 2442 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic); 2443 return; 2444 } 2445 pcir_offset = pci_get_word(ptr + 0x18); 2446 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { 2447 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset); 2448 return; 2449 } 2450 2451 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); 2452 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); 2453 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); 2454 rom_device_id = pci_get_word(ptr + pcir_offset + 6); 2455 2456 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile, 2457 vendor_id, device_id, rom_vendor_id, rom_device_id); 2458 2459 checksum = ptr[6]; 2460 2461 if (vendor_id != rom_vendor_id) { 2462 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ 2463 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); 2464 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); 2465 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2466 ptr[6] = checksum; 2467 pci_set_word(ptr + pcir_offset + 4, vendor_id); 2468 } 2469 2470 if (device_id != rom_device_id) { 2471 /* Patch device id and checksum (at offset 6 for etherboot roms). */ 2472 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); 2473 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); 2474 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); 2475 ptr[6] = checksum; 2476 pci_set_word(ptr + pcir_offset + 6, device_id); 2477 } 2478 } 2479 2480 /* Add an option rom for the device */ 2481 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, 2482 Error **errp) 2483 { 2484 int64_t size = 0; 2485 g_autofree char *path = NULL; 2486 char name[32]; 2487 const VMStateDescription *vmsd; 2488 2489 /* 2490 * In case of incoming migration ROM will come with migration stream, no 2491 * reason to load the file. Neither we want to fail if local ROM file 2492 * mismatches with specified romsize. 2493 */ 2494 bool load_file = !runstate_check(RUN_STATE_INMIGRATE); 2495 2496 if (!pdev->romfile || !strlen(pdev->romfile)) { 2497 return; 2498 } 2499 2500 if (!pdev->rom_bar) { 2501 /* 2502 * Load rom via fw_cfg instead of creating a rom bar, 2503 * for 0.11 compatibility. 2504 */ 2505 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); 2506 2507 /* 2508 * Hot-plugged devices can't use the option ROM 2509 * if the rom bar is disabled. 2510 */ 2511 if (DEVICE(pdev)->hotplugged) { 2512 error_setg(errp, "Hot-plugged device without ROM bar" 2513 " can't have an option ROM"); 2514 return; 2515 } 2516 2517 if (class == 0x0300) { 2518 rom_add_vga(pdev->romfile); 2519 } else { 2520 rom_add_option(pdev->romfile, -1); 2521 } 2522 return; 2523 } 2524 2525 if (load_file || pdev->romsize == UINT32_MAX) { 2526 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); 2527 if (path == NULL) { 2528 path = g_strdup(pdev->romfile); 2529 } 2530 2531 size = get_image_size(path); 2532 if (size < 0) { 2533 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile); 2534 return; 2535 } else if (size == 0) { 2536 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile); 2537 return; 2538 } else if (size > 2 * GiB) { 2539 error_setg(errp, 2540 "romfile \"%s\" too large (size cannot exceed 2 GiB)", 2541 pdev->romfile); 2542 return; 2543 } 2544 if (pdev->romsize != UINT_MAX) { 2545 if (size > pdev->romsize) { 2546 error_setg(errp, "romfile \"%s\" (%u bytes) " 2547 "is too large for ROM size %u", 2548 pdev->romfile, (uint32_t)size, pdev->romsize); 2549 return; 2550 } 2551 } else { 2552 pdev->romsize = pow2ceil(size); 2553 } 2554 } 2555 2556 vmsd = qdev_get_vmsd(DEVICE(pdev)); 2557 snprintf(name, sizeof(name), "%s.rom", 2558 vmsd ? vmsd->name : object_get_typename(OBJECT(pdev))); 2559 2560 pdev->has_rom = true; 2561 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, pdev->romsize, 2562 &error_fatal); 2563 2564 if (load_file) { 2565 void *ptr = memory_region_get_ram_ptr(&pdev->rom); 2566 2567 if (load_image_size(path, ptr, size) < 0) { 2568 error_setg(errp, "failed to load romfile \"%s\"", pdev->romfile); 2569 return; 2570 } 2571 2572 if (is_default_rom) { 2573 /* Only the default rom images will be patched (if needed). */ 2574 pci_patch_ids(pdev, ptr, size); 2575 } 2576 } 2577 2578 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); 2579 } 2580 2581 static void pci_del_option_rom(PCIDevice *pdev) 2582 { 2583 if (!pdev->has_rom) 2584 return; 2585 2586 vmstate_unregister_ram(&pdev->rom, &pdev->qdev); 2587 pdev->has_rom = false; 2588 } 2589 2590 /* 2591 * On success, pci_add_capability() returns a positive value 2592 * that the offset of the pci capability. 2593 * On failure, it sets an error and returns a negative error 2594 * code. 2595 */ 2596 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, 2597 uint8_t offset, uint8_t size, 2598 Error **errp) 2599 { 2600 uint8_t *config; 2601 int i, overlapping_cap; 2602 2603 if (!offset) { 2604 offset = pci_find_space(pdev, size); 2605 /* out of PCI config space is programming error */ 2606 assert(offset); 2607 } else { 2608 /* Verify that capabilities don't overlap. Note: device assignment 2609 * depends on this check to verify that the device is not broken. 2610 * Should never trigger for emulated devices, but it's helpful 2611 * for debugging these. */ 2612 for (i = offset; i < offset + size; i++) { 2613 overlapping_cap = pci_find_capability_at_offset(pdev, i); 2614 if (overlapping_cap) { 2615 error_setg(errp, "%s:%02x:%02x.%x " 2616 "Attempt to add PCI capability %x at offset " 2617 "%x overlaps existing capability %x at offset %x", 2618 pci_root_bus_path(pdev), pci_dev_bus_num(pdev), 2619 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 2620 cap_id, offset, overlapping_cap, i); 2621 return -EINVAL; 2622 } 2623 } 2624 } 2625 2626 config = pdev->config + offset; 2627 config[PCI_CAP_LIST_ID] = cap_id; 2628 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; 2629 pdev->config[PCI_CAPABILITY_LIST] = offset; 2630 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; 2631 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); 2632 /* Make capability read-only by default */ 2633 memset(pdev->wmask + offset, 0, size); 2634 /* Check capability by default */ 2635 memset(pdev->cmask + offset, 0xFF, size); 2636 return offset; 2637 } 2638 2639 /* Unlink capability from the pci config space. */ 2640 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) 2641 { 2642 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); 2643 if (!offset) 2644 return; 2645 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; 2646 /* Make capability writable again */ 2647 memset(pdev->wmask + offset, 0xff, size); 2648 memset(pdev->w1cmask + offset, 0, size); 2649 /* Clear cmask as device-specific registers can't be checked */ 2650 memset(pdev->cmask + offset, 0, size); 2651 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); 2652 2653 if (!pdev->config[PCI_CAPABILITY_LIST]) 2654 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; 2655 } 2656 2657 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) 2658 { 2659 return pci_find_capability_list(pdev, cap_id, NULL); 2660 } 2661 2662 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) 2663 { 2664 PCIDevice *d = (PCIDevice *)dev; 2665 const char *name = NULL; 2666 const pci_class_desc *desc = pci_class_descriptions; 2667 int class = pci_get_word(d->config + PCI_CLASS_DEVICE); 2668 2669 while (desc->desc && 2670 (class & ~desc->fw_ign_bits) != 2671 (desc->class & ~desc->fw_ign_bits)) { 2672 desc++; 2673 } 2674 2675 if (desc->desc) { 2676 name = desc->fw_name; 2677 } 2678 2679 if (name) { 2680 pstrcpy(buf, len, name); 2681 } else { 2682 snprintf(buf, len, "pci%04x,%04x", 2683 pci_get_word(d->config + PCI_VENDOR_ID), 2684 pci_get_word(d->config + PCI_DEVICE_ID)); 2685 } 2686 2687 return buf; 2688 } 2689 2690 static char *pcibus_get_fw_dev_path(DeviceState *dev) 2691 { 2692 PCIDevice *d = (PCIDevice *)dev; 2693 char name[33]; 2694 int has_func = !!PCI_FUNC(d->devfn); 2695 2696 return g_strdup_printf("%s@%x%s%.*x", 2697 pci_dev_fw_name(dev, name, sizeof(name)), 2698 PCI_SLOT(d->devfn), 2699 has_func ? "," : "", 2700 has_func, 2701 PCI_FUNC(d->devfn)); 2702 } 2703 2704 static char *pcibus_get_dev_path(DeviceState *dev) 2705 { 2706 PCIDevice *d = container_of(dev, PCIDevice, qdev); 2707 PCIDevice *t; 2708 int slot_depth; 2709 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. 2710 * 00 is added here to make this format compatible with 2711 * domain:Bus:Slot.Func for systems without nested PCI bridges. 2712 * Slot.Function list specifies the slot and function numbers for all 2713 * devices on the path from root to the specific device. */ 2714 const char *root_bus_path; 2715 int root_bus_len; 2716 char slot[] = ":SS.F"; 2717 int slot_len = sizeof slot - 1 /* For '\0' */; 2718 int path_len; 2719 char *path, *p; 2720 int s; 2721 2722 root_bus_path = pci_root_bus_path(d); 2723 root_bus_len = strlen(root_bus_path); 2724 2725 /* Calculate # of slots on path between device and root. */; 2726 slot_depth = 0; 2727 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2728 ++slot_depth; 2729 } 2730 2731 path_len = root_bus_len + slot_len * slot_depth; 2732 2733 /* Allocate memory, fill in the terminating null byte. */ 2734 path = g_malloc(path_len + 1 /* For '\0' */); 2735 path[path_len] = '\0'; 2736 2737 memcpy(path, root_bus_path, root_bus_len); 2738 2739 /* Fill in slot numbers. We walk up from device to root, so need to print 2740 * them in the reverse order, last to first. */ 2741 p = path + path_len; 2742 for (t = d; t; t = pci_get_bus(t)->parent_dev) { 2743 p -= slot_len; 2744 s = snprintf(slot, sizeof slot, ":%02x.%x", 2745 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); 2746 assert(s == slot_len); 2747 memcpy(p, slot, slot_len); 2748 } 2749 2750 return path; 2751 } 2752 2753 static int pci_qdev_find_recursive(PCIBus *bus, 2754 const char *id, PCIDevice **pdev) 2755 { 2756 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); 2757 if (!qdev) { 2758 return -ENODEV; 2759 } 2760 2761 /* roughly check if given qdev is pci device */ 2762 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { 2763 *pdev = PCI_DEVICE(qdev); 2764 return 0; 2765 } 2766 return -EINVAL; 2767 } 2768 2769 int pci_qdev_find_device(const char *id, PCIDevice **pdev) 2770 { 2771 PCIHostState *host_bridge; 2772 int rc = -ENODEV; 2773 2774 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { 2775 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); 2776 if (!tmp) { 2777 rc = 0; 2778 break; 2779 } 2780 if (tmp != -ENODEV) { 2781 rc = tmp; 2782 } 2783 } 2784 2785 return rc; 2786 } 2787 2788 MemoryRegion *pci_address_space(PCIDevice *dev) 2789 { 2790 return pci_get_bus(dev)->address_space_mem; 2791 } 2792 2793 MemoryRegion *pci_address_space_io(PCIDevice *dev) 2794 { 2795 return pci_get_bus(dev)->address_space_io; 2796 } 2797 2798 static void pci_device_class_init(ObjectClass *klass, void *data) 2799 { 2800 DeviceClass *k = DEVICE_CLASS(klass); 2801 2802 k->realize = pci_qdev_realize; 2803 k->unrealize = pci_qdev_unrealize; 2804 k->bus_type = TYPE_PCI_BUS; 2805 device_class_set_props(k, pci_props); 2806 object_class_property_set_description( 2807 klass, "x-max-bounce-buffer-size", 2808 "Maximum buffer size allocated for bounce buffers used for mapped " 2809 "access to indirect DMA memory"); 2810 } 2811 2812 static void pci_device_class_base_init(ObjectClass *klass, void *data) 2813 { 2814 if (!object_class_is_abstract(klass)) { 2815 ObjectClass *conventional = 2816 object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); 2817 ObjectClass *pcie = 2818 object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); 2819 ObjectClass *cxl = 2820 object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE); 2821 assert(conventional || pcie || cxl); 2822 } 2823 } 2824 2825 /* 2826 * Get IOMMU root bus, aliased bus and devfn of a PCI device 2827 * 2828 * IOMMU root bus is needed by all call sites to call into iommu_ops. 2829 * For call sites which don't need aliased BDF, passing NULL to 2830 * aliased_[bus|devfn] is allowed. 2831 * 2832 * @piommu_bus: return root #PCIBus backed by an IOMMU for the PCI device. 2833 * 2834 * @aliased_bus: return aliased #PCIBus of the PCI device, optional. 2835 * 2836 * @aliased_devfn: return aliased devfn of the PCI device, optional. 2837 */ 2838 static void pci_device_get_iommu_bus_devfn(PCIDevice *dev, 2839 PCIBus **piommu_bus, 2840 PCIBus **aliased_bus, 2841 int *aliased_devfn) 2842 { 2843 PCIBus *bus = pci_get_bus(dev); 2844 PCIBus *iommu_bus = bus; 2845 int devfn = dev->devfn; 2846 2847 while (iommu_bus && !iommu_bus->iommu_ops && iommu_bus->parent_dev) { 2848 PCIBus *parent_bus = pci_get_bus(iommu_bus->parent_dev); 2849 2850 /* 2851 * The requester ID of the provided device may be aliased, as seen from 2852 * the IOMMU, due to topology limitations. The IOMMU relies on a 2853 * requester ID to provide a unique AddressSpace for devices, but 2854 * conventional PCI buses pre-date such concepts. Instead, the PCIe- 2855 * to-PCI bridge creates and accepts transactions on behalf of down- 2856 * stream devices. When doing so, all downstream devices are masked 2857 * (aliased) behind a single requester ID. The requester ID used 2858 * depends on the format of the bridge devices. Proper PCIe-to-PCI 2859 * bridges, with a PCIe capability indicating such, follow the 2860 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification, 2861 * where the bridge uses the seconary bus as the bridge portion of the 2862 * requester ID and devfn of 00.0. For other bridges, typically those 2863 * found on the root complex such as the dmi-to-pci-bridge, we follow 2864 * the convention of typical bare-metal hardware, which uses the 2865 * requester ID of the bridge itself. There are device specific 2866 * exceptions to these rules, but these are the defaults that the 2867 * Linux kernel uses when determining DMA aliases itself and believed 2868 * to be true for the bare metal equivalents of the devices emulated 2869 * in QEMU. 2870 */ 2871 if (!pci_bus_is_express(iommu_bus)) { 2872 PCIDevice *parent = iommu_bus->parent_dev; 2873 2874 if (pci_is_express(parent) && 2875 pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { 2876 devfn = PCI_DEVFN(0, 0); 2877 bus = iommu_bus; 2878 } else { 2879 devfn = parent->devfn; 2880 bus = parent_bus; 2881 } 2882 } 2883 2884 iommu_bus = parent_bus; 2885 } 2886 2887 assert(0 <= devfn && devfn < PCI_DEVFN_MAX); 2888 assert(iommu_bus); 2889 2890 if (pci_bus_bypass_iommu(bus) || !iommu_bus->iommu_ops) { 2891 iommu_bus = NULL; 2892 } 2893 2894 *piommu_bus = iommu_bus; 2895 2896 if (aliased_bus) { 2897 *aliased_bus = bus; 2898 } 2899 2900 if (aliased_devfn) { 2901 *aliased_devfn = devfn; 2902 } 2903 } 2904 2905 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) 2906 { 2907 PCIBus *bus; 2908 PCIBus *iommu_bus; 2909 int devfn; 2910 2911 pci_device_get_iommu_bus_devfn(dev, &iommu_bus, &bus, &devfn); 2912 if (iommu_bus) { 2913 return iommu_bus->iommu_ops->get_address_space(bus, 2914 iommu_bus->iommu_opaque, devfn); 2915 } 2916 return &address_space_memory; 2917 } 2918 2919 bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, 2920 Error **errp) 2921 { 2922 PCIBus *iommu_bus, *aliased_bus; 2923 int aliased_devfn; 2924 2925 /* set_iommu_device requires device's direct BDF instead of aliased BDF */ 2926 pci_device_get_iommu_bus_devfn(dev, &iommu_bus, 2927 &aliased_bus, &aliased_devfn); 2928 if (iommu_bus && iommu_bus->iommu_ops->set_iommu_device) { 2929 hiod->aliased_bus = aliased_bus; 2930 hiod->aliased_devfn = aliased_devfn; 2931 return iommu_bus->iommu_ops->set_iommu_device(pci_get_bus(dev), 2932 iommu_bus->iommu_opaque, 2933 dev->devfn, hiod, errp); 2934 } 2935 return true; 2936 } 2937 2938 void pci_device_unset_iommu_device(PCIDevice *dev) 2939 { 2940 PCIBus *iommu_bus; 2941 2942 pci_device_get_iommu_bus_devfn(dev, &iommu_bus, NULL, NULL); 2943 if (iommu_bus && iommu_bus->iommu_ops->unset_iommu_device) { 2944 return iommu_bus->iommu_ops->unset_iommu_device(pci_get_bus(dev), 2945 iommu_bus->iommu_opaque, 2946 dev->devfn); 2947 } 2948 } 2949 2950 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque) 2951 { 2952 /* 2953 * If called, pci_setup_iommu() should provide a minimum set of 2954 * useful callbacks for the bus. 2955 */ 2956 assert(ops); 2957 assert(ops->get_address_space); 2958 2959 bus->iommu_ops = ops; 2960 bus->iommu_opaque = opaque; 2961 } 2962 2963 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) 2964 { 2965 Range *range = opaque; 2966 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); 2967 int i; 2968 2969 if (!(cmd & PCI_COMMAND_MEMORY)) { 2970 return; 2971 } 2972 2973 if (IS_PCI_BRIDGE(dev)) { 2974 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2975 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); 2976 2977 base = MAX(base, 0x1ULL << 32); 2978 2979 if (limit >= base) { 2980 Range pref_range; 2981 range_set_bounds(&pref_range, base, limit); 2982 range_extend(range, &pref_range); 2983 } 2984 } 2985 for (i = 0; i < PCI_NUM_REGIONS; ++i) { 2986 PCIIORegion *r = &dev->io_regions[i]; 2987 pcibus_t lob, upb; 2988 Range region_range; 2989 2990 if (!r->size || 2991 (r->type & PCI_BASE_ADDRESS_SPACE_IO) || 2992 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { 2993 continue; 2994 } 2995 2996 lob = pci_bar_address(dev, i, r->type, r->size); 2997 upb = lob + r->size - 1; 2998 if (lob == PCI_BAR_UNMAPPED) { 2999 continue; 3000 } 3001 3002 lob = MAX(lob, 0x1ULL << 32); 3003 3004 if (upb >= lob) { 3005 range_set_bounds(®ion_range, lob, upb); 3006 range_extend(range, ®ion_range); 3007 } 3008 } 3009 } 3010 3011 void pci_bus_get_w64_range(PCIBus *bus, Range *range) 3012 { 3013 range_make_empty(range); 3014 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); 3015 } 3016 3017 static bool pcie_has_upstream_port(PCIDevice *dev) 3018 { 3019 PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); 3020 3021 /* Device associated with an upstream port. 3022 * As there are several types of these, it's easier to check the 3023 * parent device: upstream ports are always connected to 3024 * root or downstream ports. 3025 */ 3026 return parent_dev && 3027 pci_is_express(parent_dev) && 3028 parent_dev->exp.exp_cap && 3029 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || 3030 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); 3031 } 3032 3033 PCIDevice *pci_get_function_0(PCIDevice *pci_dev) 3034 { 3035 PCIBus *bus = pci_get_bus(pci_dev); 3036 3037 if(pcie_has_upstream_port(pci_dev)) { 3038 /* With an upstream PCIe port, we only support 1 device at slot 0 */ 3039 return bus->devices[0]; 3040 } else { 3041 /* Other bus types might support multiple devices at slots 0-31 */ 3042 return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; 3043 } 3044 } 3045 3046 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) 3047 { 3048 MSIMessage msg; 3049 if (msix_enabled(dev)) { 3050 msg = msix_get_message(dev, vector); 3051 } else if (msi_enabled(dev)) { 3052 msg = msi_get_message(dev, vector); 3053 } else { 3054 /* Should never happen */ 3055 error_report("%s: unknown interrupt type", __func__); 3056 abort(); 3057 } 3058 return msg; 3059 } 3060 3061 void pci_set_power(PCIDevice *d, bool state) 3062 { 3063 /* 3064 * Don't change the enabled state of VFs when powering on/off the device. 3065 * 3066 * When powering on, VFs must not be enabled immediately but they must 3067 * wait until the guest configures SR-IOV. 3068 * When powering off, their corresponding PFs will be reset and disable 3069 * VFs. 3070 */ 3071 if (!pci_is_vf(d)) { 3072 pci_set_enabled(d, state); 3073 } 3074 } 3075 3076 void pci_set_enabled(PCIDevice *d, bool state) 3077 { 3078 if (d->enabled == state) { 3079 return; 3080 } 3081 3082 d->enabled = state; 3083 pci_update_mappings(d); 3084 memory_region_set_enabled(&d->bus_master_enable_region, 3085 (pci_get_word(d->config + PCI_COMMAND) 3086 & PCI_COMMAND_MASTER) && d->enabled); 3087 if (qdev_is_realized(&d->qdev)) { 3088 pci_device_reset(d); 3089 } 3090 } 3091 3092 static const TypeInfo pci_device_type_info = { 3093 .name = TYPE_PCI_DEVICE, 3094 .parent = TYPE_DEVICE, 3095 .instance_size = sizeof(PCIDevice), 3096 .abstract = true, 3097 .class_size = sizeof(PCIDeviceClass), 3098 .class_init = pci_device_class_init, 3099 .class_base_init = pci_device_class_base_init, 3100 }; 3101 3102 static void pci_register_types(void) 3103 { 3104 type_register_static(&pci_bus_info); 3105 type_register_static(&pcie_bus_info); 3106 type_register_static(&cxl_bus_info); 3107 type_register_static(&conventional_pci_interface_info); 3108 type_register_static(&cxl_interface_info); 3109 type_register_static(&pcie_interface_info); 3110 type_register_static(&pci_device_type_info); 3111 } 3112 3113 type_init(pci_register_types) 3114