1 /* 2 * QEMU Uninorth PCI host (for all Mac99 and newer machines) 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/irq.h" 27 #include "hw/qdev-properties.h" 28 #include "qemu/module.h" 29 #include "hw/pci/pci_device.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/pci-host/uninorth.h" 32 #include "trace.h" 33 34 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) 35 { 36 return (irq_num + (pci_dev->devfn >> 3)) & 3; 37 } 38 39 static void pci_unin_set_irq(void *opaque, int irq_num, int level) 40 { 41 UNINHostState *s = opaque; 42 43 trace_unin_set_irq(irq_num, level); 44 qemu_set_irq(s->irqs[irq_num], level); 45 } 46 47 static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) 48 { 49 uint32_t retval; 50 51 if (reg & (1u << 31)) { 52 /* XXX OpenBIOS compatibility hack */ 53 retval = reg | (addr & 3); 54 } else if (reg & 1) { 55 /* CFA1 style */ 56 retval = (reg & ~7u) | (addr & 7); 57 } else { 58 uint32_t slot, func; 59 60 /* Grab CFA0 style values */ 61 slot = ctz32(reg & 0xfffff800); 62 if (slot == 32) { 63 slot = -1; /* XXX: should this be 0? */ 64 } 65 func = PCI_FUNC(reg >> 8); 66 67 /* ... and then convert them to x86 format */ 68 /* config pointer */ 69 retval = (reg & (0xff - 7)) | (addr & 7); 70 /* slot, fn */ 71 retval |= PCI_DEVFN(slot, func) << 8; 72 } 73 74 trace_unin_get_config_reg(reg, addr, retval); 75 76 return retval; 77 } 78 79 static void unin_data_write(void *opaque, hwaddr addr, 80 uint64_t val, unsigned len) 81 { 82 UNINHostState *s = opaque; 83 PCIHostState *phb = PCI_HOST_BRIDGE(s); 84 trace_unin_data_write(addr, len, val); 85 pci_data_write(phb->bus, 86 unin_get_config_reg(phb->config_reg, addr), 87 val, len); 88 } 89 90 static uint64_t unin_data_read(void *opaque, hwaddr addr, 91 unsigned len) 92 { 93 UNINHostState *s = opaque; 94 PCIHostState *phb = PCI_HOST_BRIDGE(s); 95 uint32_t val; 96 97 val = pci_data_read(phb->bus, 98 unin_get_config_reg(phb->config_reg, addr), 99 len); 100 trace_unin_data_read(addr, len, val); 101 return val; 102 } 103 104 static const MemoryRegionOps unin_data_ops = { 105 .read = unin_data_read, 106 .write = unin_data_write, 107 .endianness = DEVICE_LITTLE_ENDIAN, 108 }; 109 110 static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev) 111 { 112 UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); 113 114 return g_strdup_printf("%x", s->ofw_addr); 115 } 116 117 static void pci_unin_main_realize(DeviceState *dev, Error **errp) 118 { 119 UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); 120 PCIHostState *h = PCI_HOST_BRIDGE(dev); 121 122 h->bus = pci_register_root_bus(dev, NULL, 123 pci_unin_set_irq, pci_unin_map_irq, 124 s, 125 &s->pci_mmio, 126 &s->pci_io, 127 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); 128 129 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); 130 131 /* 132 * DEC 21154 bridge was unused for many years, this comment is 133 * a placeholder for whoever wishes to resurrect it 134 */ 135 } 136 137 static void pci_unin_main_init(Object *obj) 138 { 139 UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj); 140 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 141 PCIHostState *h = PCI_HOST_BRIDGE(obj); 142 143 /* Use values found on a real PowerMac */ 144 /* Uninorth main bus */ 145 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, 146 obj, "unin-pci-conf-idx", 0x1000); 147 memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, 148 "unin-pci-conf-data", 0x1000); 149 150 memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", 151 0x100000000ULL); 152 memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, 153 "unin-pci-isa-mmio", 0x00800000); 154 155 memory_region_init_alias(&s->pci_hole, OBJECT(s), 156 "unin-pci-hole", &s->pci_mmio, 157 0x80000000ULL, 0x10000000ULL); 158 159 sysbus_init_mmio(sbd, &h->conf_mem); 160 sysbus_init_mmio(sbd, &h->data_mem); 161 sysbus_init_mmio(sbd, &s->pci_hole); 162 sysbus_init_mmio(sbd, &s->pci_io); 163 164 qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs)); 165 } 166 167 static void pci_u3_agp_realize(DeviceState *dev, Error **errp) 168 { 169 UNINHostState *s = U3_AGP_HOST_BRIDGE(dev); 170 PCIHostState *h = PCI_HOST_BRIDGE(dev); 171 172 h->bus = pci_register_root_bus(dev, NULL, 173 pci_unin_set_irq, pci_unin_map_irq, 174 s, 175 &s->pci_mmio, 176 &s->pci_io, 177 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); 178 179 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp"); 180 } 181 182 static void pci_u3_agp_init(Object *obj) 183 { 184 UNINHostState *s = U3_AGP_HOST_BRIDGE(obj); 185 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 186 PCIHostState *h = PCI_HOST_BRIDGE(obj); 187 188 /* Uninorth U3 AGP bus */ 189 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, 190 obj, "unin-pci-conf-idx", 0x1000); 191 memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj, 192 "unin-pci-conf-data", 0x1000); 193 194 memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", 195 0x100000000ULL); 196 memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, 197 "unin-pci-isa-mmio", 0x00800000); 198 199 memory_region_init_alias(&s->pci_hole, OBJECT(s), 200 "unin-pci-hole", &s->pci_mmio, 201 0x80000000ULL, 0x70000000ULL); 202 203 sysbus_init_mmio(sbd, &h->conf_mem); 204 sysbus_init_mmio(sbd, &h->data_mem); 205 sysbus_init_mmio(sbd, &s->pci_hole); 206 sysbus_init_mmio(sbd, &s->pci_io); 207 208 qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs)); 209 } 210 211 static void pci_unin_agp_realize(DeviceState *dev, Error **errp) 212 { 213 UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev); 214 PCIHostState *h = PCI_HOST_BRIDGE(dev); 215 216 h->bus = pci_register_root_bus(dev, NULL, 217 pci_unin_set_irq, pci_unin_map_irq, 218 s, 219 &s->pci_mmio, 220 &s->pci_io, 221 PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); 222 223 pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); 224 } 225 226 static void pci_unin_agp_init(Object *obj) 227 { 228 UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj); 229 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 230 PCIHostState *h = PCI_HOST_BRIDGE(obj); 231 232 /* Uninorth AGP bus */ 233 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, 234 obj, "unin-agp-conf-idx", 0x1000); 235 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, 236 obj, "unin-agp-conf-data", 0x1000); 237 238 sysbus_init_mmio(sbd, &h->conf_mem); 239 sysbus_init_mmio(sbd, &h->data_mem); 240 241 qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs)); 242 } 243 244 static void pci_unin_internal_realize(DeviceState *dev, Error **errp) 245 { 246 UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev); 247 PCIHostState *h = PCI_HOST_BRIDGE(dev); 248 249 h->bus = pci_register_root_bus(dev, NULL, 250 pci_unin_set_irq, pci_unin_map_irq, 251 s, 252 &s->pci_mmio, 253 &s->pci_io, 254 PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS); 255 256 pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci"); 257 } 258 259 static void pci_unin_internal_init(Object *obj) 260 { 261 UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj); 262 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 263 PCIHostState *h = PCI_HOST_BRIDGE(obj); 264 265 /* Uninorth internal bus */ 266 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, 267 obj, "unin-pci-conf-idx", 0x1000); 268 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, 269 obj, "unin-pci-conf-data", 0x1000); 270 271 sysbus_init_mmio(sbd, &h->conf_mem); 272 sysbus_init_mmio(sbd, &h->data_mem); 273 274 qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs)); 275 } 276 277 static void unin_main_pci_host_realize(PCIDevice *d, Error **errp) 278 { 279 d->config[PCI_CACHE_LINE_SIZE] = 0x08; 280 d->config[PCI_LATENCY_TIMER] = 0x10; 281 d->config[PCI_CAPABILITY_LIST] = 0x00; 282 283 /* 284 * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI 285 * memory space with base 0x80000000, size 0x10000000 for Apple's 286 * AppleMacRiscPCI driver 287 */ 288 d->config[0x48] = 0x0; 289 d->config[0x49] = 0x0; 290 d->config[0x4a] = 0x0; 291 d->config[0x4b] = 0x1; 292 } 293 294 static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp) 295 { 296 d->config[PCI_CACHE_LINE_SIZE] = 0x08; 297 d->config[PCI_LATENCY_TIMER] = 0x10; 298 /* d->config[PCI_CAPABILITY_LIST] = 0x80; */ 299 } 300 301 static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp) 302 { 303 d->config[PCI_CACHE_LINE_SIZE] = 0x08; 304 d->config[PCI_LATENCY_TIMER] = 0x10; 305 } 306 307 static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp) 308 { 309 d->config[PCI_CACHE_LINE_SIZE] = 0x08; 310 d->config[PCI_LATENCY_TIMER] = 0x10; 311 d->config[PCI_CAPABILITY_LIST] = 0x00; 312 } 313 314 static void unin_main_pci_host_class_init(ObjectClass *klass, void *data) 315 { 316 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 317 DeviceClass *dc = DEVICE_CLASS(klass); 318 319 k->realize = unin_main_pci_host_realize; 320 k->vendor_id = PCI_VENDOR_ID_APPLE; 321 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI; 322 k->revision = 0x00; 323 k->class_id = PCI_CLASS_BRIDGE_HOST; 324 /* 325 * PCI-facing part of the host bridge, not usable without the 326 * host-facing part, which can't be device_add'ed, yet. 327 */ 328 dc->user_creatable = false; 329 } 330 331 static const TypeInfo unin_main_pci_host_info = { 332 .name = "uni-north-pci", 333 .parent = TYPE_PCI_DEVICE, 334 .instance_size = sizeof(PCIDevice), 335 .class_init = unin_main_pci_host_class_init, 336 .interfaces = (InterfaceInfo[]) { 337 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 338 { }, 339 }, 340 }; 341 342 static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data) 343 { 344 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 345 DeviceClass *dc = DEVICE_CLASS(klass); 346 347 k->realize = u3_agp_pci_host_realize; 348 k->vendor_id = PCI_VENDOR_ID_APPLE; 349 k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP; 350 k->revision = 0x00; 351 k->class_id = PCI_CLASS_BRIDGE_HOST; 352 /* 353 * PCI-facing part of the host bridge, not usable without the 354 * host-facing part, which can't be device_add'ed, yet. 355 */ 356 dc->user_creatable = false; 357 } 358 359 static const TypeInfo u3_agp_pci_host_info = { 360 .name = "u3-agp", 361 .parent = TYPE_PCI_DEVICE, 362 .instance_size = sizeof(PCIDevice), 363 .class_init = u3_agp_pci_host_class_init, 364 .interfaces = (InterfaceInfo[]) { 365 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 366 { }, 367 }, 368 }; 369 370 static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data) 371 { 372 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 373 DeviceClass *dc = DEVICE_CLASS(klass); 374 375 k->realize = unin_agp_pci_host_realize; 376 k->vendor_id = PCI_VENDOR_ID_APPLE; 377 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP; 378 k->revision = 0x00; 379 k->class_id = PCI_CLASS_BRIDGE_HOST; 380 /* 381 * PCI-facing part of the host bridge, not usable without the 382 * host-facing part, which can't be device_add'ed, yet. 383 */ 384 dc->user_creatable = false; 385 } 386 387 static const TypeInfo unin_agp_pci_host_info = { 388 .name = "uni-north-agp", 389 .parent = TYPE_PCI_DEVICE, 390 .instance_size = sizeof(PCIDevice), 391 .class_init = unin_agp_pci_host_class_init, 392 .interfaces = (InterfaceInfo[]) { 393 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 394 { }, 395 }, 396 }; 397 398 static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data) 399 { 400 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 401 DeviceClass *dc = DEVICE_CLASS(klass); 402 403 k->realize = unin_internal_pci_host_realize; 404 k->vendor_id = PCI_VENDOR_ID_APPLE; 405 k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI; 406 k->revision = 0x00; 407 k->class_id = PCI_CLASS_BRIDGE_HOST; 408 /* 409 * PCI-facing part of the host bridge, not usable without the 410 * host-facing part, which can't be device_add'ed, yet. 411 */ 412 dc->user_creatable = false; 413 } 414 415 static const TypeInfo unin_internal_pci_host_info = { 416 .name = "uni-north-internal-pci", 417 .parent = TYPE_PCI_DEVICE, 418 .instance_size = sizeof(PCIDevice), 419 .class_init = unin_internal_pci_host_class_init, 420 .interfaces = (InterfaceInfo[]) { 421 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 422 { }, 423 }, 424 }; 425 426 static const Property pci_unin_main_pci_host_props[] = { 427 DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1), 428 }; 429 430 static void pci_unin_main_class_init(ObjectClass *klass, void *data) 431 { 432 DeviceClass *dc = DEVICE_CLASS(klass); 433 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 434 435 dc->realize = pci_unin_main_realize; 436 device_class_set_props(dc, pci_unin_main_pci_host_props); 437 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 438 dc->fw_name = "pci"; 439 sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address; 440 } 441 442 static const TypeInfo pci_unin_main_info = { 443 .name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE, 444 .parent = TYPE_PCI_HOST_BRIDGE, 445 .instance_size = sizeof(UNINHostState), 446 .instance_init = pci_unin_main_init, 447 .class_init = pci_unin_main_class_init, 448 }; 449 450 static void pci_u3_agp_class_init(ObjectClass *klass, void *data) 451 { 452 DeviceClass *dc = DEVICE_CLASS(klass); 453 454 dc->realize = pci_u3_agp_realize; 455 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 456 } 457 458 static const TypeInfo pci_u3_agp_info = { 459 .name = TYPE_U3_AGP_HOST_BRIDGE, 460 .parent = TYPE_PCI_HOST_BRIDGE, 461 .instance_size = sizeof(UNINHostState), 462 .instance_init = pci_u3_agp_init, 463 .class_init = pci_u3_agp_class_init, 464 }; 465 466 static void pci_unin_agp_class_init(ObjectClass *klass, void *data) 467 { 468 DeviceClass *dc = DEVICE_CLASS(klass); 469 470 dc->realize = pci_unin_agp_realize; 471 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 472 } 473 474 static const TypeInfo pci_unin_agp_info = { 475 .name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE, 476 .parent = TYPE_PCI_HOST_BRIDGE, 477 .instance_size = sizeof(UNINHostState), 478 .instance_init = pci_unin_agp_init, 479 .class_init = pci_unin_agp_class_init, 480 }; 481 482 static void pci_unin_internal_class_init(ObjectClass *klass, void *data) 483 { 484 DeviceClass *dc = DEVICE_CLASS(klass); 485 486 dc->realize = pci_unin_internal_realize; 487 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 488 } 489 490 static const TypeInfo pci_unin_internal_info = { 491 .name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE, 492 .parent = TYPE_PCI_HOST_BRIDGE, 493 .instance_size = sizeof(UNINHostState), 494 .instance_init = pci_unin_internal_init, 495 .class_init = pci_unin_internal_class_init, 496 }; 497 498 /* UniN device */ 499 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 500 unsigned size) 501 { 502 trace_unin_write(addr, value); 503 } 504 505 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 506 { 507 uint32_t value; 508 509 switch (addr) { 510 case 0: 511 value = UNINORTH_VERSION_10A; 512 break; 513 default: 514 value = 0; 515 } 516 517 trace_unin_read(addr, value); 518 519 return value; 520 } 521 522 static const MemoryRegionOps unin_ops = { 523 .read = unin_read, 524 .write = unin_write, 525 .endianness = DEVICE_BIG_ENDIAN, 526 }; 527 528 static void unin_init(Object *obj) 529 { 530 UNINState *s = UNI_NORTH(obj); 531 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 532 533 memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000); 534 535 sysbus_init_mmio(sbd, &s->mem); 536 } 537 538 static void unin_class_init(ObjectClass *klass, void *data) 539 { 540 DeviceClass *dc = DEVICE_CLASS(klass); 541 542 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 543 } 544 545 static const TypeInfo unin_info = { 546 .name = TYPE_UNI_NORTH, 547 .parent = TYPE_SYS_BUS_DEVICE, 548 .instance_size = sizeof(UNINState), 549 .instance_init = unin_init, 550 .class_init = unin_class_init, 551 }; 552 553 static void unin_register_types(void) 554 { 555 type_register_static(&unin_main_pci_host_info); 556 type_register_static(&u3_agp_pci_host_info); 557 type_register_static(&unin_agp_pci_host_info); 558 type_register_static(&unin_internal_pci_host_info); 559 560 type_register_static(&pci_unin_main_info); 561 type_register_static(&pci_u3_agp_info); 562 type_register_static(&pci_unin_agp_info); 563 type_register_static(&pci_unin_internal_info); 564 565 type_register_static(&unin_info); 566 } 567 568 type_init(unin_register_types) 569