1 /* 2 * SuperH on-chip PCIC emulation. 3 * 4 * Copyright (c) 2008 Takashi YOSHII 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/sysbus.h" 26 #include "hw/sh4/sh.h" 27 #include "hw/pci/pci.h" 28 #include "hw/pci/pci_host.h" 29 #include "qemu/bswap.h" 30 #include "exec/address-spaces.h" 31 32 #define TYPE_SH_PCI_HOST_BRIDGE "sh_pci" 33 34 #define SH_PCI_HOST_BRIDGE(obj) \ 35 OBJECT_CHECK(SHPCIState, (obj), TYPE_SH_PCI_HOST_BRIDGE) 36 37 typedef struct SHPCIState { 38 PCIHostState parent_obj; 39 40 PCIDevice *dev; 41 qemu_irq irq[4]; 42 MemoryRegion memconfig_p4; 43 MemoryRegion memconfig_a7; 44 MemoryRegion isa; 45 uint32_t par; 46 uint32_t mbr; 47 uint32_t iobr; 48 } SHPCIState; 49 50 static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val, 51 unsigned size) 52 { 53 SHPCIState *pcic = p; 54 PCIHostState *phb = PCI_HOST_BRIDGE(pcic); 55 56 switch(addr) { 57 case 0 ... 0xfc: 58 stl_le_p(pcic->dev->config + addr, val); 59 break; 60 case 0x1c0: 61 pcic->par = val; 62 break; 63 case 0x1c4: 64 pcic->mbr = val & 0xff000001; 65 break; 66 case 0x1c8: 67 if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { 68 memory_region_del_subregion(get_system_memory(), &pcic->isa); 69 pcic->iobr = val & 0xfffc0001; 70 memory_region_add_subregion(get_system_memory(), 71 pcic->iobr & 0xfffc0000, &pcic->isa); 72 } 73 break; 74 case 0x220: 75 pci_data_write(phb->bus, pcic->par, val, 4); 76 break; 77 } 78 } 79 80 static uint64_t sh_pci_reg_read (void *p, hwaddr addr, 81 unsigned size) 82 { 83 SHPCIState *pcic = p; 84 PCIHostState *phb = PCI_HOST_BRIDGE(pcic); 85 86 switch(addr) { 87 case 0 ... 0xfc: 88 return ldl_le_p(pcic->dev->config + addr); 89 case 0x1c0: 90 return pcic->par; 91 case 0x1c4: 92 return pcic->mbr; 93 case 0x1c8: 94 return pcic->iobr; 95 case 0x220: 96 return pci_data_read(phb->bus, pcic->par, 4); 97 } 98 return 0; 99 } 100 101 static const MemoryRegionOps sh_pci_reg_ops = { 102 .read = sh_pci_reg_read, 103 .write = sh_pci_reg_write, 104 .endianness = DEVICE_NATIVE_ENDIAN, 105 .valid = { 106 .min_access_size = 4, 107 .max_access_size = 4, 108 }, 109 }; 110 111 static int sh_pci_map_irq(PCIDevice *d, int irq_num) 112 { 113 return (d->devfn >> 3); 114 } 115 116 static void sh_pci_set_irq(void *opaque, int irq_num, int level) 117 { 118 qemu_irq *pic = opaque; 119 120 qemu_set_irq(pic[irq_num], level); 121 } 122 123 static int sh_pci_device_init(SysBusDevice *dev) 124 { 125 PCIHostState *phb; 126 SHPCIState *s; 127 int i; 128 129 s = SH_PCI_HOST_BRIDGE(dev); 130 phb = PCI_HOST_BRIDGE(s); 131 for (i = 0; i < 4; i++) { 132 sysbus_init_irq(dev, &s->irq[i]); 133 } 134 phb->bus = pci_register_bus(DEVICE(dev), "pci", 135 sh_pci_set_irq, sh_pci_map_irq, 136 s->irq, 137 get_system_memory(), 138 get_system_io(), 139 PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS); 140 memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s, 141 "sh_pci", 0x224); 142 memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2", 143 &s->memconfig_p4, 0, 0x224); 144 memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa", 145 get_system_io(), 0, 0x40000); 146 sysbus_init_mmio(dev, &s->memconfig_p4); 147 sysbus_init_mmio(dev, &s->memconfig_a7); 148 s->iobr = 0xfe240000; 149 memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa); 150 151 s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host"); 152 return 0; 153 } 154 155 static void sh_pci_host_realize(PCIDevice *d, Error **errp) 156 { 157 pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT); 158 pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST | 159 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 160 } 161 162 static void sh_pci_host_class_init(ObjectClass *klass, void *data) 163 { 164 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 165 DeviceClass *dc = DEVICE_CLASS(klass); 166 167 k->realize = sh_pci_host_realize; 168 k->vendor_id = PCI_VENDOR_ID_HITACHI; 169 k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R; 170 /* 171 * PCI-facing part of the host bridge, not usable without the 172 * host-facing part, which can't be device_add'ed, yet. 173 */ 174 dc->user_creatable = false; 175 } 176 177 static const TypeInfo sh_pci_host_info = { 178 .name = "sh_pci_host", 179 .parent = TYPE_PCI_DEVICE, 180 .instance_size = sizeof(PCIDevice), 181 .class_init = sh_pci_host_class_init, 182 }; 183 184 static void sh_pci_device_class_init(ObjectClass *klass, void *data) 185 { 186 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 187 188 sdc->init = sh_pci_device_init; 189 } 190 191 static const TypeInfo sh_pci_device_info = { 192 .name = TYPE_SH_PCI_HOST_BRIDGE, 193 .parent = TYPE_PCI_HOST_BRIDGE, 194 .instance_size = sizeof(SHPCIState), 195 .class_init = sh_pci_device_class_init, 196 }; 197 198 static void sh_pci_register_types(void) 199 { 200 type_register_static(&sh_pci_device_info); 201 type_register_static(&sh_pci_host_info); 202 } 203 204 type_init(sh_pci_register_types) 205