1 /* 2 * SuperH on-chip PCIC emulation. 3 * 4 * Copyright (c) 2008 Takashi YOSHII 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "sysbus.h" 25 #include "sh.h" 26 #include "pci.h" 27 #include "pci_host.h" 28 #include "bswap.h" 29 #include "exec-memory.h" 30 31 typedef struct SHPCIState { 32 SysBusDevice busdev; 33 PCIBus *bus; 34 PCIDevice *dev; 35 qemu_irq irq[4]; 36 int memconfig; 37 uint32_t par; 38 uint32_t mbr; 39 uint32_t iobr; 40 } SHPCIState; 41 42 static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) 43 { 44 SHPCIState *pcic = p; 45 switch(addr) { 46 case 0 ... 0xfc: 47 cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); 48 break; 49 case 0x1c0: 50 pcic->par = val; 51 break; 52 case 0x1c4: 53 pcic->mbr = val & 0xff000001; 54 break; 55 case 0x1c8: 56 if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { 57 cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000, 58 IO_MEM_UNASSIGNED); 59 pcic->iobr = val & 0xfffc0001; 60 isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000); 61 } 62 break; 63 case 0x220: 64 pci_data_write(pcic->bus, pcic->par, val, 4); 65 break; 66 } 67 } 68 69 static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr) 70 { 71 SHPCIState *pcic = p; 72 switch(addr) { 73 case 0 ... 0xfc: 74 return le32_to_cpup((uint32_t*)(pcic->dev->config + addr)); 75 case 0x1c0: 76 return pcic->par; 77 case 0x1c4: 78 return pcic->mbr; 79 case 0x1c8: 80 return pcic->iobr; 81 case 0x220: 82 return pci_data_read(pcic->bus, pcic->par, 4); 83 } 84 return 0; 85 } 86 87 typedef struct { 88 CPUReadMemoryFunc * const r[3]; 89 CPUWriteMemoryFunc * const w[3]; 90 } MemOp; 91 92 static MemOp sh_pci_reg = { 93 { NULL, NULL, sh_pci_reg_read }, 94 { NULL, NULL, sh_pci_reg_write }, 95 }; 96 97 static int sh_pci_map_irq(PCIDevice *d, int irq_num) 98 { 99 return (d->devfn >> 3); 100 } 101 102 static void sh_pci_set_irq(void *opaque, int irq_num, int level) 103 { 104 qemu_irq *pic = opaque; 105 106 qemu_set_irq(pic[irq_num], level); 107 } 108 109 static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base) 110 { 111 SHPCIState *s = FROM_SYSBUS(SHPCIState, dev); 112 113 cpu_register_physical_memory(P4ADDR(base), 0x224, s->memconfig); 114 cpu_register_physical_memory(A7ADDR(base), 0x224, s->memconfig); 115 116 s->iobr = 0xfe240000; 117 isa_mmio_init(s->iobr, 0x40000); 118 } 119 120 static int sh_pci_init_device(SysBusDevice *dev) 121 { 122 SHPCIState *s; 123 int i; 124 125 s = FROM_SYSBUS(SHPCIState, dev); 126 for (i = 0; i < 4; i++) { 127 sysbus_init_irq(dev, &s->irq[i]); 128 } 129 s->bus = pci_register_bus(&s->busdev.qdev, "pci", 130 sh_pci_set_irq, sh_pci_map_irq, 131 s->irq, 132 get_system_memory(), 133 get_system_io(), 134 PCI_DEVFN(0, 0), 4); 135 s->memconfig = cpu_register_io_memory(sh_pci_reg.r, sh_pci_reg.w, 136 s, DEVICE_NATIVE_ENDIAN); 137 sysbus_init_mmio_cb(dev, 0x224, sh_pci_map); 138 s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host"); 139 return 0; 140 } 141 142 static int sh_pci_host_init(PCIDevice *d) 143 { 144 pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT); 145 pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST | 146 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 147 return 0; 148 } 149 150 static PCIDeviceInfo sh_pci_host_info = { 151 .qdev.name = "sh_pci_host", 152 .qdev.size = sizeof(PCIDevice), 153 .init = sh_pci_host_init, 154 .vendor_id = PCI_VENDOR_ID_HITACHI, 155 .device_id = PCI_DEVICE_ID_HITACHI_SH7751R, 156 }; 157 158 static void sh_pci_register_devices(void) 159 { 160 sysbus_register_dev("sh_pci", sizeof(SHPCIState), 161 sh_pci_init_device); 162 pci_qdev_register(&sh_pci_host_info); 163 } 164 165 device_init(sh_pci_register_devices) 166