1 /* 2 * SuperH on-chip PCIC emulation. 3 * 4 * Copyright (c) 2008 Takashi YOSHII 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "sysbus.h" 25 #include "sh.h" 26 #include "pci.h" 27 #include "pci_host.h" 28 #include "bswap.h" 29 #include "exec-memory.h" 30 31 typedef struct SHPCIState { 32 SysBusDevice busdev; 33 PCIBus *bus; 34 PCIDevice *dev; 35 qemu_irq irq[4]; 36 MemoryRegion memconfig_p4; 37 MemoryRegion memconfig_a7; 38 MemoryRegion isa; 39 uint32_t par; 40 uint32_t mbr; 41 uint32_t iobr; 42 } SHPCIState; 43 44 static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val, 45 unsigned size) 46 { 47 SHPCIState *pcic = p; 48 switch(addr) { 49 case 0 ... 0xfc: 50 cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); 51 break; 52 case 0x1c0: 53 pcic->par = val; 54 break; 55 case 0x1c4: 56 pcic->mbr = val & 0xff000001; 57 break; 58 case 0x1c8: 59 if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { 60 memory_region_del_subregion(get_system_memory(), &pcic->isa); 61 pcic->iobr = val & 0xfffc0001; 62 memory_region_add_subregion(get_system_memory(), 63 pcic->iobr & 0xfffc0000, &pcic->isa); 64 } 65 break; 66 case 0x220: 67 pci_data_write(pcic->bus, pcic->par, val, 4); 68 break; 69 } 70 } 71 72 static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr, 73 unsigned size) 74 { 75 SHPCIState *pcic = p; 76 switch(addr) { 77 case 0 ... 0xfc: 78 return le32_to_cpup((uint32_t*)(pcic->dev->config + addr)); 79 case 0x1c0: 80 return pcic->par; 81 case 0x1c4: 82 return pcic->mbr; 83 case 0x1c8: 84 return pcic->iobr; 85 case 0x220: 86 return pci_data_read(pcic->bus, pcic->par, 4); 87 } 88 return 0; 89 } 90 91 static const MemoryRegionOps sh_pci_reg_ops = { 92 .read = sh_pci_reg_read, 93 .write = sh_pci_reg_write, 94 .endianness = DEVICE_NATIVE_ENDIAN, 95 .valid = { 96 .min_access_size = 4, 97 .max_access_size = 4, 98 }, 99 }; 100 101 static int sh_pci_map_irq(PCIDevice *d, int irq_num) 102 { 103 return (d->devfn >> 3); 104 } 105 106 static void sh_pci_set_irq(void *opaque, int irq_num, int level) 107 { 108 qemu_irq *pic = opaque; 109 110 qemu_set_irq(pic[irq_num], level); 111 } 112 113 static void sh_pci_map(SysBusDevice *dev, target_phys_addr_t base) 114 { 115 SHPCIState *s = FROM_SYSBUS(SHPCIState, dev); 116 117 memory_region_add_subregion(get_system_memory(), 118 P4ADDR(base), 119 &s->memconfig_p4); 120 memory_region_add_subregion(get_system_memory(), 121 A7ADDR(base), 122 &s->memconfig_a7); 123 s->iobr = 0xfe240000; 124 memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa); 125 } 126 127 static void sh_pci_unmap(SysBusDevice *dev, target_phys_addr_t base) 128 { 129 SHPCIState *s = FROM_SYSBUS(SHPCIState, dev); 130 131 memory_region_del_subregion(get_system_memory(), &s->memconfig_p4); 132 memory_region_del_subregion(get_system_memory(), &s->memconfig_a7); 133 memory_region_del_subregion(get_system_memory(), &s->isa); 134 } 135 136 static int sh_pci_init_device(SysBusDevice *dev) 137 { 138 SHPCIState *s; 139 int i; 140 141 s = FROM_SYSBUS(SHPCIState, dev); 142 for (i = 0; i < 4; i++) { 143 sysbus_init_irq(dev, &s->irq[i]); 144 } 145 s->bus = pci_register_bus(&s->busdev.qdev, "pci", 146 sh_pci_set_irq, sh_pci_map_irq, 147 s->irq, 148 get_system_memory(), 149 get_system_io(), 150 PCI_DEVFN(0, 0), 4); 151 memory_region_init_io(&s->memconfig_p4, &sh_pci_reg_ops, s, 152 "sh_pci", 0x224); 153 memory_region_init_alias(&s->memconfig_a7, "sh_pci.2", &s->memconfig_p4, 154 0, 0x224); 155 isa_mmio_setup(&s->isa, 0x40000); 156 sysbus_init_mmio_cb2(dev, sh_pci_map, sh_pci_unmap); 157 sysbus_init_mmio_region(dev, &s->memconfig_a7); 158 sysbus_init_mmio_region(dev, &s->isa); 159 s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host"); 160 return 0; 161 } 162 163 static int sh_pci_host_init(PCIDevice *d) 164 { 165 pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT); 166 pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST | 167 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM); 168 return 0; 169 } 170 171 static PCIDeviceInfo sh_pci_host_info = { 172 .qdev.name = "sh_pci_host", 173 .qdev.size = sizeof(PCIDevice), 174 .init = sh_pci_host_init, 175 .vendor_id = PCI_VENDOR_ID_HITACHI, 176 .device_id = PCI_DEVICE_ID_HITACHI_SH7751R, 177 }; 178 179 static void sh_pci_register_devices(void) 180 { 181 sysbus_register_dev("sh_pci", sizeof(SHPCIState), 182 sh_pci_init_device); 183 pci_qdev_register(&sh_pci_host_info); 184 } 185 186 device_init(sh_pci_register_devices) 187