1 /* 2 * QEMU PREP PCI host 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2011-2013 Andreas Färber 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu-common.h" 28 #include "qemu/units.h" 29 #include "qapi/error.h" 30 #include "hw/pci/pci.h" 31 #include "hw/pci/pci_bus.h" 32 #include "hw/pci/pci_host.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "hw/intc/i8259.h" 36 #include "hw/irq.h" 37 #include "hw/loader.h" 38 #include "hw/or-irq.h" 39 #include "exec/address-spaces.h" 40 #include "elf.h" 41 #include "qom/object.h" 42 43 #define TYPE_RAVEN_PCI_DEVICE "raven" 44 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" 45 46 typedef struct RavenPCIState RavenPCIState; 47 #define RAVEN_PCI_DEVICE(obj) \ 48 OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE) 49 50 struct RavenPCIState { 51 PCIDevice dev; 52 53 uint32_t elf_machine; 54 char *bios_name; 55 MemoryRegion bios; 56 }; 57 58 typedef struct PRePPCIState PREPPCIState; 59 #define RAVEN_PCI_HOST_BRIDGE(obj) \ 60 OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE) 61 62 struct PRePPCIState { 63 PCIHostState parent_obj; 64 65 qemu_or_irq *or_irq; 66 qemu_irq pci_irqs[PCI_NUM_PINS]; 67 PCIBus pci_bus; 68 AddressSpace pci_io_as; 69 MemoryRegion pci_io; 70 MemoryRegion pci_io_non_contiguous; 71 MemoryRegion pci_memory; 72 MemoryRegion pci_intack; 73 MemoryRegion bm; 74 MemoryRegion bm_ram_alias; 75 MemoryRegion bm_pci_memory_alias; 76 AddressSpace bm_as; 77 RavenPCIState pci_dev; 78 79 int contiguous_map; 80 bool is_legacy_prep; 81 }; 82 83 #define BIOS_SIZE (1 * MiB) 84 85 static inline uint32_t raven_pci_io_config(hwaddr addr) 86 { 87 int i; 88 89 for (i = 0; i < 11; i++) { 90 if ((addr & (1 << (11 + i))) != 0) { 91 break; 92 } 93 } 94 return (addr & 0x7ff) | (i << 11); 95 } 96 97 static void raven_pci_io_write(void *opaque, hwaddr addr, 98 uint64_t val, unsigned int size) 99 { 100 PREPPCIState *s = opaque; 101 PCIHostState *phb = PCI_HOST_BRIDGE(s); 102 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size); 103 } 104 105 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr, 106 unsigned int size) 107 { 108 PREPPCIState *s = opaque; 109 PCIHostState *phb = PCI_HOST_BRIDGE(s); 110 return pci_data_read(phb->bus, raven_pci_io_config(addr), size); 111 } 112 113 static const MemoryRegionOps raven_pci_io_ops = { 114 .read = raven_pci_io_read, 115 .write = raven_pci_io_write, 116 .endianness = DEVICE_LITTLE_ENDIAN, 117 }; 118 119 static uint64_t raven_intack_read(void *opaque, hwaddr addr, 120 unsigned int size) 121 { 122 return pic_read_irq(isa_pic); 123 } 124 125 static const MemoryRegionOps raven_intack_ops = { 126 .read = raven_intack_read, 127 .valid = { 128 .max_access_size = 1, 129 }, 130 }; 131 132 static inline hwaddr raven_io_address(PREPPCIState *s, 133 hwaddr addr) 134 { 135 if (s->contiguous_map == 0) { 136 /* 64 KB contiguous space for IOs */ 137 addr &= 0xFFFF; 138 } else { 139 /* 8 MB non-contiguous space for IOs */ 140 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); 141 } 142 143 /* FIXME: handle endianness switch */ 144 145 return addr; 146 } 147 148 static uint64_t raven_io_read(void *opaque, hwaddr addr, 149 unsigned int size) 150 { 151 PREPPCIState *s = opaque; 152 uint8_t buf[4]; 153 154 addr = raven_io_address(s, addr); 155 address_space_read(&s->pci_io_as, addr + 0x80000000, 156 MEMTXATTRS_UNSPECIFIED, buf, size); 157 158 if (size == 1) { 159 return buf[0]; 160 } else if (size == 2) { 161 return lduw_le_p(buf); 162 } else if (size == 4) { 163 return ldl_le_p(buf); 164 } else { 165 g_assert_not_reached(); 166 } 167 } 168 169 static void raven_io_write(void *opaque, hwaddr addr, 170 uint64_t val, unsigned int size) 171 { 172 PREPPCIState *s = opaque; 173 uint8_t buf[4]; 174 175 addr = raven_io_address(s, addr); 176 177 if (size == 1) { 178 buf[0] = val; 179 } else if (size == 2) { 180 stw_le_p(buf, val); 181 } else if (size == 4) { 182 stl_le_p(buf, val); 183 } else { 184 g_assert_not_reached(); 185 } 186 187 address_space_write(&s->pci_io_as, addr + 0x80000000, 188 MEMTXATTRS_UNSPECIFIED, buf, size); 189 } 190 191 static const MemoryRegionOps raven_io_ops = { 192 .read = raven_io_read, 193 .write = raven_io_write, 194 .endianness = DEVICE_LITTLE_ENDIAN, 195 .impl.max_access_size = 4, 196 .valid.unaligned = true, 197 }; 198 199 static int raven_map_irq(PCIDevice *pci_dev, int irq_num) 200 { 201 return (irq_num + (pci_dev->devfn >> 3)) & 1; 202 } 203 204 static void raven_set_irq(void *opaque, int irq_num, int level) 205 { 206 PREPPCIState *s = opaque; 207 208 qemu_set_irq(s->pci_irqs[irq_num], level); 209 } 210 211 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque, 212 int devfn) 213 { 214 PREPPCIState *s = opaque; 215 216 return &s->bm_as; 217 } 218 219 static void raven_change_gpio(void *opaque, int n, int level) 220 { 221 PREPPCIState *s = opaque; 222 223 s->contiguous_map = level; 224 } 225 226 static void raven_pcihost_realizefn(DeviceState *d, Error **errp) 227 { 228 SysBusDevice *dev = SYS_BUS_DEVICE(d); 229 PCIHostState *h = PCI_HOST_BRIDGE(dev); 230 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); 231 MemoryRegion *address_space_mem = get_system_memory(); 232 int i; 233 234 if (s->is_legacy_prep) { 235 for (i = 0; i < PCI_NUM_PINS; i++) { 236 sysbus_init_irq(dev, &s->pci_irqs[i]); 237 } 238 } else { 239 /* According to PReP specification section 6.1.6 "System Interrupt 240 * Assignments", all PCI interrupts are routed via IRQ 15 */ 241 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); 242 object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS, 243 &error_fatal); 244 qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal); 245 sysbus_init_irq(dev, &s->or_irq->out_irq); 246 247 for (i = 0; i < PCI_NUM_PINS; i++) { 248 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i); 249 } 250 } 251 252 qdev_init_gpio_in(d, raven_change_gpio, 1); 253 254 pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS); 255 256 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, 257 "pci-conf-idx", 4); 258 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); 259 260 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s, 261 "pci-conf-data", 4); 262 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); 263 264 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s, 265 "pciio", 0x00400000); 266 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); 267 268 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s, 269 "pci-intack", 1); 270 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); 271 272 /* TODO Remove once realize propagates to child devices. */ 273 qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp); 274 } 275 276 static void raven_pcihost_initfn(Object *obj) 277 { 278 PCIHostState *h = PCI_HOST_BRIDGE(obj); 279 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); 280 MemoryRegion *address_space_mem = get_system_memory(); 281 DeviceState *pci_dev; 282 283 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); 284 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, 285 "pci-io-non-contiguous", 0x00800000); 286 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000); 287 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); 288 289 /* CPU address space */ 290 memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io); 291 memory_region_add_subregion_overlap(address_space_mem, 0x80000000, 292 &s->pci_io_non_contiguous, 1); 293 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); 294 pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, 295 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); 296 297 /* Bus master address space */ 298 memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB); 299 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory", 300 &s->pci_memory, 0, 301 memory_region_size(&s->pci_memory)); 302 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system", 303 get_system_memory(), 0, 0x80000000); 304 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias); 305 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias); 306 address_space_init(&s->bm_as, &s->bm, "raven-bm"); 307 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s); 308 309 h->bus = &s->pci_bus; 310 311 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); 312 pci_dev = DEVICE(&s->pci_dev); 313 object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0), 314 NULL); 315 qdev_prop_set_bit(pci_dev, "multifunction", false); 316 } 317 318 static void raven_realize(PCIDevice *d, Error **errp) 319 { 320 RavenPCIState *s = RAVEN_PCI_DEVICE(d); 321 char *filename; 322 int bios_size = -1; 323 324 d->config[0x0C] = 0x08; // cache_line_size 325 d->config[0x0D] = 0x10; // latency_timer 326 d->config[0x34] = 0x00; // capabilities_pointer 327 328 memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE, 329 &error_fatal); 330 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), 331 &s->bios); 332 if (s->bios_name) { 333 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); 334 if (filename) { 335 if (s->elf_machine != EM_NONE) { 336 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 337 NULL, NULL, NULL, 1, s->elf_machine, 338 0, 0); 339 } 340 if (bios_size < 0) { 341 bios_size = get_image_size(filename); 342 if (bios_size > 0 && bios_size <= BIOS_SIZE) { 343 hwaddr bios_addr; 344 bios_size = (bios_size + 0xfff) & ~0xfff; 345 bios_addr = (uint32_t)(-BIOS_SIZE); 346 bios_size = load_image_targphys(filename, bios_addr, 347 bios_size); 348 } 349 } 350 } 351 g_free(filename); 352 if (bios_size < 0 || bios_size > BIOS_SIZE) { 353 memory_region_del_subregion(get_system_memory(), &s->bios); 354 error_setg(errp, "Could not load bios image '%s'", s->bios_name); 355 return; 356 } 357 } 358 359 vmstate_register_ram_global(&s->bios); 360 } 361 362 static const VMStateDescription vmstate_raven = { 363 .name = "raven", 364 .version_id = 0, 365 .minimum_version_id = 0, 366 .fields = (VMStateField[]) { 367 VMSTATE_PCI_DEVICE(dev, RavenPCIState), 368 VMSTATE_END_OF_LIST() 369 }, 370 }; 371 372 static void raven_class_init(ObjectClass *klass, void *data) 373 { 374 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 375 DeviceClass *dc = DEVICE_CLASS(klass); 376 377 k->realize = raven_realize; 378 k->vendor_id = PCI_VENDOR_ID_MOTOROLA; 379 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; 380 k->revision = 0x00; 381 k->class_id = PCI_CLASS_BRIDGE_HOST; 382 dc->desc = "PReP Host Bridge - Motorola Raven"; 383 dc->vmsd = &vmstate_raven; 384 /* 385 * Reason: PCI-facing part of the host bridge, not usable without 386 * the host-facing part, which can't be device_add'ed, yet. 387 */ 388 dc->user_creatable = false; 389 } 390 391 static const TypeInfo raven_info = { 392 .name = TYPE_RAVEN_PCI_DEVICE, 393 .parent = TYPE_PCI_DEVICE, 394 .instance_size = sizeof(RavenPCIState), 395 .class_init = raven_class_init, 396 .interfaces = (InterfaceInfo[]) { 397 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 398 { }, 399 }, 400 }; 401 402 static Property raven_pcihost_properties[] = { 403 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine, 404 EM_NONE), 405 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name), 406 /* Temporary workaround until legacy prep machine is removed */ 407 DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep, 408 false), 409 DEFINE_PROP_END_OF_LIST() 410 }; 411 412 static void raven_pcihost_class_init(ObjectClass *klass, void *data) 413 { 414 DeviceClass *dc = DEVICE_CLASS(klass); 415 416 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 417 dc->realize = raven_pcihost_realizefn; 418 device_class_set_props(dc, raven_pcihost_properties); 419 dc->fw_name = "pci"; 420 } 421 422 static const TypeInfo raven_pcihost_info = { 423 .name = TYPE_RAVEN_PCI_HOST_BRIDGE, 424 .parent = TYPE_PCI_HOST_BRIDGE, 425 .instance_size = sizeof(PREPPCIState), 426 .instance_init = raven_pcihost_initfn, 427 .class_init = raven_pcihost_class_init, 428 }; 429 430 static void raven_register_types(void) 431 { 432 type_register_static(&raven_pcihost_info); 433 type_register_static(&raven_info); 434 } 435 436 type_init(raven_register_types) 437