1 /* 2 * QEMU PowerPC E500 embedded processors pci controller emulation 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from ppc4xx_pci.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "hw/irq.h" 19 #include "hw/qdev-properties.h" 20 #include "migration/vmstate.h" 21 #include "hw/pci/pci_device.h" 22 #include "hw/pci/pci_host.h" 23 #include "qemu/bswap.h" 24 #include "hw/pci-host/ppce500.h" 25 #include "qom/object.h" 26 27 #ifdef DEBUG_PCI 28 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) 29 #else 30 #define pci_debug(fmt, ...) 31 #endif 32 33 #define PCIE500_CFGADDR 0x0 34 #define PCIE500_CFGDATA 0x4 35 #define PCIE500_REG_BASE 0xC00 36 #define PCIE500_ALL_SIZE 0x1000 37 #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) 38 39 #define PCIE500_PCI_IOLEN 0x10000ULL 40 41 #define PPCE500_PCI_CONFIG_ADDR 0x0 42 #define PPCE500_PCI_CONFIG_DATA 0x4 43 #define PPCE500_PCI_INTACK 0x8 44 45 #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) 46 #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) 47 #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) 48 #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) 49 #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) 50 #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) 51 #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) 52 53 #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) 54 55 #define PCI_POTAR 0x0 56 #define PCI_POTEAR 0x4 57 #define PCI_POWBAR 0x8 58 #define PCI_POWAR 0x10 59 60 #define PCI_PITAR 0x0 61 #define PCI_PIWBAR 0x8 62 #define PCI_PIWBEAR 0xC 63 #define PCI_PIWAR 0x10 64 65 #define PPCE500_PCI_NR_POBS 5 66 #define PPCE500_PCI_NR_PIBS 3 67 68 #define PIWAR_EN 0x80000000 /* Enable */ 69 #define PIWAR_PF 0x20000000 /* prefetch */ 70 #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ 71 #define PIWAR_READ_SNOOP 0x00050000 72 #define PIWAR_WRITE_SNOOP 0x00005000 73 #define PIWAR_SZ_MASK 0x0000003f 74 75 struct pci_outbound { 76 uint32_t potar; 77 uint32_t potear; 78 uint32_t powbar; 79 uint32_t powar; 80 MemoryRegion mem; 81 }; 82 83 struct pci_inbound { 84 uint32_t pitar; 85 uint32_t piwbar; 86 uint32_t piwbear; 87 uint32_t piwar; 88 MemoryRegion mem; 89 }; 90 91 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" 92 93 OBJECT_DECLARE_SIMPLE_TYPE(PPCE500PCIState, PPC_E500_PCI_HOST_BRIDGE) 94 95 struct PPCE500PCIState { 96 PCIHostState parent_obj; 97 98 struct pci_outbound pob[PPCE500_PCI_NR_POBS]; 99 struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; 100 uint32_t gasket_time; 101 qemu_irq irq[PCI_NUM_PINS]; 102 uint32_t irq_num[PCI_NUM_PINS]; 103 uint32_t first_slot; 104 uint32_t first_pin_irq; 105 AddressSpace bm_as; 106 MemoryRegion bm; 107 /* mmio maps */ 108 MemoryRegion container; 109 MemoryRegion iomem; 110 MemoryRegion pio; 111 MemoryRegion busmem; 112 }; 113 114 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" 115 OBJECT_DECLARE_SIMPLE_TYPE(PPCE500PCIBridgeState, PPC_E500_PCI_BRIDGE) 116 117 struct PPCE500PCIBridgeState { 118 /*< private >*/ 119 PCIDevice parent; 120 /*< public >*/ 121 122 MemoryRegion bar0; 123 }; 124 125 126 static uint64_t pci_reg_read4(void *opaque, hwaddr addr, 127 unsigned size) 128 { 129 PPCE500PCIState *pci = opaque; 130 unsigned long win; 131 uint32_t value = 0; 132 int idx; 133 134 win = addr & 0xfe0; 135 136 switch (win) { 137 case PPCE500_PCI_OW1: 138 case PPCE500_PCI_OW2: 139 case PPCE500_PCI_OW3: 140 case PPCE500_PCI_OW4: 141 idx = (addr >> 5) & 0x7; 142 switch (addr & 0x1F) { 143 case PCI_POTAR: 144 value = pci->pob[idx].potar; 145 break; 146 case PCI_POTEAR: 147 value = pci->pob[idx].potear; 148 break; 149 case PCI_POWBAR: 150 value = pci->pob[idx].powbar; 151 break; 152 case PCI_POWAR: 153 value = pci->pob[idx].powar; 154 break; 155 default: 156 break; 157 } 158 break; 159 160 case PPCE500_PCI_IW3: 161 case PPCE500_PCI_IW2: 162 case PPCE500_PCI_IW1: 163 idx = ((addr >> 5) & 0x3) - 1; 164 switch (addr & 0x1F) { 165 case PCI_PITAR: 166 value = pci->pib[idx].pitar; 167 break; 168 case PCI_PIWBAR: 169 value = pci->pib[idx].piwbar; 170 break; 171 case PCI_PIWBEAR: 172 value = pci->pib[idx].piwbear; 173 break; 174 case PCI_PIWAR: 175 value = pci->pib[idx].piwar; 176 break; 177 default: 178 break; 179 }; 180 break; 181 182 case PPCE500_PCI_GASKET_TIMR: 183 value = pci->gasket_time; 184 break; 185 186 default: 187 break; 188 } 189 190 pci_debug("%s: win:%lx(addr:" HWADDR_FMT_plx ") -> value:%x\n", __func__, 191 win, addr, value); 192 return value; 193 } 194 195 /* DMA mapping */ 196 static void e500_update_piw(PPCE500PCIState *pci, int idx) 197 { 198 uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12; 199 uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12; 200 uint64_t war = pci->pib[idx].piwar; 201 uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); 202 MemoryRegion *address_space_mem = get_system_memory(); 203 MemoryRegion *mem = &pci->pib[idx].mem; 204 MemoryRegion *bm = &pci->bm; 205 char *name; 206 207 if (memory_region_is_mapped(mem)) { 208 /* Before we modify anything, unmap and destroy the region */ 209 memory_region_del_subregion(bm, mem); 210 object_unparent(OBJECT(mem)); 211 } 212 213 if (!(war & PIWAR_EN)) { 214 /* Not enabled, nothing to do */ 215 return; 216 } 217 218 name = g_strdup_printf("PCI Inbound Window %d", idx); 219 memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar, 220 size); 221 memory_region_add_subregion_overlap(bm, wbar, mem, -1); 222 g_free(name); 223 224 pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n", 225 __func__, size, wbar, tar); 226 } 227 228 /* BAR mapping */ 229 static void e500_update_pow(PPCE500PCIState *pci, int idx) 230 { 231 uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12; 232 uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12; 233 uint64_t war = pci->pob[idx].powar; 234 uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); 235 MemoryRegion *mem = &pci->pob[idx].mem; 236 MemoryRegion *address_space_mem = get_system_memory(); 237 char *name; 238 239 if (memory_region_is_mapped(mem)) { 240 /* Before we modify anything, unmap and destroy the region */ 241 memory_region_del_subregion(address_space_mem, mem); 242 object_unparent(OBJECT(mem)); 243 } 244 245 if (!(war & PIWAR_EN)) { 246 /* Not enabled, nothing to do */ 247 return; 248 } 249 250 name = g_strdup_printf("PCI Outbound Window %d", idx); 251 memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar, 252 size); 253 memory_region_add_subregion(address_space_mem, wbar, mem); 254 g_free(name); 255 256 pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n", 257 __func__, size, wbar, tar); 258 } 259 260 static void pci_reg_write4(void *opaque, hwaddr addr, 261 uint64_t value, unsigned size) 262 { 263 PPCE500PCIState *pci = opaque; 264 unsigned long win; 265 int idx; 266 267 win = addr & 0xfe0; 268 269 pci_debug("%s: value:%x -> win:%lx(addr:" HWADDR_FMT_plx ")\n", 270 __func__, (unsigned)value, win, addr); 271 272 switch (win) { 273 case PPCE500_PCI_OW1: 274 case PPCE500_PCI_OW2: 275 case PPCE500_PCI_OW3: 276 case PPCE500_PCI_OW4: 277 idx = (addr >> 5) & 0x7; 278 switch (addr & 0x1F) { 279 case PCI_POTAR: 280 pci->pob[idx].potar = value; 281 e500_update_pow(pci, idx); 282 break; 283 case PCI_POTEAR: 284 pci->pob[idx].potear = value; 285 e500_update_pow(pci, idx); 286 break; 287 case PCI_POWBAR: 288 pci->pob[idx].powbar = value; 289 e500_update_pow(pci, idx); 290 break; 291 case PCI_POWAR: 292 pci->pob[idx].powar = value; 293 e500_update_pow(pci, idx); 294 break; 295 default: 296 break; 297 }; 298 break; 299 300 case PPCE500_PCI_IW3: 301 case PPCE500_PCI_IW2: 302 case PPCE500_PCI_IW1: 303 idx = ((addr >> 5) & 0x3) - 1; 304 switch (addr & 0x1F) { 305 case PCI_PITAR: 306 pci->pib[idx].pitar = value; 307 e500_update_piw(pci, idx); 308 break; 309 case PCI_PIWBAR: 310 pci->pib[idx].piwbar = value; 311 e500_update_piw(pci, idx); 312 break; 313 case PCI_PIWBEAR: 314 pci->pib[idx].piwbear = value; 315 e500_update_piw(pci, idx); 316 break; 317 case PCI_PIWAR: 318 pci->pib[idx].piwar = value; 319 e500_update_piw(pci, idx); 320 break; 321 default: 322 break; 323 }; 324 break; 325 326 case PPCE500_PCI_GASKET_TIMR: 327 pci->gasket_time = value; 328 break; 329 330 default: 331 break; 332 }; 333 } 334 335 static const MemoryRegionOps e500_pci_reg_ops = { 336 .read = pci_reg_read4, 337 .write = pci_reg_write4, 338 .endianness = DEVICE_BIG_ENDIAN, 339 }; 340 341 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) 342 { 343 int devno = PCI_SLOT(pci_dev->devfn); 344 int ret; 345 346 ret = ppce500_pci_map_irq_slot(devno, pin); 347 348 pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, 349 pci_dev->devfn, pin, ret, devno); 350 351 return ret; 352 } 353 354 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level) 355 { 356 PPCE500PCIState *s = opaque; 357 qemu_irq *pic = s->irq; 358 359 pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); 360 361 qemu_set_irq(pic[pin], level); 362 } 363 364 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin) 365 { 366 PCIINTxRoute route; 367 PPCE500PCIState *s = opaque; 368 369 route.mode = PCI_INTX_ENABLED; 370 route.irq = s->irq_num[pin]; 371 372 pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); 373 return route; 374 } 375 376 static const VMStateDescription vmstate_pci_outbound = { 377 .name = "pci_outbound", 378 .version_id = 0, 379 .minimum_version_id = 0, 380 .fields = (const VMStateField[]) { 381 VMSTATE_UINT32(potar, struct pci_outbound), 382 VMSTATE_UINT32(potear, struct pci_outbound), 383 VMSTATE_UINT32(powbar, struct pci_outbound), 384 VMSTATE_UINT32(powar, struct pci_outbound), 385 VMSTATE_END_OF_LIST() 386 } 387 }; 388 389 static const VMStateDescription vmstate_pci_inbound = { 390 .name = "pci_inbound", 391 .version_id = 0, 392 .minimum_version_id = 0, 393 .fields = (const VMStateField[]) { 394 VMSTATE_UINT32(pitar, struct pci_inbound), 395 VMSTATE_UINT32(piwbar, struct pci_inbound), 396 VMSTATE_UINT32(piwbear, struct pci_inbound), 397 VMSTATE_UINT32(piwar, struct pci_inbound), 398 VMSTATE_END_OF_LIST() 399 } 400 }; 401 402 static const VMStateDescription vmstate_ppce500_pci = { 403 .name = "ppce500_pci", 404 .version_id = 1, 405 .minimum_version_id = 1, 406 .fields = (const VMStateField[]) { 407 VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, 408 vmstate_pci_outbound, struct pci_outbound), 409 VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, 410 vmstate_pci_inbound, struct pci_inbound), 411 VMSTATE_UINT32(gasket_time, PPCE500PCIState), 412 VMSTATE_END_OF_LIST() 413 } 414 }; 415 416 417 static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp) 418 { 419 PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); 420 SysBusDevice *ccsr = SYS_BUS_DEVICE( 421 object_resolve_path_component(qdev_get_machine(), "e500-ccsr")); 422 MemoryRegion *ccsr_space = sysbus_mmio_get_region(ccsr, 0); 423 424 memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", 425 ccsr_space, 0, int128_get64(ccsr_space->size)); 426 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); 427 } 428 429 static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque, 430 int devfn) 431 { 432 PPCE500PCIState *s = opaque; 433 434 return &s->bm_as; 435 } 436 437 static const PCIIOMMUOps ppce500_iommu_ops = { 438 .get_address_space = e500_pcihost_set_iommu, 439 }; 440 441 static void e500_pcihost_realize(DeviceState *dev, Error **errp) 442 { 443 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 444 PCIHostState *h; 445 PPCE500PCIState *s; 446 PCIBus *b; 447 int i; 448 449 h = PCI_HOST_BRIDGE(dev); 450 s = PPC_E500_PCI_HOST_BRIDGE(dev); 451 452 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 453 sysbus_init_irq(sbd, &s->irq[i]); 454 } 455 456 for (i = 0; i < PCI_NUM_PINS; i++) { 457 s->irq_num[i] = s->first_pin_irq + i; 458 } 459 460 memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); 461 memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX); 462 463 /* PIO lives at the bottom of our bus space */ 464 memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2); 465 466 b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq, 467 mpc85xx_pci_map_irq, s, &s->busmem, &s->pio, 468 PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); 469 h->bus = b; 470 471 /* Set up PCI view of memory */ 472 memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX); 473 memory_region_add_subregion(&s->bm, 0x0, &s->busmem); 474 address_space_init(&s->bm_as, &s->bm, "pci-bm"); 475 pci_setup_iommu(b, &ppce500_iommu_ops, s); 476 477 pci_create_simple(b, 0, TYPE_PPC_E500_PCI_BRIDGE); 478 479 memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); 480 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h, 481 "pci-conf-idx", 4); 482 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h, 483 "pci-conf-data", 4); 484 memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s, 485 "pci.reg", PCIE500_REG_SIZE); 486 memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); 487 memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); 488 memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); 489 sysbus_init_mmio(sbd, &s->container); 490 pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq); 491 } 492 493 static void e500_host_bridge_class_init(ObjectClass *klass, const void *data) 494 { 495 DeviceClass *dc = DEVICE_CLASS(klass); 496 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 497 498 k->realize = e500_pcihost_bridge_realize; 499 k->vendor_id = PCI_VENDOR_ID_FREESCALE; 500 k->device_id = PCI_DEVICE_ID_MPC8533E; 501 k->class_id = PCI_CLASS_PROCESSOR_POWERPC; 502 dc->desc = "Host bridge"; 503 /* 504 * PCI-facing part of the host bridge, not usable without the 505 * host-facing part, which can't be device_add'ed, yet. 506 */ 507 dc->user_creatable = false; 508 } 509 510 static const Property pcihost_properties[] = { 511 DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), 512 DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1), 513 }; 514 515 static void e500_pcihost_class_init(ObjectClass *klass, const void *data) 516 { 517 DeviceClass *dc = DEVICE_CLASS(klass); 518 519 dc->realize = e500_pcihost_realize; 520 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 521 device_class_set_props(dc, pcihost_properties); 522 dc->vmsd = &vmstate_ppce500_pci; 523 } 524 525 static const TypeInfo e500_pci_types[] = { 526 { 527 .name = TYPE_PPC_E500_PCI_BRIDGE, 528 .parent = TYPE_PCI_DEVICE, 529 .instance_size = sizeof(PPCE500PCIBridgeState), 530 .class_init = e500_host_bridge_class_init, 531 .interfaces = (const InterfaceInfo[]) { 532 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 533 { }, 534 }, 535 }, 536 { 537 .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, 538 .parent = TYPE_PCI_HOST_BRIDGE, 539 .instance_size = sizeof(PPCE500PCIState), 540 .class_init = e500_pcihost_class_init, 541 }, 542 }; 543 544 DEFINE_TYPES(e500_pci_types) 545