1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, see <http://www.gnu.org/licenses/>. 13 * 14 * Copyright IBM Corp. 2008 15 * 16 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 17 */ 18 19 /* This file implements emulation of the 32-bit PCI controller found in some 20 * 4xx SoCs, such as the 440EP. */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/log.h" 24 #include "hw/irq.h" 25 #include "hw/ppc/ppc.h" 26 #include "hw/ppc/ppc4xx.h" 27 #include "migration/vmstate.h" 28 #include "qemu/module.h" 29 #include "sysemu/reset.h" 30 #include "hw/pci/pci.h" 31 #include "hw/pci/pci_host.h" 32 #include "trace.h" 33 #include "qom/object.h" 34 35 struct PCIMasterMap { 36 uint32_t la; 37 uint32_t ma; 38 uint32_t pcila; 39 uint32_t pciha; 40 }; 41 42 struct PCITargetMap { 43 uint32_t ms; 44 uint32_t la; 45 }; 46 47 OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE) 48 49 #define PPC4xx_PCI_NR_PMMS 3 50 #define PPC4xx_PCI_NR_PTMS 2 51 52 #define PPC4xx_PCI_NUM_DEVS 5 53 54 struct PPC4xxPCIState { 55 PCIHostState parent_obj; 56 57 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS]; 58 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS]; 59 qemu_irq irq[PPC4xx_PCI_NUM_DEVS]; 60 61 MemoryRegion container; 62 MemoryRegion iomem; 63 }; 64 65 #define PCIC0_CFGADDR 0x0 66 #define PCIC0_CFGDATA 0x4 67 68 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to 69 * PCI accesses. */ 70 #define PCIL0_PMM0LA 0x0 71 #define PCIL0_PMM0MA 0x4 72 #define PCIL0_PMM0PCILA 0x8 73 #define PCIL0_PMM0PCIHA 0xc 74 #define PCIL0_PMM1LA 0x10 75 #define PCIL0_PMM1MA 0x14 76 #define PCIL0_PMM1PCILA 0x18 77 #define PCIL0_PMM1PCIHA 0x1c 78 #define PCIL0_PMM2LA 0x20 79 #define PCIL0_PMM2MA 0x24 80 #define PCIL0_PMM2PCILA 0x28 81 #define PCIL0_PMM2PCIHA 0x2c 82 83 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to 84 * PLB accesses. */ 85 #define PCIL0_PTM1MS 0x30 86 #define PCIL0_PTM1LA 0x34 87 #define PCIL0_PTM2MS 0x38 88 #define PCIL0_PTM2LA 0x3c 89 #define PCI_REG_BASE 0x800000 90 #define PCI_REG_SIZE 0x40 91 92 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE) 93 94 static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset, 95 uint64_t value, unsigned size) 96 { 97 struct PPC4xxPCIState *pci = opaque; 98 99 /* We ignore all target attempts at PCI configuration, effectively 100 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ 101 102 switch (offset) { 103 case PCIL0_PMM0LA: 104 pci->pmm[0].la = value; 105 break; 106 case PCIL0_PMM0MA: 107 pci->pmm[0].ma = value; 108 break; 109 case PCIL0_PMM0PCIHA: 110 pci->pmm[0].pciha = value; 111 break; 112 case PCIL0_PMM0PCILA: 113 pci->pmm[0].pcila = value; 114 break; 115 116 case PCIL0_PMM1LA: 117 pci->pmm[1].la = value; 118 break; 119 case PCIL0_PMM1MA: 120 pci->pmm[1].ma = value; 121 break; 122 case PCIL0_PMM1PCIHA: 123 pci->pmm[1].pciha = value; 124 break; 125 case PCIL0_PMM1PCILA: 126 pci->pmm[1].pcila = value; 127 break; 128 129 case PCIL0_PMM2LA: 130 pci->pmm[2].la = value; 131 break; 132 case PCIL0_PMM2MA: 133 pci->pmm[2].ma = value; 134 break; 135 case PCIL0_PMM2PCIHA: 136 pci->pmm[2].pciha = value; 137 break; 138 case PCIL0_PMM2PCILA: 139 pci->pmm[2].pcila = value; 140 break; 141 142 case PCIL0_PTM1MS: 143 pci->ptm[0].ms = value; 144 break; 145 case PCIL0_PTM1LA: 146 pci->ptm[0].la = value; 147 break; 148 case PCIL0_PTM2MS: 149 pci->ptm[1].ms = value; 150 break; 151 case PCIL0_PTM2LA: 152 pci->ptm[1].la = value; 153 break; 154 155 default: 156 qemu_log_mask(LOG_GUEST_ERROR, 157 "%s: unhandled PCI internal register 0x%" HWADDR_PRIx "\n", 158 __func__, offset); 159 break; 160 } 161 } 162 163 static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset, 164 unsigned size) 165 { 166 struct PPC4xxPCIState *pci = opaque; 167 uint32_t value; 168 169 switch (offset) { 170 case PCIL0_PMM0LA: 171 value = pci->pmm[0].la; 172 break; 173 case PCIL0_PMM0MA: 174 value = pci->pmm[0].ma; 175 break; 176 case PCIL0_PMM0PCIHA: 177 value = pci->pmm[0].pciha; 178 break; 179 case PCIL0_PMM0PCILA: 180 value = pci->pmm[0].pcila; 181 break; 182 183 case PCIL0_PMM1LA: 184 value = pci->pmm[1].la; 185 break; 186 case PCIL0_PMM1MA: 187 value = pci->pmm[1].ma; 188 break; 189 case PCIL0_PMM1PCIHA: 190 value = pci->pmm[1].pciha; 191 break; 192 case PCIL0_PMM1PCILA: 193 value = pci->pmm[1].pcila; 194 break; 195 196 case PCIL0_PMM2LA: 197 value = pci->pmm[2].la; 198 break; 199 case PCIL0_PMM2MA: 200 value = pci->pmm[2].ma; 201 break; 202 case PCIL0_PMM2PCIHA: 203 value = pci->pmm[2].pciha; 204 break; 205 case PCIL0_PMM2PCILA: 206 value = pci->pmm[2].pcila; 207 break; 208 209 case PCIL0_PTM1MS: 210 value = pci->ptm[0].ms; 211 break; 212 case PCIL0_PTM1LA: 213 value = pci->ptm[0].la; 214 break; 215 case PCIL0_PTM2MS: 216 value = pci->ptm[1].ms; 217 break; 218 case PCIL0_PTM2LA: 219 value = pci->ptm[1].la; 220 break; 221 222 default: 223 qemu_log_mask(LOG_GUEST_ERROR, 224 "%s: invalid PCI internal register 0x%" HWADDR_PRIx "\n", 225 __func__, offset); 226 value = 0; 227 } 228 229 return value; 230 } 231 232 static const MemoryRegionOps pci_reg_ops = { 233 .read = ppc4xx_pci_reg_read4, 234 .write = ppc4xx_pci_reg_write4, 235 .endianness = DEVICE_LITTLE_ENDIAN, 236 }; 237 238 static void ppc4xx_pci_reset(void *opaque) 239 { 240 struct PPC4xxPCIState *pci = opaque; 241 242 memset(pci->pmm, 0, sizeof(pci->pmm)); 243 memset(pci->ptm, 0, sizeof(pci->ptm)); 244 } 245 246 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This 247 * may need further refactoring for other boards. */ 248 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) 249 { 250 int slot = PCI_SLOT(pci_dev->devfn); 251 252 trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot); 253 254 return slot > 0 ? slot - 1 : PPC4xx_PCI_NUM_DEVS - 1; 255 } 256 257 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) 258 { 259 qemu_irq *pci_irqs = opaque; 260 261 trace_ppc4xx_pci_set_irq(irq_num); 262 assert(irq_num >= 0 && irq_num < PPC4xx_PCI_NUM_DEVS); 263 qemu_set_irq(pci_irqs[irq_num], level); 264 } 265 266 static const VMStateDescription vmstate_pci_master_map = { 267 .name = "pci_master_map", 268 .version_id = 0, 269 .minimum_version_id = 0, 270 .fields = (VMStateField[]) { 271 VMSTATE_UINT32(la, struct PCIMasterMap), 272 VMSTATE_UINT32(ma, struct PCIMasterMap), 273 VMSTATE_UINT32(pcila, struct PCIMasterMap), 274 VMSTATE_UINT32(pciha, struct PCIMasterMap), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 static const VMStateDescription vmstate_pci_target_map = { 280 .name = "pci_target_map", 281 .version_id = 0, 282 .minimum_version_id = 0, 283 .fields = (VMStateField[]) { 284 VMSTATE_UINT32(ms, struct PCITargetMap), 285 VMSTATE_UINT32(la, struct PCITargetMap), 286 VMSTATE_END_OF_LIST() 287 } 288 }; 289 290 static const VMStateDescription vmstate_ppc4xx_pci = { 291 .name = "ppc4xx_pci", 292 .version_id = 1, 293 .minimum_version_id = 1, 294 .fields = (VMStateField[]) { 295 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1, 296 vmstate_pci_master_map, 297 struct PCIMasterMap), 298 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1, 299 vmstate_pci_target_map, 300 struct PCITargetMap), 301 VMSTATE_END_OF_LIST() 302 } 303 }; 304 305 /* XXX Interrupt acknowledge cycles not supported. */ 306 static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp) 307 { 308 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 309 PPC4xxPCIState *s; 310 PCIHostState *h; 311 PCIBus *b; 312 int i; 313 314 h = PCI_HOST_BRIDGE(dev); 315 s = PPC4xx_PCI_HOST_BRIDGE(dev); 316 317 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 318 sysbus_init_irq(sbd, &s->irq[i]); 319 } 320 321 b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq, 322 ppc4xx_pci_map_irq, s->irq, get_system_memory(), 323 get_system_io(), 0, ARRAY_SIZE(s->irq), 324 TYPE_PCI_BUS); 325 h->bus = b; 326 327 pci_create_simple(b, 0, "ppc4xx-host-bridge"); 328 329 /* XXX split into 2 memory regions, one for config space, one for regs */ 330 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE); 331 memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h, 332 "pci-conf-idx", 4); 333 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h, 334 "pci-conf-data", 4); 335 memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s, 336 "pci.reg", PCI_REG_SIZE); 337 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem); 338 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem); 339 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem); 340 sysbus_init_mmio(sbd, &s->container); 341 qemu_register_reset(ppc4xx_pci_reset, s); 342 } 343 344 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data) 345 { 346 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 347 DeviceClass *dc = DEVICE_CLASS(klass); 348 349 dc->desc = "Host bridge"; 350 k->vendor_id = PCI_VENDOR_ID_IBM; 351 k->device_id = PCI_DEVICE_ID_IBM_440GX; 352 k->class_id = PCI_CLASS_BRIDGE_OTHER; 353 /* 354 * PCI-facing part of the host bridge, not usable without the 355 * host-facing part, which can't be device_add'ed, yet. 356 */ 357 dc->user_creatable = false; 358 } 359 360 static const TypeInfo ppc4xx_host_bridge_info = { 361 .name = "ppc4xx-host-bridge", 362 .parent = TYPE_PCI_DEVICE, 363 .instance_size = sizeof(PCIDevice), 364 .class_init = ppc4xx_host_bridge_class_init, 365 .interfaces = (InterfaceInfo[]) { 366 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 367 { }, 368 }, 369 }; 370 371 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data) 372 { 373 DeviceClass *dc = DEVICE_CLASS(klass); 374 375 dc->realize = ppc4xx_pcihost_realize; 376 dc->vmsd = &vmstate_ppc4xx_pci; 377 } 378 379 static const TypeInfo ppc4xx_pcihost_info = { 380 .name = TYPE_PPC4xx_PCI_HOST_BRIDGE, 381 .parent = TYPE_PCI_HOST_BRIDGE, 382 .instance_size = sizeof(PPC4xxPCIState), 383 .class_init = ppc4xx_pcihost_class_init, 384 }; 385 386 static void ppc4xx_pci_register_types(void) 387 { 388 type_register_static(&ppc4xx_pcihost_info); 389 type_register_static(&ppc4xx_host_bridge_info); 390 } 391 392 type_init(ppc4xx_pci_register_types) 393