1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, see <http://www.gnu.org/licenses/>. 13 * 14 * Copyright IBM Corp. 2008 15 * 16 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 17 */ 18 19 /* This file implements emulation of the 32-bit PCI controller found in some 20 * 4xx SoCs, such as the 440EP. */ 21 22 #include "qemu/osdep.h" 23 #include "hw/hw.h" 24 #include "hw/ppc/ppc.h" 25 #include "hw/ppc/ppc4xx.h" 26 #include "qemu/module.h" 27 #include "sysemu/reset.h" 28 #include "hw/pci/pci.h" 29 #include "hw/pci/pci_host.h" 30 #include "exec/address-spaces.h" 31 #include "trace.h" 32 33 struct PCIMasterMap { 34 uint32_t la; 35 uint32_t ma; 36 uint32_t pcila; 37 uint32_t pciha; 38 }; 39 40 struct PCITargetMap { 41 uint32_t ms; 42 uint32_t la; 43 }; 44 45 #define PPC4xx_PCI_HOST_BRIDGE(obj) \ 46 OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE) 47 48 #define PPC4xx_PCI_NR_PMMS 3 49 #define PPC4xx_PCI_NR_PTMS 2 50 51 struct PPC4xxPCIState { 52 PCIHostState parent_obj; 53 54 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS]; 55 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS]; 56 qemu_irq irq[4]; 57 58 MemoryRegion container; 59 MemoryRegion iomem; 60 }; 61 typedef struct PPC4xxPCIState PPC4xxPCIState; 62 63 #define PCIC0_CFGADDR 0x0 64 #define PCIC0_CFGDATA 0x4 65 66 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to 67 * PCI accesses. */ 68 #define PCIL0_PMM0LA 0x0 69 #define PCIL0_PMM0MA 0x4 70 #define PCIL0_PMM0PCILA 0x8 71 #define PCIL0_PMM0PCIHA 0xc 72 #define PCIL0_PMM1LA 0x10 73 #define PCIL0_PMM1MA 0x14 74 #define PCIL0_PMM1PCILA 0x18 75 #define PCIL0_PMM1PCIHA 0x1c 76 #define PCIL0_PMM2LA 0x20 77 #define PCIL0_PMM2MA 0x24 78 #define PCIL0_PMM2PCILA 0x28 79 #define PCIL0_PMM2PCIHA 0x2c 80 81 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to 82 * PLB accesses. */ 83 #define PCIL0_PTM1MS 0x30 84 #define PCIL0_PTM1LA 0x34 85 #define PCIL0_PTM2MS 0x38 86 #define PCIL0_PTM2LA 0x3c 87 #define PCI_REG_BASE 0x800000 88 #define PCI_REG_SIZE 0x40 89 90 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE) 91 92 static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset, 93 uint64_t value, unsigned size) 94 { 95 struct PPC4xxPCIState *pci = opaque; 96 97 /* We ignore all target attempts at PCI configuration, effectively 98 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ 99 100 switch (offset) { 101 case PCIL0_PMM0LA: 102 pci->pmm[0].la = value; 103 break; 104 case PCIL0_PMM0MA: 105 pci->pmm[0].ma = value; 106 break; 107 case PCIL0_PMM0PCIHA: 108 pci->pmm[0].pciha = value; 109 break; 110 case PCIL0_PMM0PCILA: 111 pci->pmm[0].pcila = value; 112 break; 113 114 case PCIL0_PMM1LA: 115 pci->pmm[1].la = value; 116 break; 117 case PCIL0_PMM1MA: 118 pci->pmm[1].ma = value; 119 break; 120 case PCIL0_PMM1PCIHA: 121 pci->pmm[1].pciha = value; 122 break; 123 case PCIL0_PMM1PCILA: 124 pci->pmm[1].pcila = value; 125 break; 126 127 case PCIL0_PMM2LA: 128 pci->pmm[2].la = value; 129 break; 130 case PCIL0_PMM2MA: 131 pci->pmm[2].ma = value; 132 break; 133 case PCIL0_PMM2PCIHA: 134 pci->pmm[2].pciha = value; 135 break; 136 case PCIL0_PMM2PCILA: 137 pci->pmm[2].pcila = value; 138 break; 139 140 case PCIL0_PTM1MS: 141 pci->ptm[0].ms = value; 142 break; 143 case PCIL0_PTM1LA: 144 pci->ptm[0].la = value; 145 break; 146 case PCIL0_PTM2MS: 147 pci->ptm[1].ms = value; 148 break; 149 case PCIL0_PTM2LA: 150 pci->ptm[1].la = value; 151 break; 152 153 default: 154 printf("%s: unhandled PCI internal register 0x%lx\n", __func__, 155 (unsigned long)offset); 156 break; 157 } 158 } 159 160 static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset, 161 unsigned size) 162 { 163 struct PPC4xxPCIState *pci = opaque; 164 uint32_t value; 165 166 switch (offset) { 167 case PCIL0_PMM0LA: 168 value = pci->pmm[0].la; 169 break; 170 case PCIL0_PMM0MA: 171 value = pci->pmm[0].ma; 172 break; 173 case PCIL0_PMM0PCIHA: 174 value = pci->pmm[0].pciha; 175 break; 176 case PCIL0_PMM0PCILA: 177 value = pci->pmm[0].pcila; 178 break; 179 180 case PCIL0_PMM1LA: 181 value = pci->pmm[1].la; 182 break; 183 case PCIL0_PMM1MA: 184 value = pci->pmm[1].ma; 185 break; 186 case PCIL0_PMM1PCIHA: 187 value = pci->pmm[1].pciha; 188 break; 189 case PCIL0_PMM1PCILA: 190 value = pci->pmm[1].pcila; 191 break; 192 193 case PCIL0_PMM2LA: 194 value = pci->pmm[2].la; 195 break; 196 case PCIL0_PMM2MA: 197 value = pci->pmm[2].ma; 198 break; 199 case PCIL0_PMM2PCIHA: 200 value = pci->pmm[2].pciha; 201 break; 202 case PCIL0_PMM2PCILA: 203 value = pci->pmm[2].pcila; 204 break; 205 206 case PCIL0_PTM1MS: 207 value = pci->ptm[0].ms; 208 break; 209 case PCIL0_PTM1LA: 210 value = pci->ptm[0].la; 211 break; 212 case PCIL0_PTM2MS: 213 value = pci->ptm[1].ms; 214 break; 215 case PCIL0_PTM2LA: 216 value = pci->ptm[1].la; 217 break; 218 219 default: 220 printf("%s: invalid PCI internal register 0x%lx\n", __func__, 221 (unsigned long)offset); 222 value = 0; 223 } 224 225 return value; 226 } 227 228 static const MemoryRegionOps pci_reg_ops = { 229 .read = ppc4xx_pci_reg_read4, 230 .write = ppc4xx_pci_reg_write4, 231 .endianness = DEVICE_LITTLE_ENDIAN, 232 }; 233 234 static void ppc4xx_pci_reset(void *opaque) 235 { 236 struct PPC4xxPCIState *pci = opaque; 237 238 memset(pci->pmm, 0, sizeof(pci->pmm)); 239 memset(pci->ptm, 0, sizeof(pci->ptm)); 240 } 241 242 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This 243 * may need further refactoring for other boards. */ 244 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) 245 { 246 int slot = pci_dev->devfn >> 3; 247 248 trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot); 249 250 return slot - 1; 251 } 252 253 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) 254 { 255 qemu_irq *pci_irqs = opaque; 256 257 trace_ppc4xx_pci_set_irq(irq_num); 258 if (irq_num < 0) { 259 fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num); 260 return; 261 } 262 qemu_set_irq(pci_irqs[irq_num], level); 263 } 264 265 static const VMStateDescription vmstate_pci_master_map = { 266 .name = "pci_master_map", 267 .version_id = 0, 268 .minimum_version_id = 0, 269 .fields = (VMStateField[]) { 270 VMSTATE_UINT32(la, struct PCIMasterMap), 271 VMSTATE_UINT32(ma, struct PCIMasterMap), 272 VMSTATE_UINT32(pcila, struct PCIMasterMap), 273 VMSTATE_UINT32(pciha, struct PCIMasterMap), 274 VMSTATE_END_OF_LIST() 275 } 276 }; 277 278 static const VMStateDescription vmstate_pci_target_map = { 279 .name = "pci_target_map", 280 .version_id = 0, 281 .minimum_version_id = 0, 282 .fields = (VMStateField[]) { 283 VMSTATE_UINT32(ms, struct PCITargetMap), 284 VMSTATE_UINT32(la, struct PCITargetMap), 285 VMSTATE_END_OF_LIST() 286 } 287 }; 288 289 static const VMStateDescription vmstate_ppc4xx_pci = { 290 .name = "ppc4xx_pci", 291 .version_id = 1, 292 .minimum_version_id = 1, 293 .fields = (VMStateField[]) { 294 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1, 295 vmstate_pci_master_map, 296 struct PCIMasterMap), 297 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1, 298 vmstate_pci_target_map, 299 struct PCITargetMap), 300 VMSTATE_END_OF_LIST() 301 } 302 }; 303 304 /* XXX Interrupt acknowledge cycles not supported. */ 305 static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp) 306 { 307 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 308 PPC4xxPCIState *s; 309 PCIHostState *h; 310 PCIBus *b; 311 int i; 312 313 h = PCI_HOST_BRIDGE(dev); 314 s = PPC4xx_PCI_HOST_BRIDGE(dev); 315 316 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 317 sysbus_init_irq(sbd, &s->irq[i]); 318 } 319 320 b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq, 321 ppc4xx_pci_map_irq, s->irq, get_system_memory(), 322 get_system_io(), 0, 4, TYPE_PCI_BUS); 323 h->bus = b; 324 325 pci_create_simple(b, 0, "ppc4xx-host-bridge"); 326 327 /* XXX split into 2 memory regions, one for config space, one for regs */ 328 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE); 329 memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h, 330 "pci-conf-idx", 4); 331 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h, 332 "pci-conf-data", 4); 333 memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s, 334 "pci.reg", PCI_REG_SIZE); 335 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem); 336 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem); 337 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem); 338 sysbus_init_mmio(sbd, &s->container); 339 qemu_register_reset(ppc4xx_pci_reset, s); 340 } 341 342 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data) 343 { 344 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 345 DeviceClass *dc = DEVICE_CLASS(klass); 346 347 dc->desc = "Host bridge"; 348 k->vendor_id = PCI_VENDOR_ID_IBM; 349 k->device_id = PCI_DEVICE_ID_IBM_440GX; 350 k->class_id = PCI_CLASS_BRIDGE_OTHER; 351 /* 352 * PCI-facing part of the host bridge, not usable without the 353 * host-facing part, which can't be device_add'ed, yet. 354 */ 355 dc->user_creatable = false; 356 } 357 358 static const TypeInfo ppc4xx_host_bridge_info = { 359 .name = "ppc4xx-host-bridge", 360 .parent = TYPE_PCI_DEVICE, 361 .instance_size = sizeof(PCIDevice), 362 .class_init = ppc4xx_host_bridge_class_init, 363 .interfaces = (InterfaceInfo[]) { 364 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 365 { }, 366 }, 367 }; 368 369 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data) 370 { 371 DeviceClass *dc = DEVICE_CLASS(klass); 372 373 dc->realize = ppc4xx_pcihost_realize; 374 dc->vmsd = &vmstate_ppc4xx_pci; 375 } 376 377 static const TypeInfo ppc4xx_pcihost_info = { 378 .name = TYPE_PPC4xx_PCI_HOST_BRIDGE, 379 .parent = TYPE_PCI_HOST_BRIDGE, 380 .instance_size = sizeof(PPC4xxPCIState), 381 .class_init = ppc4xx_pcihost_class_init, 382 }; 383 384 static void ppc4xx_pci_register_types(void) 385 { 386 type_register_static(&ppc4xx_pcihost_info); 387 type_register_static(&ppc4xx_host_bridge_info); 388 } 389 390 type_init(ppc4xx_pci_register_types) 391