1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, see <http://www.gnu.org/licenses/>. 13 * 14 * Copyright IBM Corp. 2008 15 * 16 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 17 */ 18 19 /* This file implements emulation of the 32-bit PCI controller found in some 20 * 4xx SoCs, such as the 440EP. */ 21 22 #include "hw.h" 23 #include "ppc.h" 24 #include "ppc4xx.h" 25 #include "pci.h" 26 #include "pci_host.h" 27 #include "exec-memory.h" 28 29 #undef DEBUG 30 #ifdef DEBUG 31 #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0) 32 #else 33 #define DPRINTF(fmt, ...) 34 #endif /* DEBUG */ 35 36 struct PCIMasterMap { 37 uint32_t la; 38 uint32_t ma; 39 uint32_t pcila; 40 uint32_t pciha; 41 }; 42 43 struct PCITargetMap { 44 uint32_t ms; 45 uint32_t la; 46 }; 47 48 #define PPC4xx_PCI_HOST_BRIDGE(obj) \ 49 OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE) 50 51 #define PPC4xx_PCI_NR_PMMS 3 52 #define PPC4xx_PCI_NR_PTMS 2 53 54 struct PPC4xxPCIState { 55 PCIHostState pci_state; 56 57 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS]; 58 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS]; 59 qemu_irq irq[4]; 60 61 MemoryRegion container; 62 MemoryRegion iomem; 63 }; 64 typedef struct PPC4xxPCIState PPC4xxPCIState; 65 66 #define PCIC0_CFGADDR 0x0 67 #define PCIC0_CFGDATA 0x4 68 69 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to 70 * PCI accesses. */ 71 #define PCIL0_PMM0LA 0x0 72 #define PCIL0_PMM0MA 0x4 73 #define PCIL0_PMM0PCILA 0x8 74 #define PCIL0_PMM0PCIHA 0xc 75 #define PCIL0_PMM1LA 0x10 76 #define PCIL0_PMM1MA 0x14 77 #define PCIL0_PMM1PCILA 0x18 78 #define PCIL0_PMM1PCIHA 0x1c 79 #define PCIL0_PMM2LA 0x20 80 #define PCIL0_PMM2MA 0x24 81 #define PCIL0_PMM2PCILA 0x28 82 #define PCIL0_PMM2PCIHA 0x2c 83 84 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to 85 * PLB accesses. */ 86 #define PCIL0_PTM1MS 0x30 87 #define PCIL0_PTM1LA 0x34 88 #define PCIL0_PTM2MS 0x38 89 #define PCIL0_PTM2LA 0x3c 90 #define PCI_REG_BASE 0x800000 91 #define PCI_REG_SIZE 0x40 92 93 #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE) 94 95 static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr, 96 unsigned size) 97 { 98 PPC4xxPCIState *ppc4xx_pci = opaque; 99 100 return ppc4xx_pci->pci_state.config_reg; 101 } 102 103 static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr, 104 uint64_t value, unsigned size) 105 { 106 PPC4xxPCIState *ppc4xx_pci = opaque; 107 108 ppc4xx_pci->pci_state.config_reg = value & ~0x3; 109 } 110 111 static const MemoryRegionOps pci4xx_cfgaddr_ops = { 112 .read = pci4xx_cfgaddr_read, 113 .write = pci4xx_cfgaddr_write, 114 .endianness = DEVICE_LITTLE_ENDIAN, 115 }; 116 117 static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, 118 uint64_t value, unsigned size) 119 { 120 struct PPC4xxPCIState *pci = opaque; 121 122 /* We ignore all target attempts at PCI configuration, effectively 123 * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ 124 125 switch (offset) { 126 case PCIL0_PMM0LA: 127 pci->pmm[0].la = value; 128 break; 129 case PCIL0_PMM0MA: 130 pci->pmm[0].ma = value; 131 break; 132 case PCIL0_PMM0PCIHA: 133 pci->pmm[0].pciha = value; 134 break; 135 case PCIL0_PMM0PCILA: 136 pci->pmm[0].pcila = value; 137 break; 138 139 case PCIL0_PMM1LA: 140 pci->pmm[1].la = value; 141 break; 142 case PCIL0_PMM1MA: 143 pci->pmm[1].ma = value; 144 break; 145 case PCIL0_PMM1PCIHA: 146 pci->pmm[1].pciha = value; 147 break; 148 case PCIL0_PMM1PCILA: 149 pci->pmm[1].pcila = value; 150 break; 151 152 case PCIL0_PMM2LA: 153 pci->pmm[2].la = value; 154 break; 155 case PCIL0_PMM2MA: 156 pci->pmm[2].ma = value; 157 break; 158 case PCIL0_PMM2PCIHA: 159 pci->pmm[2].pciha = value; 160 break; 161 case PCIL0_PMM2PCILA: 162 pci->pmm[2].pcila = value; 163 break; 164 165 case PCIL0_PTM1MS: 166 pci->ptm[0].ms = value; 167 break; 168 case PCIL0_PTM1LA: 169 pci->ptm[0].la = value; 170 break; 171 case PCIL0_PTM2MS: 172 pci->ptm[1].ms = value; 173 break; 174 case PCIL0_PTM2LA: 175 pci->ptm[1].la = value; 176 break; 177 178 default: 179 printf("%s: unhandled PCI internal register 0x%lx\n", __func__, 180 (unsigned long)offset); 181 break; 182 } 183 } 184 185 static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset, 186 unsigned size) 187 { 188 struct PPC4xxPCIState *pci = opaque; 189 uint32_t value; 190 191 switch (offset) { 192 case PCIL0_PMM0LA: 193 value = pci->pmm[0].la; 194 break; 195 case PCIL0_PMM0MA: 196 value = pci->pmm[0].ma; 197 break; 198 case PCIL0_PMM0PCIHA: 199 value = pci->pmm[0].pciha; 200 break; 201 case PCIL0_PMM0PCILA: 202 value = pci->pmm[0].pcila; 203 break; 204 205 case PCIL0_PMM1LA: 206 value = pci->pmm[1].la; 207 break; 208 case PCIL0_PMM1MA: 209 value = pci->pmm[1].ma; 210 break; 211 case PCIL0_PMM1PCIHA: 212 value = pci->pmm[1].pciha; 213 break; 214 case PCIL0_PMM1PCILA: 215 value = pci->pmm[1].pcila; 216 break; 217 218 case PCIL0_PMM2LA: 219 value = pci->pmm[2].la; 220 break; 221 case PCIL0_PMM2MA: 222 value = pci->pmm[2].ma; 223 break; 224 case PCIL0_PMM2PCIHA: 225 value = pci->pmm[2].pciha; 226 break; 227 case PCIL0_PMM2PCILA: 228 value = pci->pmm[2].pcila; 229 break; 230 231 case PCIL0_PTM1MS: 232 value = pci->ptm[0].ms; 233 break; 234 case PCIL0_PTM1LA: 235 value = pci->ptm[0].la; 236 break; 237 case PCIL0_PTM2MS: 238 value = pci->ptm[1].ms; 239 break; 240 case PCIL0_PTM2LA: 241 value = pci->ptm[1].la; 242 break; 243 244 default: 245 printf("%s: invalid PCI internal register 0x%lx\n", __func__, 246 (unsigned long)offset); 247 value = 0; 248 } 249 250 return value; 251 } 252 253 static const MemoryRegionOps pci_reg_ops = { 254 .read = ppc4xx_pci_reg_read4, 255 .write = ppc4xx_pci_reg_write4, 256 .endianness = DEVICE_LITTLE_ENDIAN, 257 }; 258 259 static void ppc4xx_pci_reset(void *opaque) 260 { 261 struct PPC4xxPCIState *pci = opaque; 262 263 memset(pci->pmm, 0, sizeof(pci->pmm)); 264 memset(pci->ptm, 0, sizeof(pci->ptm)); 265 } 266 267 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This 268 * may need further refactoring for other boards. */ 269 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) 270 { 271 int slot = pci_dev->devfn >> 3; 272 273 DPRINTF("%s: devfn %x irq %d -> %d\n", __func__, 274 pci_dev->devfn, irq_num, slot); 275 276 return slot - 1; 277 } 278 279 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) 280 { 281 qemu_irq *pci_irqs = opaque; 282 283 DPRINTF("%s: PCI irq %d\n", __func__, irq_num); 284 if (irq_num < 0) { 285 fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num); 286 return; 287 } 288 qemu_set_irq(pci_irqs[irq_num], level); 289 } 290 291 static const VMStateDescription vmstate_pci_master_map = { 292 .name = "pci_master_map", 293 .version_id = 0, 294 .minimum_version_id = 0, 295 .minimum_version_id_old = 0, 296 .fields = (VMStateField[]) { 297 VMSTATE_UINT32(la, struct PCIMasterMap), 298 VMSTATE_UINT32(ma, struct PCIMasterMap), 299 VMSTATE_UINT32(pcila, struct PCIMasterMap), 300 VMSTATE_UINT32(pciha, struct PCIMasterMap), 301 VMSTATE_END_OF_LIST() 302 } 303 }; 304 305 static const VMStateDescription vmstate_pci_target_map = { 306 .name = "pci_target_map", 307 .version_id = 0, 308 .minimum_version_id = 0, 309 .minimum_version_id_old = 0, 310 .fields = (VMStateField[]) { 311 VMSTATE_UINT32(ms, struct PCITargetMap), 312 VMSTATE_UINT32(la, struct PCITargetMap), 313 VMSTATE_END_OF_LIST() 314 } 315 }; 316 317 static const VMStateDescription vmstate_ppc4xx_pci = { 318 .name = "ppc4xx_pci", 319 .version_id = 1, 320 .minimum_version_id = 1, 321 .minimum_version_id_old = 1, 322 .fields = (VMStateField[]) { 323 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1, 324 vmstate_pci_master_map, 325 struct PCIMasterMap), 326 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1, 327 vmstate_pci_target_map, 328 struct PCITargetMap), 329 VMSTATE_END_OF_LIST() 330 } 331 }; 332 333 /* XXX Interrupt acknowledge cycles not supported. */ 334 static int ppc4xx_pcihost_initfn(SysBusDevice *dev) 335 { 336 PPC4xxPCIState *s; 337 PCIHostState *h; 338 PCIBus *b; 339 int i; 340 341 h = FROM_SYSBUS(PCIHostState, dev); 342 s = PPC4xx_PCI_HOST_BRIDGE(dev); 343 344 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 345 sysbus_init_irq(dev, &s->irq[i]); 346 } 347 348 b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq, 349 ppc4xx_pci_map_irq, s->irq, get_system_memory(), 350 get_system_io(), 0, 4); 351 h->bus = b; 352 353 pci_create_simple(b, 0, "ppc4xx-host-bridge"); 354 355 /* XXX split into 2 memory regions, one for config space, one for regs */ 356 memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE); 357 memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h, 358 "pci-conf-idx", 4); 359 memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, 360 "pci-conf-data", 4); 361 memory_region_init_io(&s->iomem, &pci_reg_ops, s, 362 "pci.reg", PCI_REG_SIZE); 363 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem); 364 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem); 365 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem); 366 sysbus_init_mmio(dev, &s->container); 367 qemu_register_reset(ppc4xx_pci_reset, s); 368 369 return 0; 370 } 371 372 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data) 373 { 374 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 375 DeviceClass *dc = DEVICE_CLASS(klass); 376 377 dc->desc = "Host bridge"; 378 k->vendor_id = PCI_VENDOR_ID_IBM; 379 k->device_id = PCI_DEVICE_ID_IBM_440GX; 380 k->class_id = PCI_CLASS_BRIDGE_OTHER; 381 } 382 383 static const TypeInfo ppc4xx_host_bridge_info = { 384 .name = "ppc4xx-host-bridge", 385 .parent = TYPE_PCI_DEVICE, 386 .instance_size = sizeof(PCIDevice), 387 .class_init = ppc4xx_host_bridge_class_init, 388 }; 389 390 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data) 391 { 392 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 393 DeviceClass *dc = DEVICE_CLASS(klass); 394 395 k->init = ppc4xx_pcihost_initfn; 396 dc->vmsd = &vmstate_ppc4xx_pci; 397 } 398 399 static const TypeInfo ppc4xx_pcihost_info = { 400 .name = TYPE_PPC4xx_PCI_HOST_BRIDGE, 401 .parent = TYPE_SYS_BUS_DEVICE, 402 .instance_size = sizeof(PPC4xxPCIState), 403 .class_init = ppc4xx_pcihost_class_init, 404 }; 405 406 static void ppc4xx_pci_register_types(void) 407 { 408 type_register_static(&ppc4xx_pcihost_info); 409 type_register_static(&ppc4xx_host_bridge_info); 410 } 411 412 type_init(ppc4xx_pci_register_types) 413