1 /* 2 * QEMU PowerPC PowerNV Proxy PHB model 3 * 4 * Copyright (c) 2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/visitor.h" 13 #include "qapi/error.h" 14 #include "hw/pci-host/pnv_phb.h" 15 #include "hw/pci-host/pnv_phb3.h" 16 #include "hw/pci-host/pnv_phb4.h" 17 #include "hw/ppc/pnv.h" 18 #include "hw/qdev-properties.h" 19 #include "qom/object.h" 20 #include "sysemu/sysemu.h" 21 22 23 /* 24 * Set the QOM parent of an object child. If the device state 25 * associated with the child has an id, use it as QOM id. Otherwise 26 * use object_typename[index] as QOM id. 27 */ 28 static void pnv_parent_qom_fixup(Object *parent, Object *child, int index) 29 { 30 g_autofree char *default_id = 31 g_strdup_printf("%s[%d]", object_get_typename(child), index); 32 const char *dev_id = DEVICE(child)->id; 33 34 if (child->parent == parent) { 35 return; 36 } 37 38 object_ref(child); 39 object_unparent(child); 40 object_property_add_child(parent, dev_id ? dev_id : default_id, child); 41 object_unref(child); 42 } 43 44 static void pnv_parent_bus_fixup(DeviceState *parent, DeviceState *child, 45 Error **errp) 46 { 47 BusState *parent_bus = qdev_get_parent_bus(parent); 48 49 if (!qdev_set_parent_bus(child, parent_bus, errp)) { 50 return; 51 } 52 } 53 54 /* 55 * Attach a root port device. 56 * 57 * 'index' will be used both as a PCIE slot value and to calculate 58 * QOM id. 'chip_id' is going to be used as PCIE chassis for the 59 * root port. 60 */ 61 static void pnv_phb_attach_root_port(PCIHostState *pci) 62 { 63 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT); 64 const char *dev_id = DEVICE(root)->id; 65 g_autofree char *default_id = NULL; 66 int index; 67 68 index = object_property_get_int(OBJECT(pci->bus), "phb-id", &error_fatal); 69 default_id = g_strdup_printf("%s[%d]", TYPE_PNV_PHB_ROOT_PORT, index); 70 71 object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id, 72 OBJECT(root)); 73 74 pci_realize_and_unref(root, pci->bus, &error_fatal); 75 } 76 77 /* 78 * User created devices won't have the initial setup that default 79 * devices have. This setup consists of assigning a parent device 80 * (chip for PHB3, PEC for PHB4/5) that will be the QOM/bus parent 81 * of the PHB. 82 */ 83 static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp) 84 { 85 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 86 PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); 87 Object *parent = NULL; 88 89 if (!chip) { 90 error_setg(errp, "invalid chip id: %d", phb->chip_id); 91 return false; 92 } 93 94 parent = pnv_chip_add_phb(chip, phb, errp); 95 if (!parent) { 96 return false; 97 } 98 99 /* 100 * Reparent user created devices to the chip to build 101 * correctly the device tree. pnv_xscom_dt() needs every 102 * PHB to be a child of the chip to build the DT correctly. 103 */ 104 pnv_parent_qom_fixup(parent, OBJECT(phb), phb->phb_id); 105 pnv_parent_bus_fixup(DEVICE(chip), DEVICE(phb), errp); 106 107 return true; 108 } 109 110 static void pnv_phb_realize(DeviceState *dev, Error **errp) 111 { 112 PnvPHB *phb = PNV_PHB(dev); 113 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 114 g_autofree char *phb_typename = NULL; 115 116 if (!phb->version) { 117 error_setg(errp, "version not specified"); 118 return; 119 } 120 121 switch (phb->version) { 122 case 3: 123 phb_typename = g_strdup(TYPE_PNV_PHB3); 124 break; 125 case 4: 126 phb_typename = g_strdup(TYPE_PNV_PHB4); 127 break; 128 case 5: 129 phb_typename = g_strdup(TYPE_PNV_PHB5); 130 break; 131 default: 132 g_assert_not_reached(); 133 } 134 135 phb->backend = object_new(phb_typename); 136 object_property_add_child(OBJECT(dev), "phb-backend", phb->backend); 137 138 /* Passthrough child device properties to the proxy device */ 139 object_property_set_uint(phb->backend, "index", phb->phb_id, errp); 140 object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp); 141 object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp); 142 143 /* 144 * Handle user created devices. User devices will not have a 145 * pointer to a chip (PHB3) and a PEC (PHB4/5). 146 */ 147 if (!phb->chip && !phb->pec) { 148 if (!pnv_phb_user_device_init(phb, errp)) { 149 return; 150 } 151 } 152 153 if (phb->version == 3) { 154 object_property_set_link(phb->backend, "chip", 155 OBJECT(phb->chip), errp); 156 } else { 157 object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp); 158 } 159 160 if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) { 161 return; 162 } 163 164 if (phb->version == 3) { 165 pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend)); 166 } else { 167 pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend)); 168 } 169 170 if (!defaults_enabled()) { 171 return; 172 } 173 174 pnv_phb_attach_root_port(pci); 175 } 176 177 static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, 178 PCIBus *rootbus) 179 { 180 PnvPHB *phb = PNV_PHB(host_bridge); 181 182 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", 183 phb->chip_id, phb->phb_id); 184 return phb->bus_path; 185 } 186 187 static Property pnv_phb_properties[] = { 188 DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0), 189 DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0), 190 DEFINE_PROP_UINT32("version", PnvPHB, version, 0), 191 192 DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *), 193 194 DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC, 195 PnvPhb4PecState *), 196 197 DEFINE_PROP_END_OF_LIST(), 198 }; 199 200 static void pnv_phb_class_init(ObjectClass *klass, void *data) 201 { 202 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 203 DeviceClass *dc = DEVICE_CLASS(klass); 204 205 hc->root_bus_path = pnv_phb_root_bus_path; 206 dc->realize = pnv_phb_realize; 207 device_class_set_props(dc, pnv_phb_properties); 208 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 209 dc->user_creatable = true; 210 } 211 212 static void pnv_phb_root_port_reset(DeviceState *dev) 213 { 214 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 215 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); 216 PCIDevice *d = PCI_DEVICE(dev); 217 uint8_t *conf = d->config; 218 219 rpc->parent_reset(dev); 220 221 if (phb_rp->version == 3) { 222 return; 223 } 224 225 /* PHB4 and later requires these extra reset steps */ 226 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 227 PCI_IO_RANGE_MASK & 0xff); 228 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 229 PCI_IO_RANGE_MASK & 0xff); 230 pci_set_word(conf + PCI_MEMORY_BASE, 0); 231 pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0); 232 pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1); 233 pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); 234 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ 235 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); 236 pci_config_set_interrupt_pin(conf, 0); 237 } 238 239 static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) 240 { 241 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 242 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); 243 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev)); 244 PCIDevice *pci = PCI_DEVICE(dev); 245 uint16_t device_id = 0; 246 Error *local_err = NULL; 247 int chip_id, index; 248 249 chip_id = object_property_get_int(OBJECT(bus), "chip-id", &error_fatal); 250 index = object_property_get_int(OBJECT(bus), "phb-id", &error_fatal); 251 252 /* Set unique chassis/slot values for the root port */ 253 qdev_prop_set_uint8(dev, "chassis", chip_id); 254 qdev_prop_set_uint16(dev, "slot", index); 255 256 rpc->parent_realize(dev, &local_err); 257 if (local_err) { 258 error_propagate(errp, local_err); 259 return; 260 } 261 262 switch (phb_rp->version) { 263 case 3: 264 device_id = PNV_PHB3_DEVICE_ID; 265 break; 266 case 4: 267 device_id = PNV_PHB4_DEVICE_ID; 268 break; 269 case 5: 270 device_id = PNV_PHB5_DEVICE_ID; 271 break; 272 default: 273 g_assert_not_reached(); 274 } 275 276 pci_config_set_device_id(pci->config, device_id); 277 pci_config_set_interrupt_pin(pci->config, 0); 278 } 279 280 static Property pnv_phb_root_port_properties[] = { 281 DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0), 282 283 DEFINE_PROP_END_OF_LIST(), 284 }; 285 286 static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) 287 { 288 DeviceClass *dc = DEVICE_CLASS(klass); 289 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 290 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); 291 292 dc->desc = "IBM PHB PCIE Root Port"; 293 294 device_class_set_props(dc, pnv_phb_root_port_properties); 295 device_class_set_parent_realize(dc, pnv_phb_root_port_realize, 296 &rpc->parent_realize); 297 device_class_set_parent_reset(dc, pnv_phb_root_port_reset, 298 &rpc->parent_reset); 299 dc->reset = &pnv_phb_root_port_reset; 300 dc->user_creatable = true; 301 302 k->vendor_id = PCI_VENDOR_ID_IBM; 303 /* device_id will be written during realize() */ 304 k->device_id = 0; 305 k->revision = 0; 306 307 rpc->exp_offset = 0x48; 308 rpc->aer_offset = 0x100; 309 } 310 311 static const TypeInfo pnv_phb_type_info = { 312 .name = TYPE_PNV_PHB, 313 .parent = TYPE_PCIE_HOST_BRIDGE, 314 .instance_size = sizeof(PnvPHB), 315 .class_init = pnv_phb_class_init, 316 }; 317 318 static const TypeInfo pnv_phb_root_port_info = { 319 .name = TYPE_PNV_PHB_ROOT_PORT, 320 .parent = TYPE_PCIE_ROOT_PORT, 321 .instance_size = sizeof(PnvPHBRootPort), 322 .class_init = pnv_phb_root_port_class_init, 323 }; 324 325 static void pnv_phb_register_types(void) 326 { 327 type_register_static(&pnv_phb_type_info); 328 type_register_static(&pnv_phb_root_port_info); 329 } 330 331 type_init(pnv_phb_register_types) 332