1 /* 2 * QEMU PowerPC PowerNV Proxy PHB model 3 * 4 * Copyright (c) 2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/visitor.h" 13 #include "qapi/error.h" 14 #include "hw/pci-host/pnv_phb.h" 15 #include "hw/pci-host/pnv_phb3.h" 16 #include "hw/pci-host/pnv_phb4.h" 17 #include "hw/ppc/pnv.h" 18 #include "hw/qdev-properties.h" 19 #include "qom/object.h" 20 21 /* 22 * Attach a root port device. 23 * 24 * 'index' will be used both as a PCIE slot value and to calculate 25 * QOM id. 'chip_id' is going to be used as PCIE chassis for the 26 * root port. 27 */ 28 static void pnv_phb_attach_root_port(PCIHostState *pci) 29 { 30 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT); 31 const char *dev_id = DEVICE(root)->id; 32 g_autofree char *default_id = NULL; 33 int index; 34 35 index = object_property_get_int(OBJECT(pci->bus), "phb-id", &error_fatal); 36 default_id = g_strdup_printf("%s[%d]", TYPE_PNV_PHB_ROOT_PORT, index); 37 38 object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id, 39 OBJECT(root)); 40 41 pci_realize_and_unref(root, pci->bus, &error_fatal); 42 } 43 44 static void pnv_phb_realize(DeviceState *dev, Error **errp) 45 { 46 PnvPHB *phb = PNV_PHB(dev); 47 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 48 g_autofree char *phb_typename = NULL; 49 50 if (!phb->version) { 51 error_setg(errp, "version not specified"); 52 return; 53 } 54 55 switch (phb->version) { 56 case 3: 57 phb_typename = g_strdup(TYPE_PNV_PHB3); 58 break; 59 case 4: 60 phb_typename = g_strdup(TYPE_PNV_PHB4); 61 break; 62 case 5: 63 phb_typename = g_strdup(TYPE_PNV_PHB5); 64 break; 65 default: 66 g_assert_not_reached(); 67 } 68 69 phb->backend = object_new(phb_typename); 70 object_property_add_child(OBJECT(dev), "phb-backend", phb->backend); 71 72 /* Passthrough child device properties to the proxy device */ 73 object_property_set_uint(phb->backend, "index", phb->phb_id, errp); 74 object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp); 75 object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp); 76 77 if (phb->version == 3) { 78 object_property_set_link(phb->backend, "chip", 79 OBJECT(phb->chip), errp); 80 } else { 81 object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp); 82 } 83 84 if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) { 85 return; 86 } 87 88 if (phb->version == 3) { 89 pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend)); 90 } else { 91 pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend)); 92 } 93 94 pnv_phb_attach_root_port(pci); 95 } 96 97 static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, 98 PCIBus *rootbus) 99 { 100 PnvPHB *phb = PNV_PHB(host_bridge); 101 102 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", 103 phb->chip_id, phb->phb_id); 104 return phb->bus_path; 105 } 106 107 static Property pnv_phb_properties[] = { 108 DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0), 109 DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0), 110 DEFINE_PROP_UINT32("version", PnvPHB, version, 0), 111 112 DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *), 113 114 DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC, 115 PnvPhb4PecState *), 116 117 DEFINE_PROP_END_OF_LIST(), 118 }; 119 120 static void pnv_phb_class_init(ObjectClass *klass, void *data) 121 { 122 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 123 DeviceClass *dc = DEVICE_CLASS(klass); 124 125 hc->root_bus_path = pnv_phb_root_bus_path; 126 dc->realize = pnv_phb_realize; 127 device_class_set_props(dc, pnv_phb_properties); 128 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 129 dc->user_creatable = false; 130 } 131 132 static void pnv_phb_root_port_reset(DeviceState *dev) 133 { 134 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 135 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); 136 PCIDevice *d = PCI_DEVICE(dev); 137 uint8_t *conf = d->config; 138 139 rpc->parent_reset(dev); 140 141 if (phb_rp->version == 3) { 142 return; 143 } 144 145 /* PHB4 and later requires these extra reset steps */ 146 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 147 PCI_IO_RANGE_MASK & 0xff); 148 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 149 PCI_IO_RANGE_MASK & 0xff); 150 pci_set_word(conf + PCI_MEMORY_BASE, 0); 151 pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0); 152 pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1); 153 pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); 154 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ 155 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); 156 pci_config_set_interrupt_pin(conf, 0); 157 } 158 159 static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) 160 { 161 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 162 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); 163 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev)); 164 PCIDevice *pci = PCI_DEVICE(dev); 165 uint16_t device_id = 0; 166 Error *local_err = NULL; 167 int chip_id, index; 168 169 chip_id = object_property_get_int(OBJECT(bus), "chip-id", &error_fatal); 170 index = object_property_get_int(OBJECT(bus), "phb-id", &error_fatal); 171 172 /* Set unique chassis/slot values for the root port */ 173 qdev_prop_set_uint8(dev, "chassis", chip_id); 174 qdev_prop_set_uint16(dev, "slot", index); 175 176 rpc->parent_realize(dev, &local_err); 177 if (local_err) { 178 error_propagate(errp, local_err); 179 return; 180 } 181 182 switch (phb_rp->version) { 183 case 3: 184 device_id = PNV_PHB3_DEVICE_ID; 185 break; 186 case 4: 187 device_id = PNV_PHB4_DEVICE_ID; 188 break; 189 case 5: 190 device_id = PNV_PHB5_DEVICE_ID; 191 break; 192 default: 193 g_assert_not_reached(); 194 } 195 196 pci_config_set_device_id(pci->config, device_id); 197 pci_config_set_interrupt_pin(pci->config, 0); 198 } 199 200 static Property pnv_phb_root_port_properties[] = { 201 DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0), 202 203 DEFINE_PROP_END_OF_LIST(), 204 }; 205 206 static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) 207 { 208 DeviceClass *dc = DEVICE_CLASS(klass); 209 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 210 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); 211 212 dc->desc = "IBM PHB PCIE Root Port"; 213 214 device_class_set_props(dc, pnv_phb_root_port_properties); 215 device_class_set_parent_realize(dc, pnv_phb_root_port_realize, 216 &rpc->parent_realize); 217 device_class_set_parent_reset(dc, pnv_phb_root_port_reset, 218 &rpc->parent_reset); 219 dc->reset = &pnv_phb_root_port_reset; 220 dc->user_creatable = false; 221 222 k->vendor_id = PCI_VENDOR_ID_IBM; 223 /* device_id will be written during realize() */ 224 k->device_id = 0; 225 k->revision = 0; 226 227 rpc->exp_offset = 0x48; 228 rpc->aer_offset = 0x100; 229 } 230 231 static const TypeInfo pnv_phb_type_info = { 232 .name = TYPE_PNV_PHB, 233 .parent = TYPE_PCIE_HOST_BRIDGE, 234 .instance_size = sizeof(PnvPHB), 235 .class_init = pnv_phb_class_init, 236 }; 237 238 static const TypeInfo pnv_phb_root_port_info = { 239 .name = TYPE_PNV_PHB_ROOT_PORT, 240 .parent = TYPE_PCIE_ROOT_PORT, 241 .instance_size = sizeof(PnvPHBRootPort), 242 .class_init = pnv_phb_root_port_class_init, 243 }; 244 245 static void pnv_phb_register_types(void) 246 { 247 type_register_static(&pnv_phb_type_info); 248 type_register_static(&pnv_phb_root_port_info); 249 } 250 251 type_init(pnv_phb_register_types) 252