1 /* 2 * QEMU PowerPC PowerNV Proxy PHB model 3 * 4 * Copyright (c) 2022, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qapi/visitor.h" 13 #include "qapi/error.h" 14 #include "hw/pci-host/pnv_phb.h" 15 #include "hw/pci-host/pnv_phb3.h" 16 #include "hw/pci-host/pnv_phb4.h" 17 #include "hw/ppc/pnv.h" 18 #include "hw/qdev-properties.h" 19 #include "qom/object.h" 20 #include "sysemu/sysemu.h" 21 22 23 /* 24 * Set the QOM parent and parent bus of an object child. If the device 25 * state associated with the child has an id, use it as QOM id. 26 * Otherwise use object_typename[index] as QOM id. 27 * 28 * This helper does both operations at the same time because seting 29 * a new QOM child will erase the bus parent of the device. This happens 30 * because object_unparent() will call object_property_del_child(), 31 * which in turn calls the property release callback prop->release if 32 * it's defined. In our case this callback is set to 33 * object_finalize_child_property(), which was assigned during the 34 * first object_property_add_child() call. This callback will end up 35 * calling device_unparent(), and this function removes the device 36 * from its parent bus. 37 * 38 * The QOM and parent bus to be set aren´t necessarily related, so 39 * let's receive both as arguments. 40 */ 41 static bool pnv_parent_fixup(Object *parent, BusState *parent_bus, 42 Object *child, int index, 43 Error **errp) 44 { 45 g_autofree char *default_id = 46 g_strdup_printf("%s[%d]", object_get_typename(child), index); 47 const char *dev_id = DEVICE(child)->id; 48 49 if (child->parent == parent) { 50 return true; 51 } 52 53 object_ref(child); 54 object_unparent(child); 55 object_property_add_child(parent, dev_id ? dev_id : default_id, child); 56 object_unref(child); 57 58 if (!qdev_set_parent_bus(DEVICE(child), parent_bus, errp)) { 59 return false; 60 } 61 62 return true; 63 } 64 65 /* 66 * Attach a root port device. 67 * 68 * 'index' will be used both as a PCIE slot value and to calculate 69 * QOM id. 'chip_id' is going to be used as PCIE chassis for the 70 * root port. 71 */ 72 static void pnv_phb_attach_root_port(PCIHostState *pci) 73 { 74 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), TYPE_PNV_PHB_ROOT_PORT); 75 const char *dev_id = DEVICE(root)->id; 76 g_autofree char *default_id = NULL; 77 int index; 78 79 index = object_property_get_int(OBJECT(pci->bus), "phb-id", &error_fatal); 80 default_id = g_strdup_printf("%s[%d]", TYPE_PNV_PHB_ROOT_PORT, index); 81 82 object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id, 83 OBJECT(root)); 84 85 pci_realize_and_unref(root, pci->bus, &error_fatal); 86 } 87 88 /* 89 * User created devices won't have the initial setup that default 90 * devices have. This setup consists of assigning a parent device 91 * (chip for PHB3, PEC for PHB4/5) that will be the QOM/bus parent 92 * of the PHB. 93 */ 94 static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp) 95 { 96 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 97 PnvChip *chip = pnv_get_chip(pnv, phb->chip_id); 98 Object *parent = NULL; 99 100 if (!chip) { 101 error_setg(errp, "invalid chip id: %d", phb->chip_id); 102 return false; 103 } 104 105 parent = pnv_chip_add_phb(chip, phb, errp); 106 if (!parent) { 107 return false; 108 } 109 110 /* 111 * Reparent user created devices to the chip to build 112 * correctly the device tree. pnv_xscom_dt() needs every 113 * PHB to be a child of the chip to build the DT correctly. 114 */ 115 if (!pnv_parent_fixup(parent, qdev_get_parent_bus(DEVICE(chip)), 116 OBJECT(phb), phb->phb_id, errp)) { 117 return false; 118 } 119 120 return true; 121 } 122 123 static void pnv_phb_realize(DeviceState *dev, Error **errp) 124 { 125 PnvPHB *phb = PNV_PHB(dev); 126 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 127 g_autofree char *phb_typename = NULL; 128 129 if (!phb->version) { 130 error_setg(errp, "version not specified"); 131 return; 132 } 133 134 switch (phb->version) { 135 case 3: 136 phb_typename = g_strdup(TYPE_PNV_PHB3); 137 break; 138 case 4: 139 phb_typename = g_strdup(TYPE_PNV_PHB4); 140 break; 141 case 5: 142 phb_typename = g_strdup(TYPE_PNV_PHB5); 143 break; 144 default: 145 g_assert_not_reached(); 146 } 147 148 phb->backend = object_new(phb_typename); 149 object_property_add_child(OBJECT(dev), "phb-backend", phb->backend); 150 151 /* Passthrough child device properties to the proxy device */ 152 object_property_set_uint(phb->backend, "index", phb->phb_id, errp); 153 object_property_set_uint(phb->backend, "chip-id", phb->chip_id, errp); 154 object_property_set_link(phb->backend, "phb-base", OBJECT(phb), errp); 155 156 /* 157 * Handle user created devices. User devices will not have a 158 * pointer to a chip (PHB3) and a PEC (PHB4/5). 159 */ 160 if (!phb->chip && !phb->pec) { 161 if (!pnv_phb_user_device_init(phb, errp)) { 162 return; 163 } 164 } 165 166 if (phb->version == 3) { 167 object_property_set_link(phb->backend, "chip", 168 OBJECT(phb->chip), errp); 169 } else { 170 object_property_set_link(phb->backend, "pec", OBJECT(phb->pec), errp); 171 } 172 173 if (!qdev_realize(DEVICE(phb->backend), NULL, errp)) { 174 return; 175 } 176 177 if (phb->version == 3) { 178 pnv_phb3_bus_init(dev, PNV_PHB3(phb->backend)); 179 } else { 180 pnv_phb4_bus_init(dev, PNV_PHB4(phb->backend)); 181 } 182 183 if (!defaults_enabled()) { 184 return; 185 } 186 187 pnv_phb_attach_root_port(pci); 188 } 189 190 static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, 191 PCIBus *rootbus) 192 { 193 PnvPHB *phb = PNV_PHB(host_bridge); 194 195 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", 196 phb->chip_id, phb->phb_id); 197 return phb->bus_path; 198 } 199 200 static Property pnv_phb_properties[] = { 201 DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0), 202 DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0), 203 DEFINE_PROP_UINT32("version", PnvPHB, version, 0), 204 205 DEFINE_PROP_LINK("chip", PnvPHB, chip, TYPE_PNV_CHIP, PnvChip *), 206 207 DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC, 208 PnvPhb4PecState *), 209 210 DEFINE_PROP_END_OF_LIST(), 211 }; 212 213 static void pnv_phb_class_init(ObjectClass *klass, void *data) 214 { 215 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 216 DeviceClass *dc = DEVICE_CLASS(klass); 217 218 hc->root_bus_path = pnv_phb_root_bus_path; 219 dc->realize = pnv_phb_realize; 220 device_class_set_props(dc, pnv_phb_properties); 221 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 222 dc->user_creatable = true; 223 } 224 225 static void pnv_phb_root_port_reset(DeviceState *dev) 226 { 227 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 228 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); 229 PCIDevice *d = PCI_DEVICE(dev); 230 uint8_t *conf = d->config; 231 232 rpc->parent_reset(dev); 233 234 if (phb_rp->version == 3) { 235 return; 236 } 237 238 /* PHB4 and later requires these extra reset steps */ 239 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 240 PCI_IO_RANGE_MASK & 0xff); 241 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 242 PCI_IO_RANGE_MASK & 0xff); 243 pci_set_word(conf + PCI_MEMORY_BASE, 0); 244 pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0); 245 pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1); 246 pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); 247 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ 248 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); 249 pci_config_set_interrupt_pin(conf, 0); 250 } 251 252 static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) 253 { 254 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 255 PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev); 256 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(dev)); 257 PCIDevice *pci = PCI_DEVICE(dev); 258 uint16_t device_id = 0; 259 Error *local_err = NULL; 260 int chip_id, index; 261 262 chip_id = object_property_get_int(OBJECT(bus), "chip-id", &error_fatal); 263 index = object_property_get_int(OBJECT(bus), "phb-id", &error_fatal); 264 265 /* Set unique chassis/slot values for the root port */ 266 qdev_prop_set_uint8(dev, "chassis", chip_id); 267 qdev_prop_set_uint16(dev, "slot", index); 268 269 rpc->parent_realize(dev, &local_err); 270 if (local_err) { 271 error_propagate(errp, local_err); 272 return; 273 } 274 275 switch (phb_rp->version) { 276 case 3: 277 device_id = PNV_PHB3_DEVICE_ID; 278 break; 279 case 4: 280 device_id = PNV_PHB4_DEVICE_ID; 281 break; 282 case 5: 283 device_id = PNV_PHB5_DEVICE_ID; 284 break; 285 default: 286 g_assert_not_reached(); 287 } 288 289 pci_config_set_device_id(pci->config, device_id); 290 pci_config_set_interrupt_pin(pci->config, 0); 291 } 292 293 static Property pnv_phb_root_port_properties[] = { 294 DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0), 295 296 DEFINE_PROP_END_OF_LIST(), 297 }; 298 299 static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) 300 { 301 DeviceClass *dc = DEVICE_CLASS(klass); 302 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 303 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); 304 305 dc->desc = "IBM PHB PCIE Root Port"; 306 307 device_class_set_props(dc, pnv_phb_root_port_properties); 308 device_class_set_parent_realize(dc, pnv_phb_root_port_realize, 309 &rpc->parent_realize); 310 device_class_set_parent_reset(dc, pnv_phb_root_port_reset, 311 &rpc->parent_reset); 312 dc->reset = &pnv_phb_root_port_reset; 313 dc->user_creatable = true; 314 315 k->vendor_id = PCI_VENDOR_ID_IBM; 316 /* device_id will be written during realize() */ 317 k->device_id = 0; 318 k->revision = 0; 319 320 rpc->exp_offset = 0x48; 321 rpc->aer_offset = 0x100; 322 } 323 324 static const TypeInfo pnv_phb_type_info = { 325 .name = TYPE_PNV_PHB, 326 .parent = TYPE_PCIE_HOST_BRIDGE, 327 .instance_size = sizeof(PnvPHB), 328 .class_init = pnv_phb_class_init, 329 }; 330 331 static const TypeInfo pnv_phb_root_port_info = { 332 .name = TYPE_PNV_PHB_ROOT_PORT, 333 .parent = TYPE_PCIE_ROOT_PORT, 334 .instance_size = sizeof(PnvPHBRootPort), 335 .class_init = pnv_phb_root_port_class_init, 336 }; 337 338 static void pnv_phb_register_types(void) 339 { 340 type_register_static(&pnv_phb_type_info); 341 type_register_static(&pnv_phb_root_port_info); 342 } 343 344 type_init(pnv_phb_register_types) 345