1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * Designware PCIe IP block emulation 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/module.h" 24 #include "qemu/log.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pci_bridge.h" 27 #include "hw/pci/pci_host.h" 28 #include "hw/pci/pcie_port.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "hw/irq.h" 32 #include "hw/pci-host/designware.h" 33 34 #define DESIGNWARE_PCIE_PORT_LINK_CONTROL 0x710 35 #define DESIGNWARE_PCIE_PHY_DEBUG_R1 0x72C 36 #define DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP BIT(4) 37 #define DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 38 #define DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE BIT(17) 39 #define DESIGNWARE_PCIE_MSI_ADDR_LO 0x820 40 #define DESIGNWARE_PCIE_MSI_ADDR_HI 0x824 41 #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE 0x828 42 #define DESIGNWARE_PCIE_MSI_INTR0_MASK 0x82C 43 #define DESIGNWARE_PCIE_MSI_INTR0_STATUS 0x830 44 #define DESIGNWARE_PCIE_ATU_VIEWPORT 0x900 45 #define DESIGNWARE_PCIE_ATU_REGION_INBOUND BIT(31) 46 #define DESIGNWARE_PCIE_ATU_CR1 0x904 47 #define DESIGNWARE_PCIE_ATU_TYPE_MEM (0x0 << 0) 48 #define DESIGNWARE_PCIE_ATU_CR2 0x908 49 #define DESIGNWARE_PCIE_ATU_ENABLE BIT(31) 50 #define DESIGNWARE_PCIE_ATU_LOWER_BASE 0x90C 51 #define DESIGNWARE_PCIE_ATU_UPPER_BASE 0x910 52 #define DESIGNWARE_PCIE_ATU_LIMIT 0x914 53 #define DESIGNWARE_PCIE_ATU_LOWER_TARGET 0x918 54 #define DESIGNWARE_PCIE_ATU_BUS(x) (((x) >> 24) & 0xff) 55 #define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff) 56 #define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C 57 58 static void designware_pcie_root_bus_class_init(ObjectClass *klass, void *data) 59 { 60 BusClass *k = BUS_CLASS(klass); 61 62 /* 63 * Designware has only a single root complex. Enforce the limit on the 64 * parent bus 65 */ 66 k->max_dev = 1; 67 } 68 69 static DesignwarePCIEHost * 70 designware_pcie_root_to_host(DesignwarePCIERoot *root) 71 { 72 BusState *bus = qdev_get_parent_bus(DEVICE(root)); 73 return DESIGNWARE_PCIE_HOST(bus->parent); 74 } 75 76 static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, 77 unsigned size) 78 { 79 /* 80 * Attempts to read from the MSI address are undefined in 81 * the PCI specifications. For this hardware, the datasheet 82 * specifies that a read from the magic address is simply not 83 * intercepted by the MSI controller, and will go out to the 84 * AHB/AXI bus like any other PCI-device-initiated DMA read. 85 * This is not trivial to implement in QEMU, so since 86 * well-behaved guests won't ever ask a PCI device to DMA from 87 * this address we just log the missing functionality. 88 */ 89 qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); 90 return 0; 91 } 92 93 static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, 94 uint64_t val, unsigned len) 95 { 96 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque); 97 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); 98 99 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; 100 101 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { 102 qemu_set_irq(host->pci.msi, 1); 103 } 104 } 105 106 static const MemoryRegionOps designware_pci_host_msi_ops = { 107 .read = designware_pcie_root_msi_read, 108 .write = designware_pcie_root_msi_write, 109 .endianness = DEVICE_LITTLE_ENDIAN, 110 .valid = { 111 .min_access_size = 4, 112 .max_access_size = 4, 113 }, 114 }; 115 116 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root) 117 118 { 119 MemoryRegion *mem = &root->msi.iomem; 120 const uint64_t base = root->msi.base; 121 const bool enable = root->msi.intr[0].enable; 122 123 memory_region_set_address(mem, base); 124 memory_region_set_enabled(mem, enable); 125 } 126 127 static DesignwarePCIEViewport * 128 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root) 129 { 130 const unsigned int idx = root->atu_viewport & 0xF; 131 const unsigned int dir = 132 !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND); 133 return &root->viewports[dir][idx]; 134 } 135 136 static uint32_t 137 designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len) 138 { 139 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); 140 DesignwarePCIEViewport *viewport = 141 designware_pcie_root_get_current_viewport(root); 142 143 uint32_t val; 144 145 switch (address) { 146 case DESIGNWARE_PCIE_PORT_LINK_CONTROL: 147 /* 148 * Linux guest uses this register only to configure number of 149 * PCIE lane (which in our case is irrelevant) and doesn't 150 * really care about the value it reads from this register 151 */ 152 val = 0xDEADBEEF; 153 break; 154 155 case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL: 156 /* 157 * To make sure that any code in guest waiting for speed 158 * change does not time out we always report 159 * PORT_LOGIC_SPEED_CHANGE as set 160 */ 161 val = DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE; 162 break; 163 164 case DESIGNWARE_PCIE_MSI_ADDR_LO: 165 val = root->msi.base; 166 break; 167 168 case DESIGNWARE_PCIE_MSI_ADDR_HI: 169 val = root->msi.base >> 32; 170 break; 171 172 case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: 173 val = root->msi.intr[0].enable; 174 break; 175 176 case DESIGNWARE_PCIE_MSI_INTR0_MASK: 177 val = root->msi.intr[0].mask; 178 break; 179 180 case DESIGNWARE_PCIE_MSI_INTR0_STATUS: 181 val = root->msi.intr[0].status; 182 break; 183 184 case DESIGNWARE_PCIE_PHY_DEBUG_R1: 185 val = DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; 186 break; 187 188 case DESIGNWARE_PCIE_ATU_VIEWPORT: 189 val = root->atu_viewport; 190 break; 191 192 case DESIGNWARE_PCIE_ATU_LOWER_BASE: 193 val = viewport->base; 194 break; 195 196 case DESIGNWARE_PCIE_ATU_UPPER_BASE: 197 val = viewport->base >> 32; 198 break; 199 200 case DESIGNWARE_PCIE_ATU_LOWER_TARGET: 201 val = viewport->target; 202 break; 203 204 case DESIGNWARE_PCIE_ATU_UPPER_TARGET: 205 val = viewport->target >> 32; 206 break; 207 208 case DESIGNWARE_PCIE_ATU_LIMIT: 209 val = viewport->limit; 210 break; 211 212 case DESIGNWARE_PCIE_ATU_CR1: 213 case DESIGNWARE_PCIE_ATU_CR2: 214 val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / 215 sizeof(uint32_t)]; 216 break; 217 218 default: 219 val = pci_default_read_config(d, address, len); 220 break; 221 } 222 223 return val; 224 } 225 226 static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr, 227 uint64_t *val, unsigned len) 228 { 229 DesignwarePCIEViewport *viewport = opaque; 230 DesignwarePCIERoot *root = viewport->root; 231 232 const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target); 233 const uint8_t devfn = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target); 234 PCIBus *pcibus = pci_get_bus(PCI_DEVICE(root)); 235 PCIDevice *pcidev = pci_find_device(pcibus, busnum, devfn); 236 237 if (pcidev) { 238 addr &= pci_config_size(pcidev) - 1; 239 240 if (val) { 241 pci_host_config_write_common(pcidev, addr, 242 pci_config_size(pcidev), 243 *val, len); 244 } else { 245 return pci_host_config_read_common(pcidev, addr, 246 pci_config_size(pcidev), 247 len); 248 } 249 } 250 251 return UINT64_MAX; 252 } 253 254 static uint64_t designware_pcie_root_data_read(void *opaque, hwaddr addr, 255 unsigned len) 256 { 257 return designware_pcie_root_data_access(opaque, addr, NULL, len); 258 } 259 260 static void designware_pcie_root_data_write(void *opaque, hwaddr addr, 261 uint64_t val, unsigned len) 262 { 263 designware_pcie_root_data_access(opaque, addr, &val, len); 264 } 265 266 static const MemoryRegionOps designware_pci_host_conf_ops = { 267 .read = designware_pcie_root_data_read, 268 .write = designware_pcie_root_data_write, 269 .endianness = DEVICE_LITTLE_ENDIAN, 270 .valid = { 271 .min_access_size = 1, 272 .max_access_size = 4, 273 }, 274 }; 275 276 static void designware_pcie_update_viewport(DesignwarePCIERoot *root, 277 DesignwarePCIEViewport *viewport) 278 { 279 const uint64_t target = viewport->target; 280 const uint64_t base = viewport->base; 281 const uint64_t size = (uint64_t)viewport->limit - base + 1; 282 const bool enabled = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; 283 284 MemoryRegion *current, *other; 285 286 if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) { 287 current = &viewport->mem; 288 other = &viewport->cfg; 289 memory_region_set_alias_offset(current, target); 290 } else { 291 current = &viewport->cfg; 292 other = &viewport->mem; 293 } 294 295 /* 296 * An outbound viewport can be reconfigure from being MEM to CFG, 297 * to account for that we disable the "other" memory region that 298 * becomes unused due to that fact. 299 */ 300 memory_region_set_enabled(other, false); 301 if (enabled) { 302 memory_region_set_size(current, size); 303 memory_region_set_address(current, base); 304 } 305 memory_region_set_enabled(current, enabled); 306 } 307 308 static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, 309 uint32_t val, int len) 310 { 311 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); 312 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); 313 DesignwarePCIEViewport *viewport = 314 designware_pcie_root_get_current_viewport(root); 315 316 switch (address) { 317 case DESIGNWARE_PCIE_PORT_LINK_CONTROL: 318 case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL: 319 case DESIGNWARE_PCIE_PHY_DEBUG_R1: 320 /* No-op */ 321 break; 322 323 case DESIGNWARE_PCIE_MSI_ADDR_LO: 324 root->msi.base &= 0xFFFFFFFF00000000ULL; 325 root->msi.base |= val; 326 designware_pcie_root_update_msi_mapping(root); 327 break; 328 329 case DESIGNWARE_PCIE_MSI_ADDR_HI: 330 root->msi.base &= 0x00000000FFFFFFFFULL; 331 root->msi.base |= (uint64_t)val << 32; 332 designware_pcie_root_update_msi_mapping(root); 333 break; 334 335 case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: 336 root->msi.intr[0].enable = val; 337 designware_pcie_root_update_msi_mapping(root); 338 break; 339 340 case DESIGNWARE_PCIE_MSI_INTR0_MASK: 341 root->msi.intr[0].mask = val; 342 break; 343 344 case DESIGNWARE_PCIE_MSI_INTR0_STATUS: 345 root->msi.intr[0].status ^= val; 346 if (!root->msi.intr[0].status) { 347 qemu_set_irq(host->pci.msi, 0); 348 } 349 break; 350 351 case DESIGNWARE_PCIE_ATU_VIEWPORT: 352 val &= DESIGNWARE_PCIE_ATU_REGION_INBOUND | 353 (DESIGNWARE_PCIE_NUM_VIEWPORTS - 1); 354 root->atu_viewport = val; 355 break; 356 357 case DESIGNWARE_PCIE_ATU_LOWER_BASE: 358 viewport->base &= 0xFFFFFFFF00000000ULL; 359 viewport->base |= val; 360 break; 361 362 case DESIGNWARE_PCIE_ATU_UPPER_BASE: 363 viewport->base &= 0x00000000FFFFFFFFULL; 364 viewport->base |= (uint64_t)val << 32; 365 break; 366 367 case DESIGNWARE_PCIE_ATU_LOWER_TARGET: 368 viewport->target &= 0xFFFFFFFF00000000ULL; 369 viewport->target |= val; 370 break; 371 372 case DESIGNWARE_PCIE_ATU_UPPER_TARGET: 373 viewport->target &= 0x00000000FFFFFFFFULL; 374 viewport->target |= val; 375 break; 376 377 case DESIGNWARE_PCIE_ATU_LIMIT: 378 viewport->limit = val; 379 break; 380 381 case DESIGNWARE_PCIE_ATU_CR1: 382 viewport->cr[0] = val; 383 break; 384 case DESIGNWARE_PCIE_ATU_CR2: 385 viewport->cr[1] = val; 386 designware_pcie_update_viewport(root, viewport); 387 break; 388 389 default: 390 pci_bridge_write_config(d, address, val, len); 391 break; 392 } 393 } 394 395 static char *designware_pcie_viewport_name(const char *direction, 396 unsigned int i, 397 const char *type) 398 { 399 return g_strdup_printf("PCI %s Viewport %u [%s]", 400 direction, i, type); 401 } 402 403 static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) 404 { 405 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); 406 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); 407 MemoryRegion *host_mem = get_system_memory(); 408 MemoryRegion *address_space = &host->pci.memory; 409 PCIBridge *br = PCI_BRIDGE(dev); 410 DesignwarePCIEViewport *viewport; 411 /* 412 * Dummy values used for initial configuration of MemoryRegions 413 * that belong to a given viewport 414 */ 415 const hwaddr dummy_offset = 0; 416 const uint64_t dummy_size = 4; 417 size_t i; 418 419 br->bus_name = "dw-pcie"; 420 421 pci_set_word(dev->config + PCI_COMMAND, 422 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 423 424 pci_config_set_interrupt_pin(dev->config, 1); 425 pci_bridge_initfn(dev, TYPE_PCIE_BUS); 426 427 pcie_port_init_reg(dev); 428 429 pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT, 430 0, &error_fatal); 431 432 msi_nonbroken = true; 433 msi_init(dev, 0x50, 32, true, true, &error_fatal); 434 435 for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) { 436 MemoryRegion *source, *destination, *mem; 437 const char *direction; 438 char *name; 439 440 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; 441 viewport->inbound = true; 442 viewport->base = 0x0000000000000000ULL; 443 viewport->target = 0x0000000000000000ULL; 444 viewport->limit = UINT32_MAX; 445 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; 446 447 source = &host->pci.address_space_root; 448 destination = host_mem; 449 direction = "Inbound"; 450 451 /* 452 * Configure MemoryRegion implementing PCI -> CPU memory 453 * access 454 */ 455 mem = &viewport->mem; 456 name = designware_pcie_viewport_name(direction, i, "MEM"); 457 memory_region_init_alias(mem, OBJECT(root), name, destination, 458 dummy_offset, dummy_size); 459 memory_region_add_subregion_overlap(source, dummy_offset, mem, -1); 460 memory_region_set_enabled(mem, false); 461 g_free(name); 462 463 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; 464 viewport->root = root; 465 viewport->inbound = false; 466 viewport->base = 0x0000000000000000ULL; 467 viewport->target = 0x0000000000000000ULL; 468 viewport->limit = UINT32_MAX; 469 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; 470 471 destination = &host->pci.memory; 472 direction = "Outbound"; 473 source = host_mem; 474 475 /* 476 * Configure MemoryRegion implementing CPU -> PCI memory 477 * access 478 */ 479 mem = &viewport->mem; 480 name = designware_pcie_viewport_name(direction, i, "MEM"); 481 memory_region_init_alias(mem, OBJECT(root), name, destination, 482 dummy_offset, dummy_size); 483 memory_region_add_subregion(source, dummy_offset, mem); 484 memory_region_set_enabled(mem, false); 485 g_free(name); 486 487 /* 488 * Configure MemoryRegion implementing access to configuration 489 * space 490 */ 491 mem = &viewport->cfg; 492 name = designware_pcie_viewport_name(direction, i, "CFG"); 493 memory_region_init_io(&viewport->cfg, OBJECT(root), 494 &designware_pci_host_conf_ops, 495 viewport, name, dummy_size); 496 memory_region_add_subregion(source, dummy_offset, mem); 497 memory_region_set_enabled(mem, false); 498 g_free(name); 499 } 500 501 /* 502 * If no inbound iATU windows are configured, HW defaults to 503 * letting inbound TLPs to pass in. We emulate that by explicitly 504 * configuring first inbound window to cover all of target's 505 * address space. 506 * 507 * NOTE: This will not work correctly for the case when first 508 * configured inbound window is window 0 509 */ 510 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; 511 viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; 512 designware_pcie_update_viewport(root, viewport); 513 514 memory_region_init_io(&root->msi.iomem, OBJECT(root), 515 &designware_pci_host_msi_ops, 516 root, "pcie-msi", 0x4); 517 /* 518 * We initially place MSI interrupt I/O region at address 0 and 519 * disable it. It'll be later moved to correct offset and enabled 520 * in designware_pcie_root_update_msi_mapping() as a part of 521 * initialization done by guest OS 522 */ 523 memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem); 524 memory_region_set_enabled(&root->msi.iomem, false); 525 } 526 527 static void designware_pcie_set_irq(void *opaque, int irq_num, int level) 528 { 529 DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST(opaque); 530 531 qemu_set_irq(host->pci.irqs[irq_num], level); 532 } 533 534 static const char * 535 designware_pcie_host_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus) 536 { 537 return "0000:00"; 538 } 539 540 static const VMStateDescription vmstate_designware_pcie_msi_bank = { 541 .name = "designware-pcie-msi-bank", 542 .version_id = 1, 543 .minimum_version_id = 1, 544 .fields = (const VMStateField[]) { 545 VMSTATE_UINT32(enable, DesignwarePCIEMSIBank), 546 VMSTATE_UINT32(mask, DesignwarePCIEMSIBank), 547 VMSTATE_UINT32(status, DesignwarePCIEMSIBank), 548 VMSTATE_END_OF_LIST() 549 } 550 }; 551 552 static const VMStateDescription vmstate_designware_pcie_msi = { 553 .name = "designware-pcie-msi", 554 .version_id = 1, 555 .minimum_version_id = 1, 556 .fields = (const VMStateField[]) { 557 VMSTATE_UINT64(base, DesignwarePCIEMSI), 558 VMSTATE_STRUCT_ARRAY(intr, 559 DesignwarePCIEMSI, 560 DESIGNWARE_PCIE_NUM_MSI_BANKS, 561 1, 562 vmstate_designware_pcie_msi_bank, 563 DesignwarePCIEMSIBank), 564 VMSTATE_END_OF_LIST() 565 } 566 }; 567 568 static const VMStateDescription vmstate_designware_pcie_viewport = { 569 .name = "designware-pcie-viewport", 570 .version_id = 1, 571 .minimum_version_id = 1, 572 .fields = (const VMStateField[]) { 573 VMSTATE_UINT64(base, DesignwarePCIEViewport), 574 VMSTATE_UINT64(target, DesignwarePCIEViewport), 575 VMSTATE_UINT32(limit, DesignwarePCIEViewport), 576 VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2), 577 VMSTATE_END_OF_LIST() 578 } 579 }; 580 581 static const VMStateDescription vmstate_designware_pcie_root = { 582 .name = "designware-pcie-root", 583 .version_id = 1, 584 .minimum_version_id = 1, 585 .fields = (const VMStateField[]) { 586 VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), 587 VMSTATE_UINT32(atu_viewport, DesignwarePCIERoot), 588 VMSTATE_STRUCT_2DARRAY(viewports, 589 DesignwarePCIERoot, 590 2, 591 DESIGNWARE_PCIE_NUM_VIEWPORTS, 592 1, 593 vmstate_designware_pcie_viewport, 594 DesignwarePCIEViewport), 595 VMSTATE_STRUCT(msi, 596 DesignwarePCIERoot, 597 1, 598 vmstate_designware_pcie_msi, 599 DesignwarePCIEMSI), 600 VMSTATE_END_OF_LIST() 601 } 602 }; 603 604 static void designware_pcie_root_class_init(ObjectClass *klass, void *data) 605 { 606 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 607 DeviceClass *dc = DEVICE_CLASS(klass); 608 609 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 610 611 k->vendor_id = PCI_VENDOR_ID_SYNOPSYS; 612 k->device_id = 0xABCD; 613 k->revision = 0; 614 k->class_id = PCI_CLASS_BRIDGE_PCI; 615 k->exit = pci_bridge_exitfn; 616 k->realize = designware_pcie_root_realize; 617 k->config_read = designware_pcie_root_config_read; 618 k->config_write = designware_pcie_root_config_write; 619 620 device_class_set_legacy_reset(dc, pci_bridge_reset); 621 /* 622 * PCI-facing part of the host bridge, not usable without the 623 * host-facing part, which can't be device_add'ed, yet. 624 */ 625 dc->user_creatable = false; 626 dc->vmsd = &vmstate_designware_pcie_root; 627 } 628 629 static uint64_t designware_pcie_host_mmio_read(void *opaque, hwaddr addr, 630 unsigned int size) 631 { 632 PCIHostState *pci = PCI_HOST_BRIDGE(opaque); 633 PCIDevice *device = pci_find_device(pci->bus, 0, 0); 634 635 return pci_host_config_read_common(device, 636 addr, 637 pci_config_size(device), 638 size); 639 } 640 641 static void designware_pcie_host_mmio_write(void *opaque, hwaddr addr, 642 uint64_t val, unsigned int size) 643 { 644 PCIHostState *pci = PCI_HOST_BRIDGE(opaque); 645 PCIDevice *device = pci_find_device(pci->bus, 0, 0); 646 647 return pci_host_config_write_common(device, 648 addr, 649 pci_config_size(device), 650 val, size); 651 } 652 653 static const MemoryRegionOps designware_pci_mmio_ops = { 654 .read = designware_pcie_host_mmio_read, 655 .write = designware_pcie_host_mmio_write, 656 .endianness = DEVICE_LITTLE_ENDIAN, 657 .impl = { 658 /* 659 * Our device would not work correctly if the guest was doing 660 * unaligned access. This might not be a limitation on the real 661 * device but in practice there is no reason for a guest to access 662 * this device unaligned. 663 */ 664 .min_access_size = 4, 665 .max_access_size = 4, 666 .unaligned = false, 667 }, 668 }; 669 670 static AddressSpace *designware_pcie_host_set_iommu(PCIBus *bus, void *opaque, 671 int devfn) 672 { 673 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(opaque); 674 675 return &s->pci.address_space; 676 } 677 678 static const PCIIOMMUOps designware_iommu_ops = { 679 .get_address_space = designware_pcie_host_set_iommu, 680 }; 681 682 static void designware_pcie_host_realize(DeviceState *dev, Error **errp) 683 { 684 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 685 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev); 686 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 687 size_t i; 688 689 for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) { 690 sysbus_init_irq(sbd, &s->pci.irqs[i]); 691 } 692 sysbus_init_irq(sbd, &s->pci.msi); 693 694 memory_region_init_io(&s->mmio, 695 OBJECT(s), 696 &designware_pci_mmio_ops, 697 s, 698 "pcie.reg", 4 * 1024); 699 sysbus_init_mmio(sbd, &s->mmio); 700 701 memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16); 702 memory_region_init(&s->pci.memory, OBJECT(s), 703 "pcie-bus-memory", 704 UINT64_MAX); 705 706 pci->bus = pci_register_root_bus(dev, "pcie", 707 designware_pcie_set_irq, 708 pci_swizzle_map_irq_fn, 709 s, 710 &s->pci.memory, 711 &s->pci.io, 712 0, 4, 713 TYPE_DESIGNWARE_PCIE_ROOT_BUS); 714 pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 715 716 memory_region_init(&s->pci.address_space_root, 717 OBJECT(s), 718 "pcie-bus-address-space-root", 719 UINT64_MAX); 720 memory_region_add_subregion(&s->pci.address_space_root, 721 0x0, &s->pci.memory); 722 address_space_init(&s->pci.address_space, 723 &s->pci.address_space_root, 724 "pcie-bus-address-space"); 725 pci_setup_iommu(pci->bus, &designware_iommu_ops, s); 726 727 qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal); 728 } 729 730 static const VMStateDescription vmstate_designware_pcie_host = { 731 .name = "designware-pcie-host", 732 .version_id = 1, 733 .minimum_version_id = 1, 734 .fields = (const VMStateField[]) { 735 VMSTATE_STRUCT(root, 736 DesignwarePCIEHost, 737 1, 738 vmstate_designware_pcie_root, 739 DesignwarePCIERoot), 740 VMSTATE_END_OF_LIST() 741 } 742 }; 743 744 static void designware_pcie_host_class_init(ObjectClass *klass, void *data) 745 { 746 DeviceClass *dc = DEVICE_CLASS(klass); 747 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 748 749 hc->root_bus_path = designware_pcie_host_root_bus_path; 750 dc->realize = designware_pcie_host_realize; 751 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 752 dc->fw_name = "pci"; 753 dc->vmsd = &vmstate_designware_pcie_host; 754 } 755 756 static void designware_pcie_host_init(Object *obj) 757 { 758 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj); 759 DesignwarePCIERoot *root = &s->root; 760 761 object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT); 762 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); 763 qdev_prop_set_bit(DEVICE(root), "multifunction", false); 764 } 765 766 static const TypeInfo designware_pcie_types[] = { 767 { 768 .name = TYPE_DESIGNWARE_PCIE_ROOT_BUS, 769 .parent = TYPE_PCIE_BUS, 770 .instance_size = sizeof(DesignwarePCIERootBus), 771 .class_init = designware_pcie_root_bus_class_init, 772 }, { 773 .name = TYPE_DESIGNWARE_PCIE_HOST, 774 .parent = TYPE_PCI_HOST_BRIDGE, 775 .instance_size = sizeof(DesignwarePCIEHost), 776 .instance_init = designware_pcie_host_init, 777 .class_init = designware_pcie_host_class_init, 778 }, { 779 .name = TYPE_DESIGNWARE_PCIE_ROOT, 780 .parent = TYPE_PCI_BRIDGE, 781 .instance_size = sizeof(DesignwarePCIERoot), 782 .class_init = designware_pcie_root_class_init, 783 .interfaces = (InterfaceInfo[]) { 784 { INTERFACE_PCIE_DEVICE }, 785 { } 786 }, 787 }, 788 }; 789 790 DEFINE_TYPES(designware_pcie_types) 791