1 /* 2 * bonito north bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 6 * 7 * This code is licensed under the GNU GPL v2. 8 */ 9 10 /* 11 * fulong 2e mini pc has a bonito north bridge. 12 */ 13 14 /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? 15 * 16 * devfn pci_slot<<3 + funno 17 * one pci bus can have 32 devices and each device can have 8 functions. 18 * 19 * In bonito north bridge, pci slot = IDSEL bit - 12. 20 * For example, PCI_IDSEL_VIA686B = 17, 21 * pci slot = 17-12=5 22 * 23 * so 24 * VT686B_FUN0's devfn = (5<<3)+0 25 * VT686B_FUN1's devfn = (5<<3)+1 26 * 27 * qemu also uses pci address for north bridge to access pci config register. 28 * bus_no [23:16] 29 * dev_no [15:11] 30 * fun_no [10:8] 31 * reg_no [7:2] 32 * 33 * so function bonito_sbridge_pciaddr for the translation from 34 * north bridge address to pci address. 35 */ 36 37 #include <assert.h> 38 39 #include "hw.h" 40 #include "pci.h" 41 #include "pc.h" 42 #include "mips.h" 43 #include "pci_host.h" 44 #include "sysemu.h" 45 #include "exec-memory.h" 46 47 //#define DEBUG_BONITO 48 49 #ifdef DEBUG_BONITO 50 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) 51 #else 52 #define DPRINTF(fmt, ...) 53 #endif 54 55 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ 56 #define BONITO_BOOT_BASE 0x1fc00000 57 #define BONITO_BOOT_SIZE 0x00100000 58 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) 59 #define BONITO_FLASH_BASE 0x1c000000 60 #define BONITO_FLASH_SIZE 0x03000000 61 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) 62 #define BONITO_SOCKET_BASE 0x1f800000 63 #define BONITO_SOCKET_SIZE 0x00400000 64 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) 65 #define BONITO_REG_BASE 0x1fe00000 66 #define BONITO_REG_SIZE 0x00040000 67 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) 68 #define BONITO_DEV_BASE 0x1ff00000 69 #define BONITO_DEV_SIZE 0x00100000 70 #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) 71 #define BONITO_PCILO_BASE 0x10000000 72 #define BONITO_PCILO_BASE_VA 0xb0000000 73 #define BONITO_PCILO_SIZE 0x0c000000 74 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) 75 #define BONITO_PCILO0_BASE 0x10000000 76 #define BONITO_PCILO1_BASE 0x14000000 77 #define BONITO_PCILO2_BASE 0x18000000 78 #define BONITO_PCIHI_BASE 0x20000000 79 #define BONITO_PCIHI_SIZE 0x20000000 80 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) 81 #define BONITO_PCIIO_BASE 0x1fd00000 82 #define BONITO_PCIIO_BASE_VA 0xbfd00000 83 #define BONITO_PCIIO_SIZE 0x00010000 84 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) 85 #define BONITO_PCICFG_BASE 0x1fe80000 86 #define BONITO_PCICFG_SIZE 0x00080000 87 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) 88 89 90 #define BONITO_PCICONFIGBASE 0x00 91 #define BONITO_REGBASE 0x100 92 93 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) 94 #define BONITO_PCICONFIG_SIZE (0x100) 95 96 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) 97 #define BONITO_INTERNAL_REG_SIZE (0x70) 98 99 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) 100 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) 101 102 103 104 /* 1. Bonito h/w Configuration */ 105 /* Power on register */ 106 107 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ 108 #define BONITO_BONGENCFG_OFFSET 0x4 109 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ 110 111 /* 2. IO & IDE configuration */ 112 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ 113 114 /* 3. IO & IDE configuration */ 115 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ 116 117 /* 4. PCI address map control */ 118 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ 119 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ 120 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ 121 122 /* 5. ICU & GPIO regs */ 123 /* GPIO Regs - r/w */ 124 #define BONITO_GPIODATA_OFFSET 0x1c 125 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ 126 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ 127 128 /* ICU Configuration Regs - r/w */ 129 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ 130 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ 131 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ 132 133 /* ICU Enable Regs - IntEn & IntISR are r/o. */ 134 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ 135 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ 136 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ 137 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ 138 139 /* PCI mail boxes */ 140 #define BONITO_PCIMAIL0_OFFSET 0x40 141 #define BONITO_PCIMAIL1_OFFSET 0x44 142 #define BONITO_PCIMAIL2_OFFSET 0x48 143 #define BONITO_PCIMAIL3_OFFSET 0x4c 144 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ 145 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ 146 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ 147 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ 148 149 /* 6. PCI cache */ 150 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ 151 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ 152 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ 153 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ 154 155 /* 7. other*/ 156 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ 157 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ 158 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ 159 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ 160 161 #define BONITO_REGS (0x70 >> 2) 162 163 /* PCI config for south bridge. type 0 */ 164 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ 165 #define BONITO_PCICONF_IDSEL_OFFSET 11 166 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ 167 #define BONITO_PCICONF_FUN_OFFSET 8 168 #define BONITO_PCICONF_REG_MASK 0xFC 169 #define BONITO_PCICONF_REG_OFFSET 0 170 171 172 /* idsel BIT = pci slot number +12 */ 173 #define PCI_SLOT_BASE 12 174 #define PCI_IDSEL_VIA686B_BIT (17) 175 #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT) 176 177 #define PCI_ADDR(busno,devno,funno,regno) \ 178 ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) 179 180 typedef PCIHostState BonitoState; 181 182 typedef struct PCIBonitoState 183 { 184 PCIDevice dev; 185 BonitoState *pcihost; 186 uint32_t regs[BONITO_REGS]; 187 188 struct bonldma { 189 uint32_t ldmactrl; 190 uint32_t ldmastat; 191 uint32_t ldmaaddr; 192 uint32_t ldmago; 193 } bonldma; 194 195 /* Based at 1fe00300, bonito Copier */ 196 struct boncop { 197 uint32_t copctrl; 198 uint32_t copstat; 199 uint32_t coppaddr; 200 uint32_t copgo; 201 } boncop; 202 203 /* Bonito registers */ 204 MemoryRegion iomem; 205 206 target_phys_addr_t bonito_pciio_start; 207 target_phys_addr_t bonito_pciio_length; 208 int bonito_pciio_handle; 209 210 target_phys_addr_t bonito_localio_start; 211 target_phys_addr_t bonito_localio_length; 212 int bonito_localio_handle; 213 214 target_phys_addr_t bonito_ldma_start; 215 target_phys_addr_t bonito_ldma_length; 216 int bonito_ldma_handle; 217 218 target_phys_addr_t bonito_cop_start; 219 target_phys_addr_t bonito_cop_length; 220 int bonito_cop_handle; 221 222 } PCIBonitoState; 223 224 PCIBonitoState * bonito_state; 225 226 static void bonito_writel(void *opaque, target_phys_addr_t addr, 227 uint64_t val, unsigned size) 228 { 229 PCIBonitoState *s = opaque; 230 uint32_t saddr; 231 int reset = 0; 232 233 saddr = (addr - BONITO_REGBASE) >> 2; 234 235 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr); 236 switch (saddr) { 237 case BONITO_BONPONCFG: 238 case BONITO_IODEVCFG: 239 case BONITO_SDCFG: 240 case BONITO_PCIMAP: 241 case BONITO_PCIMEMBASECFG: 242 case BONITO_PCIMAP_CFG: 243 case BONITO_GPIODATA: 244 case BONITO_GPIOIE: 245 case BONITO_INTEDGE: 246 case BONITO_INTSTEER: 247 case BONITO_INTPOL: 248 case BONITO_PCIMAIL0: 249 case BONITO_PCIMAIL1: 250 case BONITO_PCIMAIL2: 251 case BONITO_PCIMAIL3: 252 case BONITO_PCICACHECTRL: 253 case BONITO_PCICACHETAG: 254 case BONITO_PCIBADADDR: 255 case BONITO_PCIMSTAT: 256 case BONITO_TIMECFG: 257 case BONITO_CPUCFG: 258 case BONITO_DQCFG: 259 case BONITO_MEMSIZE: 260 s->regs[saddr] = val; 261 break; 262 case BONITO_BONGENCFG: 263 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { 264 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ 265 } 266 s->regs[saddr] = val; 267 if (reset) { 268 qemu_system_reset_request(); 269 } 270 break; 271 case BONITO_INTENSET: 272 s->regs[BONITO_INTENSET] = val; 273 s->regs[BONITO_INTEN] |= val; 274 break; 275 case BONITO_INTENCLR: 276 s->regs[BONITO_INTENCLR] = val; 277 s->regs[BONITO_INTEN] &= ~val; 278 break; 279 case BONITO_INTEN: 280 case BONITO_INTISR: 281 DPRINTF("write to readonly bonito register %x\n", saddr); 282 break; 283 default: 284 DPRINTF("write to unknown bonito register %x\n", saddr); 285 break; 286 } 287 } 288 289 static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr, 290 unsigned size) 291 { 292 PCIBonitoState *s = opaque; 293 uint32_t saddr; 294 295 saddr = (addr - BONITO_REGBASE) >> 2; 296 297 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); 298 switch (saddr) { 299 case BONITO_INTISR: 300 return s->regs[saddr]; 301 default: 302 return s->regs[saddr]; 303 } 304 } 305 306 static const MemoryRegionOps bonito_ops = { 307 .read = bonito_readl, 308 .write = bonito_writel, 309 .endianness = DEVICE_NATIVE_ENDIAN, 310 .valid = { 311 .min_access_size = 4, 312 .max_access_size = 4, 313 }, 314 }; 315 316 static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr, 317 uint64_t val, unsigned size) 318 { 319 PCIBonitoState *s = opaque; 320 321 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 322 s->dev.config_write(&s->dev, addr, val, 4); 323 } 324 325 static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr, 326 unsigned size) 327 { 328 329 PCIBonitoState *s = opaque; 330 331 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); 332 return s->dev.config_read(&s->dev, addr, 4); 333 } 334 335 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ 336 337 static const MemoryRegionOps bonito_pciconf_ops = { 338 .read = bonito_pciconf_readl, 339 .write = bonito_pciconf_writel, 340 .endianness = DEVICE_NATIVE_ENDIAN, 341 .valid = { 342 .min_access_size = 4, 343 .max_access_size = 4, 344 }, 345 }; 346 347 static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr) 348 { 349 uint32_t val; 350 PCIBonitoState *s = opaque; 351 352 val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)]; 353 354 return val; 355 } 356 357 static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr, 358 uint32_t val) 359 { 360 PCIBonitoState *s = opaque; 361 362 ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff; 363 } 364 365 static CPUWriteMemoryFunc * const bonito_ldma_write[] = { 366 NULL, 367 NULL, 368 bonito_ldma_writel, 369 }; 370 371 static CPUReadMemoryFunc * const bonito_ldma_read[] = { 372 NULL, 373 NULL, 374 bonito_ldma_readl, 375 }; 376 377 static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr) 378 { 379 uint32_t val; 380 PCIBonitoState *s = opaque; 381 382 val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)]; 383 384 return val; 385 } 386 387 static void bonito_cop_writel(void *opaque, target_phys_addr_t addr, 388 uint32_t val) 389 { 390 PCIBonitoState *s = opaque; 391 392 ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff; 393 } 394 395 static CPUWriteMemoryFunc * const bonito_cop_write[] = { 396 NULL, 397 NULL, 398 bonito_cop_writel, 399 }; 400 401 static CPUReadMemoryFunc * const bonito_cop_read[] = { 402 NULL, 403 NULL, 404 bonito_cop_readl, 405 }; 406 407 static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr) 408 { 409 PCIBonitoState *s = opaque; 410 uint32_t cfgaddr; 411 uint32_t idsel; 412 uint32_t devno; 413 uint32_t funno; 414 uint32_t regno; 415 uint32_t pciaddr; 416 417 /* support type0 pci config */ 418 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { 419 return 0xffffffff; 420 } 421 422 cfgaddr = addr & 0xffff; 423 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; 424 425 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; 426 devno = ffs(idsel) - 1; 427 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; 428 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; 429 430 if (idsel == 0) { 431 fprintf(stderr, "error in bonito pci config address" TARGET_FMT_plx 432 ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); 433 exit(1); 434 } 435 pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno); 436 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", 437 cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno); 438 439 return pciaddr; 440 } 441 442 static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr, 443 uint32_t val) 444 { 445 PCIBonitoState *s = opaque; 446 uint32_t pciaddr; 447 uint16_t status; 448 449 DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val); 450 pciaddr = bonito_sbridge_pciaddr(s, addr); 451 452 if (pciaddr == 0xffffffff) { 453 return; 454 } 455 456 /* set the pci address in s->config_reg */ 457 s->pcihost->config_reg = (pciaddr) | (1u << 31); 458 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val & 0xff, 1); 459 460 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 461 status = pci_get_word(s->dev.config + PCI_STATUS); 462 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 463 pci_set_word(s->dev.config + PCI_STATUS, status); 464 } 465 466 static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr, 467 uint32_t val) 468 { 469 PCIBonitoState *s = opaque; 470 uint32_t pciaddr; 471 uint16_t status; 472 473 DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val); 474 assert((addr&0x1)==0); 475 476 pciaddr = bonito_sbridge_pciaddr(s, addr); 477 478 if (pciaddr == 0xffffffff) { 479 return; 480 } 481 482 /* set the pci address in s->config_reg */ 483 s->pcihost->config_reg = (pciaddr) | (1u << 31); 484 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 2); 485 486 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 487 status = pci_get_word(s->dev.config + PCI_STATUS); 488 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 489 pci_set_word(s->dev.config + PCI_STATUS, status); 490 } 491 492 static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr, 493 uint32_t val) 494 { 495 PCIBonitoState *s = opaque; 496 uint32_t pciaddr; 497 uint16_t status; 498 499 DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 500 assert((addr&0x3)==0); 501 502 pciaddr = bonito_sbridge_pciaddr(s, addr); 503 504 if (pciaddr == 0xffffffff) { 505 return; 506 } 507 508 /* set the pci address in s->config_reg */ 509 s->pcihost->config_reg = (pciaddr) | (1u << 31); 510 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4); 511 512 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 513 status = pci_get_word(s->dev.config + PCI_STATUS); 514 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 515 pci_set_word(s->dev.config + PCI_STATUS, status); 516 } 517 518 static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr) 519 { 520 PCIBonitoState *s = opaque; 521 uint32_t pciaddr; 522 uint16_t status; 523 524 DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr); 525 pciaddr = bonito_sbridge_pciaddr(s, addr); 526 527 if (pciaddr == 0xffffffff) { 528 return 0xff; 529 } 530 531 /* set the pci address in s->config_reg */ 532 s->pcihost->config_reg = (pciaddr) | (1u << 31); 533 534 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 535 status = pci_get_word(s->dev.config + PCI_STATUS); 536 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 537 pci_set_word(s->dev.config + PCI_STATUS, status); 538 539 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1); 540 } 541 542 static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr) 543 { 544 PCIBonitoState *s = opaque; 545 uint32_t pciaddr; 546 uint16_t status; 547 548 DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr); 549 assert((addr&0x1)==0); 550 551 pciaddr = bonito_sbridge_pciaddr(s, addr); 552 553 if (pciaddr == 0xffffffff) { 554 return 0xffff; 555 } 556 557 /* set the pci address in s->config_reg */ 558 s->pcihost->config_reg = (pciaddr) | (1u << 31); 559 560 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 561 status = pci_get_word(s->dev.config + PCI_STATUS); 562 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 563 pci_set_word(s->dev.config + PCI_STATUS, status); 564 565 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2); 566 } 567 568 static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr) 569 { 570 PCIBonitoState *s = opaque; 571 uint32_t pciaddr; 572 uint16_t status; 573 574 DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr); 575 assert((addr&0x3) == 0); 576 577 pciaddr = bonito_sbridge_pciaddr(s, addr); 578 579 if (pciaddr == 0xffffffff) { 580 return 0xffffffff; 581 } 582 583 /* set the pci address in s->config_reg */ 584 s->pcihost->config_reg = (pciaddr) | (1u << 31); 585 586 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 587 status = pci_get_word(s->dev.config + PCI_STATUS); 588 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 589 pci_set_word(s->dev.config + PCI_STATUS, status); 590 591 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 4); 592 } 593 594 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ 595 static const MemoryRegionOps bonito_spciconf_ops = { 596 .old_mmio = { 597 .read = { 598 bonito_spciconf_readb, 599 bonito_spciconf_readw, 600 bonito_spciconf_readl, 601 }, 602 .write = { 603 bonito_spciconf_writeb, 604 bonito_spciconf_writew, 605 bonito_spciconf_writel, 606 }, 607 }, 608 .endianness = DEVICE_NATIVE_ENDIAN, 609 }; 610 611 #define BONITO_IRQ_BASE 32 612 613 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) 614 { 615 qemu_irq *pic = opaque; 616 int internal_irq = irq_num - BONITO_IRQ_BASE; 617 618 if (bonito_state->regs[BONITO_INTEDGE] & (1<<internal_irq)) { 619 qemu_irq_pulse(*pic); 620 } else { /* level triggered */ 621 if (bonito_state->regs[BONITO_INTPOL] & (1<<internal_irq)) { 622 qemu_irq_raise(*pic); 623 } else { 624 qemu_irq_lower(*pic); 625 } 626 } 627 } 628 629 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ 630 static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num) 631 { 632 int slot; 633 634 slot = (pci_dev->devfn >> 3); 635 636 switch (slot) { 637 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ 638 return irq_num % 4 + BONITO_IRQ_BASE; 639 case 6: /* FULONG2E_ATI_SLOT, VGA */ 640 return 4 + BONITO_IRQ_BASE; 641 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ 642 return 5 + BONITO_IRQ_BASE; 643 case 8 ... 12: /* PCI slot 1 to 4 */ 644 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; 645 default: /* Unknown device, don't do any translation */ 646 return irq_num; 647 } 648 } 649 650 static void bonito_reset(void *opaque) 651 { 652 PCIBonitoState *s = opaque; 653 654 /* set the default value of north bridge registers */ 655 656 s->regs[BONITO_BONPONCFG] = 0xc40; 657 s->regs[BONITO_BONGENCFG] = 0x1384; 658 s->regs[BONITO_IODEVCFG] = 0x2bff8010; 659 s->regs[BONITO_SDCFG] = 0x255e0091; 660 661 s->regs[BONITO_GPIODATA] = 0x1ff; 662 s->regs[BONITO_GPIOIE] = 0x1ff; 663 s->regs[BONITO_DQCFG] = 0x8; 664 s->regs[BONITO_MEMSIZE] = 0x10000000; 665 s->regs[BONITO_PCIMAP] = 0x6140; 666 } 667 668 static const VMStateDescription vmstate_bonito = { 669 .name = "Bonito", 670 .version_id = 1, 671 .minimum_version_id = 1, 672 .minimum_version_id_old = 1, 673 .fields = (VMStateField []) { 674 VMSTATE_PCI_DEVICE(dev, PCIBonitoState), 675 VMSTATE_END_OF_LIST() 676 } 677 }; 678 679 static int bonito_pcihost_initfn(SysBusDevice *dev) 680 { 681 return 0; 682 } 683 684 static int bonito_initfn(PCIDevice *dev) 685 { 686 PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev); 687 SysBusDevice *sysbus = &s->pcihost->busdev; 688 689 /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */ 690 pci_config_set_prog_interface(dev->config, 0x00); 691 692 /* set the north bridge register mapping */ 693 memory_region_init_io(&s->iomem, &bonito_ops, s, 694 "north-bridge-register", BONITO_INTERNAL_REG_SIZE); 695 sysbus_init_mmio_region(sysbus, &s->iomem); 696 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); 697 698 /* set the north bridge pci configure mapping */ 699 memory_region_init_io(&s->pcihost->conf_mem, &bonito_pciconf_ops, s, 700 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); 701 sysbus_init_mmio_region(sysbus, &s->pcihost->conf_mem); 702 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); 703 704 /* set the south bridge pci configure mapping */ 705 memory_region_init_io(&s->pcihost->data_mem, &bonito_spciconf_ops, s, 706 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); 707 sysbus_init_mmio_region(sysbus, &s->pcihost->data_mem); 708 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); 709 710 s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read, 711 bonito_ldma_write, s, 712 DEVICE_NATIVE_ENDIAN); 713 s->bonito_ldma_start = 0xbfe00200; 714 s->bonito_ldma_length = 0x100; 715 cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length, 716 s->bonito_ldma_handle); 717 718 s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read, 719 bonito_cop_write, s, 720 DEVICE_NATIVE_ENDIAN); 721 s->bonito_cop_start = 0xbfe00300; 722 s->bonito_cop_length = 0x100; 723 cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length, 724 s->bonito_cop_handle); 725 726 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ 727 s->bonito_pciio_start = BONITO_PCIIO_BASE; 728 s->bonito_pciio_length = BONITO_PCIIO_SIZE; 729 isa_mem_base = s->bonito_pciio_start; 730 isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length); 731 732 /* add pci local io mapping */ 733 s->bonito_localio_start = BONITO_DEV_BASE; 734 s->bonito_localio_length = BONITO_DEV_SIZE; 735 isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length); 736 737 /* set the default value of north bridge pci config */ 738 pci_set_word(dev->config + PCI_COMMAND, 0x0000); 739 pci_set_word(dev->config + PCI_STATUS, 0x0000); 740 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); 741 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); 742 743 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); 744 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); 745 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); 746 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); 747 748 qemu_register_reset(bonito_reset, s); 749 750 return 0; 751 } 752 753 PCIBus *bonito_init(qemu_irq *pic) 754 { 755 DeviceState *dev; 756 PCIBus *b; 757 BonitoState *pcihost; 758 PCIBonitoState *s; 759 PCIDevice *d; 760 761 dev = qdev_create(NULL, "Bonito-pcihost"); 762 pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev)); 763 b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq, 764 pci_bonito_map_irq, pic, get_system_memory(), 765 get_system_io(), 766 0x28, 32); 767 pcihost->bus = b; 768 qdev_init_nofail(dev); 769 770 /* set the pcihost pointer before bonito_initfn is called */ 771 d = pci_create(b, PCI_DEVFN(0, 0), "Bonito"); 772 s = DO_UPCAST(PCIBonitoState, dev, d); 773 s->pcihost = pcihost; 774 bonito_state = s; 775 qdev_init_nofail(&d->qdev); 776 777 return b; 778 } 779 780 static PCIDeviceInfo bonito_info = { 781 .qdev.name = "Bonito", 782 .qdev.desc = "Host bridge", 783 .qdev.size = sizeof(PCIBonitoState), 784 .qdev.vmsd = &vmstate_bonito, 785 .qdev.no_user = 1, 786 .init = bonito_initfn, 787 /*Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined"*/ 788 .vendor_id = 0xdf53, 789 .device_id = 0x00d5, 790 .revision = 0x01, 791 .class_id = PCI_CLASS_BRIDGE_HOST, 792 }; 793 794 static SysBusDeviceInfo bonito_pcihost_info = { 795 .init = bonito_pcihost_initfn, 796 .qdev.name = "Bonito-pcihost", 797 .qdev.size = sizeof(BonitoState), 798 .qdev.no_user = 1, 799 }; 800 801 static void bonito_register(void) 802 { 803 sysbus_register_withprop(&bonito_pcihost_info); 804 pci_qdev_register(&bonito_info); 805 } 806 device_init(bonito_register); 807