1 /* 2 * bonito north bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 6 * 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 /* 14 * fulong 2e mini pc has a bonito north bridge. 15 */ 16 17 /* 18 * what is the meaning of devfn in qemu and IDSEL in bonito northbridge? 19 * 20 * devfn pci_slot<<3 + funno 21 * one pci bus can have 32 devices and each device can have 8 functions. 22 * 23 * In bonito north bridge, pci slot = IDSEL bit - 12. 24 * For example, PCI_IDSEL_VIA686B = 17, 25 * pci slot = 17-12=5 26 * 27 * so 28 * VT686B_FUN0's devfn = (5<<3)+0 29 * VT686B_FUN1's devfn = (5<<3)+1 30 * 31 * qemu also uses pci address for north bridge to access pci config register. 32 * bus_no [23:16] 33 * dev_no [15:11] 34 * fun_no [10:8] 35 * reg_no [7:2] 36 * 37 * so function bonito_sbridge_pciaddr for the translation from 38 * north bridge address to pci address. 39 */ 40 41 #include "qemu/osdep.h" 42 #include "qemu/units.h" 43 #include "qemu/error-report.h" 44 #include "hw/pci/pci.h" 45 #include "hw/irq.h" 46 #include "hw/mips/mips.h" 47 #include "hw/pci/pci_host.h" 48 #include "migration/vmstate.h" 49 #include "sysemu/reset.h" 50 #include "sysemu/runstate.h" 51 #include "exec/address-spaces.h" 52 #include "hw/misc/unimp.h" 53 54 /* #define DEBUG_BONITO */ 55 56 #ifdef DEBUG_BONITO 57 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) 58 #else 59 #define DPRINTF(fmt, ...) 60 #endif 61 62 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ 63 #define BONITO_BOOT_BASE 0x1fc00000 64 #define BONITO_BOOT_SIZE 0x00100000 65 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1) 66 #define BONITO_FLASH_BASE 0x1c000000 67 #define BONITO_FLASH_SIZE 0x03000000 68 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1) 69 #define BONITO_SOCKET_BASE 0x1f800000 70 #define BONITO_SOCKET_SIZE 0x00400000 71 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1) 72 #define BONITO_REG_BASE 0x1fe00000 73 #define BONITO_REG_SIZE 0x00040000 74 #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1) 75 #define BONITO_DEV_BASE 0x1ff00000 76 #define BONITO_DEV_SIZE 0x00100000 77 #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1) 78 #define BONITO_PCILO_BASE 0x10000000 79 #define BONITO_PCILO_BASE_VA 0xb0000000 80 #define BONITO_PCILO_SIZE 0x0c000000 81 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1) 82 #define BONITO_PCILO0_BASE 0x10000000 83 #define BONITO_PCILO1_BASE 0x14000000 84 #define BONITO_PCILO2_BASE 0x18000000 85 #define BONITO_PCIHI_BASE 0x20000000 86 #define BONITO_PCIHI_SIZE 0x60000000 87 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1) 88 #define BONITO_PCIIO_BASE 0x1fd00000 89 #define BONITO_PCIIO_BASE_VA 0xbfd00000 90 #define BONITO_PCIIO_SIZE 0x00010000 91 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1) 92 #define BONITO_PCICFG_BASE 0x1fe80000 93 #define BONITO_PCICFG_SIZE 0x00080000 94 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1) 95 96 97 #define BONITO_PCICONFIGBASE 0x00 98 #define BONITO_REGBASE 0x100 99 100 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE) 101 #define BONITO_PCICONFIG_SIZE (0x100) 102 103 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE) 104 #define BONITO_INTERNAL_REG_SIZE (0x70) 105 106 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) 107 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) 108 109 110 111 /* 1. Bonito h/w Configuration */ 112 /* Power on register */ 113 114 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ 115 #define BONITO_BONGENCFG_OFFSET 0x4 116 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */ 117 118 /* 2. IO & IDE configuration */ 119 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ 120 121 /* 3. IO & IDE configuration */ 122 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ 123 124 /* 4. PCI address map control */ 125 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ 126 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ 127 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ 128 129 /* 5. ICU & GPIO regs */ 130 /* GPIO Regs - r/w */ 131 #define BONITO_GPIODATA_OFFSET 0x1c 132 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ 133 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ 134 135 /* ICU Configuration Regs - r/w */ 136 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ 137 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ 138 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ 139 140 /* ICU Enable Regs - IntEn & IntISR are r/o. */ 141 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ 142 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ 143 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ 144 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ 145 146 /* PCI mail boxes */ 147 #define BONITO_PCIMAIL0_OFFSET 0x40 148 #define BONITO_PCIMAIL1_OFFSET 0x44 149 #define BONITO_PCIMAIL2_OFFSET 0x48 150 #define BONITO_PCIMAIL3_OFFSET 0x4c 151 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ 152 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ 153 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ 154 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ 155 156 /* 6. PCI cache */ 157 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ 158 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ 159 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ 160 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ 161 162 /* 7. other*/ 163 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ 164 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ 165 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ 166 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ 167 168 #define BONITO_REGS (0x70 >> 2) 169 170 /* PCI config for south bridge. type 0 */ 171 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ 172 #define BONITO_PCICONF_IDSEL_OFFSET 11 173 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ 174 #define BONITO_PCICONF_FUN_OFFSET 8 175 #define BONITO_PCICONF_REG_MASK 0xFC 176 #define BONITO_PCICONF_REG_OFFSET 0 177 178 179 /* idsel BIT = pci slot number +12 */ 180 #define PCI_SLOT_BASE 12 181 #define PCI_IDSEL_VIA686B_BIT (17) 182 #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT) 183 184 #define PCI_ADDR(busno , devno , funno , regno) \ 185 ((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \ 186 (((funno) << 8) & 0x700) + (regno)) 187 188 typedef struct BonitoState BonitoState; 189 190 typedef struct PCIBonitoState { 191 PCIDevice dev; 192 193 BonitoState *pcihost; 194 uint32_t regs[BONITO_REGS]; 195 196 struct bonldma { 197 uint32_t ldmactrl; 198 uint32_t ldmastat; 199 uint32_t ldmaaddr; 200 uint32_t ldmago; 201 } bonldma; 202 203 /* Based at 1fe00300, bonito Copier */ 204 struct boncop { 205 uint32_t copctrl; 206 uint32_t copstat; 207 uint32_t coppaddr; 208 uint32_t copgo; 209 } boncop; 210 211 /* Bonito registers */ 212 MemoryRegion iomem; 213 MemoryRegion iomem_ldma; 214 MemoryRegion iomem_cop; 215 MemoryRegion bonito_pciio; 216 MemoryRegion bonito_localio; 217 218 } PCIBonitoState; 219 220 struct BonitoState { 221 PCIHostState parent_obj; 222 qemu_irq *pic; 223 PCIBonitoState *pci_dev; 224 MemoryRegion pci_mem; 225 }; 226 227 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" 228 #define BONITO_PCI_HOST_BRIDGE(obj) \ 229 OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) 230 231 #define TYPE_PCI_BONITO "Bonito" 232 #define PCI_BONITO(obj) \ 233 OBJECT_CHECK(PCIBonitoState, (obj), TYPE_PCI_BONITO) 234 235 static void bonito_writel(void *opaque, hwaddr addr, 236 uint64_t val, unsigned size) 237 { 238 PCIBonitoState *s = opaque; 239 uint32_t saddr; 240 int reset = 0; 241 242 saddr = addr >> 2; 243 244 DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n", 245 addr, val, saddr); 246 switch (saddr) { 247 case BONITO_BONPONCFG: 248 case BONITO_IODEVCFG: 249 case BONITO_SDCFG: 250 case BONITO_PCIMAP: 251 case BONITO_PCIMEMBASECFG: 252 case BONITO_PCIMAP_CFG: 253 case BONITO_GPIODATA: 254 case BONITO_GPIOIE: 255 case BONITO_INTEDGE: 256 case BONITO_INTSTEER: 257 case BONITO_INTPOL: 258 case BONITO_PCIMAIL0: 259 case BONITO_PCIMAIL1: 260 case BONITO_PCIMAIL2: 261 case BONITO_PCIMAIL3: 262 case BONITO_PCICACHECTRL: 263 case BONITO_PCICACHETAG: 264 case BONITO_PCIBADADDR: 265 case BONITO_PCIMSTAT: 266 case BONITO_TIMECFG: 267 case BONITO_CPUCFG: 268 case BONITO_DQCFG: 269 case BONITO_MEMSIZE: 270 s->regs[saddr] = val; 271 break; 272 case BONITO_BONGENCFG: 273 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { 274 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ 275 } 276 s->regs[saddr] = val; 277 if (reset) { 278 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 279 } 280 break; 281 case BONITO_INTENSET: 282 s->regs[BONITO_INTENSET] = val; 283 s->regs[BONITO_INTEN] |= val; 284 break; 285 case BONITO_INTENCLR: 286 s->regs[BONITO_INTENCLR] = val; 287 s->regs[BONITO_INTEN] &= ~val; 288 break; 289 case BONITO_INTEN: 290 case BONITO_INTISR: 291 DPRINTF("write to readonly bonito register %x\n", saddr); 292 break; 293 default: 294 DPRINTF("write to unknown bonito register %x\n", saddr); 295 break; 296 } 297 } 298 299 static uint64_t bonito_readl(void *opaque, hwaddr addr, 300 unsigned size) 301 { 302 PCIBonitoState *s = opaque; 303 uint32_t saddr; 304 305 saddr = addr >> 2; 306 307 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); 308 switch (saddr) { 309 case BONITO_INTISR: 310 return s->regs[saddr]; 311 default: 312 return s->regs[saddr]; 313 } 314 } 315 316 static const MemoryRegionOps bonito_ops = { 317 .read = bonito_readl, 318 .write = bonito_writel, 319 .endianness = DEVICE_NATIVE_ENDIAN, 320 .valid = { 321 .min_access_size = 4, 322 .max_access_size = 4, 323 }, 324 }; 325 326 static void bonito_pciconf_writel(void *opaque, hwaddr addr, 327 uint64_t val, unsigned size) 328 { 329 PCIBonitoState *s = opaque; 330 PCIDevice *d = PCI_DEVICE(s); 331 332 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val); 333 d->config_write(d, addr, val, 4); 334 } 335 336 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, 337 unsigned size) 338 { 339 340 PCIBonitoState *s = opaque; 341 PCIDevice *d = PCI_DEVICE(s); 342 343 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); 344 return d->config_read(d, addr, 4); 345 } 346 347 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ 348 349 static const MemoryRegionOps bonito_pciconf_ops = { 350 .read = bonito_pciconf_readl, 351 .write = bonito_pciconf_writel, 352 .endianness = DEVICE_NATIVE_ENDIAN, 353 .valid = { 354 .min_access_size = 4, 355 .max_access_size = 4, 356 }, 357 }; 358 359 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, 360 unsigned size) 361 { 362 uint32_t val; 363 PCIBonitoState *s = opaque; 364 365 if (addr >= sizeof(s->bonldma)) { 366 return 0; 367 } 368 369 val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)]; 370 371 return val; 372 } 373 374 static void bonito_ldma_writel(void *opaque, hwaddr addr, 375 uint64_t val, unsigned size) 376 { 377 PCIBonitoState *s = opaque; 378 379 if (addr >= sizeof(s->bonldma)) { 380 return; 381 } 382 383 ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff; 384 } 385 386 static const MemoryRegionOps bonito_ldma_ops = { 387 .read = bonito_ldma_readl, 388 .write = bonito_ldma_writel, 389 .endianness = DEVICE_NATIVE_ENDIAN, 390 .valid = { 391 .min_access_size = 4, 392 .max_access_size = 4, 393 }, 394 }; 395 396 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, 397 unsigned size) 398 { 399 uint32_t val; 400 PCIBonitoState *s = opaque; 401 402 if (addr >= sizeof(s->boncop)) { 403 return 0; 404 } 405 406 val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)]; 407 408 return val; 409 } 410 411 static void bonito_cop_writel(void *opaque, hwaddr addr, 412 uint64_t val, unsigned size) 413 { 414 PCIBonitoState *s = opaque; 415 416 if (addr >= sizeof(s->boncop)) { 417 return; 418 } 419 420 ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff; 421 } 422 423 static const MemoryRegionOps bonito_cop_ops = { 424 .read = bonito_cop_readl, 425 .write = bonito_cop_writel, 426 .endianness = DEVICE_NATIVE_ENDIAN, 427 .valid = { 428 .min_access_size = 4, 429 .max_access_size = 4, 430 }, 431 }; 432 433 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) 434 { 435 PCIBonitoState *s = opaque; 436 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 437 uint32_t cfgaddr; 438 uint32_t idsel; 439 uint32_t devno; 440 uint32_t funno; 441 uint32_t regno; 442 uint32_t pciaddr; 443 444 /* support type0 pci config */ 445 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { 446 return 0xffffffff; 447 } 448 449 cfgaddr = addr & 0xffff; 450 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; 451 452 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> 453 BONITO_PCICONF_IDSEL_OFFSET; 454 devno = ctz32(idsel); 455 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; 456 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; 457 458 if (idsel == 0) { 459 error_report("error in bonito pci config address " TARGET_FMT_plx 460 ",pcimap_cfg=%x", addr, s->regs[BONITO_PCIMAP_CFG]); 461 exit(1); 462 } 463 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); 464 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", 465 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); 466 467 return pciaddr; 468 } 469 470 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, 471 unsigned size) 472 { 473 PCIBonitoState *s = opaque; 474 PCIDevice *d = PCI_DEVICE(s); 475 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 476 uint32_t pciaddr; 477 uint16_t status; 478 479 DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n", 480 addr, size, val); 481 482 pciaddr = bonito_sbridge_pciaddr(s, addr); 483 484 if (pciaddr == 0xffffffff) { 485 return; 486 } 487 488 /* set the pci address in s->config_reg */ 489 phb->config_reg = (pciaddr) | (1u << 31); 490 pci_data_write(phb->bus, phb->config_reg, val, size); 491 492 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 493 status = pci_get_word(d->config + PCI_STATUS); 494 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 495 pci_set_word(d->config + PCI_STATUS, status); 496 } 497 498 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) 499 { 500 PCIBonitoState *s = opaque; 501 PCIDevice *d = PCI_DEVICE(s); 502 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 503 uint32_t pciaddr; 504 uint16_t status; 505 506 DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size); 507 508 pciaddr = bonito_sbridge_pciaddr(s, addr); 509 510 if (pciaddr == 0xffffffff) { 511 return MAKE_64BIT_MASK(0, size * 8); 512 } 513 514 /* set the pci address in s->config_reg */ 515 phb->config_reg = (pciaddr) | (1u << 31); 516 517 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 518 status = pci_get_word(d->config + PCI_STATUS); 519 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 520 pci_set_word(d->config + PCI_STATUS, status); 521 522 return pci_data_read(phb->bus, phb->config_reg, size); 523 } 524 525 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ 526 static const MemoryRegionOps bonito_spciconf_ops = { 527 .read = bonito_spciconf_read, 528 .write = bonito_spciconf_write, 529 .valid.min_access_size = 1, 530 .valid.max_access_size = 4, 531 .impl.min_access_size = 1, 532 .impl.max_access_size = 4, 533 .endianness = DEVICE_NATIVE_ENDIAN, 534 }; 535 536 #define BONITO_IRQ_BASE 32 537 538 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) 539 { 540 BonitoState *s = opaque; 541 qemu_irq *pic = s->pic; 542 PCIBonitoState *bonito_state = s->pci_dev; 543 int internal_irq = irq_num - BONITO_IRQ_BASE; 544 545 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { 546 qemu_irq_pulse(*pic); 547 } else { /* level triggered */ 548 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { 549 qemu_irq_raise(*pic); 550 } else { 551 qemu_irq_lower(*pic); 552 } 553 } 554 } 555 556 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ 557 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num) 558 { 559 int slot; 560 561 slot = (pci_dev->devfn >> 3); 562 563 switch (slot) { 564 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ 565 return irq_num % 4 + BONITO_IRQ_BASE; 566 case 6: /* FULONG2E_ATI_SLOT, VGA */ 567 return 4 + BONITO_IRQ_BASE; 568 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ 569 return 5 + BONITO_IRQ_BASE; 570 case 8 ... 12: /* PCI slot 1 to 4 */ 571 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; 572 default: /* Unknown device, don't do any translation */ 573 return irq_num; 574 } 575 } 576 577 static void bonito_reset(void *opaque) 578 { 579 PCIBonitoState *s = opaque; 580 581 /* set the default value of north bridge registers */ 582 583 s->regs[BONITO_BONPONCFG] = 0xc40; 584 s->regs[BONITO_BONGENCFG] = 0x1384; 585 s->regs[BONITO_IODEVCFG] = 0x2bff8010; 586 s->regs[BONITO_SDCFG] = 0x255e0091; 587 588 s->regs[BONITO_GPIODATA] = 0x1ff; 589 s->regs[BONITO_GPIOIE] = 0x1ff; 590 s->regs[BONITO_DQCFG] = 0x8; 591 s->regs[BONITO_MEMSIZE] = 0x10000000; 592 s->regs[BONITO_PCIMAP] = 0x6140; 593 } 594 595 static const VMStateDescription vmstate_bonito = { 596 .name = "Bonito", 597 .version_id = 1, 598 .minimum_version_id = 1, 599 .fields = (VMStateField[]) { 600 VMSTATE_PCI_DEVICE(dev, PCIBonitoState), 601 VMSTATE_END_OF_LIST() 602 } 603 }; 604 605 static void bonito_pcihost_realize(DeviceState *dev, Error **errp) 606 { 607 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 608 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev); 609 MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3); 610 611 memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE); 612 phb->bus = pci_register_root_bus(dev, "pci", 613 pci_bonito_set_irq, pci_bonito_map_irq, 614 dev, &bs->pci_mem, get_system_io(), 615 0x28, 32, TYPE_PCI_BUS); 616 617 for (size_t i = 0; i < 3; i++) { 618 char *name = g_strdup_printf("pci.lomem%zu", i); 619 620 memory_region_init_alias(&pcimem_lo_alias[i], NULL, name, 621 &bs->pci_mem, i * 64 * MiB, 64 * MiB); 622 memory_region_add_subregion(get_system_memory(), 623 BONITO_PCILO_BASE + i * 64 * MiB, 624 &pcimem_lo_alias[i]); 625 g_free(name); 626 } 627 628 create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB); 629 } 630 631 static void bonito_realize(PCIDevice *dev, Error **errp) 632 { 633 PCIBonitoState *s = PCI_BONITO(dev); 634 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); 635 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 636 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost); 637 MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1); 638 639 /* 640 * Bonito North Bridge, built on FPGA, 641 * VENDOR_ID/DEVICE_ID are "undefined" 642 */ 643 pci_config_set_prog_interface(dev->config, 0x00); 644 645 /* set the north bridge register mapping */ 646 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s, 647 "north-bridge-register", BONITO_INTERNAL_REG_SIZE); 648 sysbus_init_mmio(sysbus, &s->iomem); 649 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); 650 651 /* set the north bridge pci configure mapping */ 652 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s, 653 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); 654 sysbus_init_mmio(sysbus, &phb->conf_mem); 655 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); 656 657 /* set the south bridge pci configure mapping */ 658 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s, 659 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); 660 sysbus_init_mmio(sysbus, &phb->data_mem); 661 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); 662 663 create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE); 664 665 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s, 666 "ldma", 0x100); 667 sysbus_init_mmio(sysbus, &s->iomem_ldma); 668 sysbus_mmio_map(sysbus, 3, 0x1fe00200); 669 670 /* PCI copier */ 671 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s, 672 "cop", 0x100); 673 sysbus_init_mmio(sysbus, &s->iomem_cop); 674 sysbus_mmio_map(sysbus, 4, 0x1fe00300); 675 676 create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB); 677 678 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ 679 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio", 680 get_system_io(), 0, BONITO_PCIIO_SIZE); 681 sysbus_init_mmio(sysbus, &s->bonito_pciio); 682 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE); 683 684 /* add pci local io mapping */ 685 686 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]", 687 get_system_io(), 0, 256 * KiB); 688 sysbus_init_mmio(sysbus, &s->bonito_localio); 689 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE); 690 create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB, 691 256 * KiB); 692 create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB, 693 256 * KiB); 694 create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB, 695 256 * KiB); 696 697 memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias", 698 &bs->pci_mem, 0, BONITO_PCIHI_SIZE); 699 memory_region_add_subregion(get_system_memory(), 700 BONITO_PCIHI_BASE, pcimem_alias); 701 create_unimplemented_device("PCI_2", 702 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE, 703 2 * GiB); 704 705 /* set the default value of north bridge pci config */ 706 pci_set_word(dev->config + PCI_COMMAND, 0x0000); 707 pci_set_word(dev->config + PCI_STATUS, 0x0000); 708 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); 709 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); 710 711 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); 712 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); 713 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); 714 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); 715 716 qemu_register_reset(bonito_reset, s); 717 } 718 719 PCIBus *bonito_init(qemu_irq *pic) 720 { 721 DeviceState *dev; 722 BonitoState *pcihost; 723 PCIHostState *phb; 724 PCIBonitoState *s; 725 PCIDevice *d; 726 727 dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE); 728 phb = PCI_HOST_BRIDGE(dev); 729 pcihost = BONITO_PCI_HOST_BRIDGE(dev); 730 pcihost->pic = pic; 731 qdev_init_nofail(dev); 732 733 d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO); 734 s = PCI_BONITO(d); 735 s->pcihost = pcihost; 736 pcihost->pci_dev = s; 737 qdev_init_nofail(DEVICE(d)); 738 739 return phb->bus; 740 } 741 742 static void bonito_class_init(ObjectClass *klass, void *data) 743 { 744 DeviceClass *dc = DEVICE_CLASS(klass); 745 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 746 747 k->realize = bonito_realize; 748 k->vendor_id = 0xdf53; 749 k->device_id = 0x00d5; 750 k->revision = 0x01; 751 k->class_id = PCI_CLASS_BRIDGE_HOST; 752 dc->desc = "Host bridge"; 753 dc->vmsd = &vmstate_bonito; 754 /* 755 * PCI-facing part of the host bridge, not usable without the 756 * host-facing part, which can't be device_add'ed, yet. 757 */ 758 dc->user_creatable = false; 759 } 760 761 static const TypeInfo bonito_info = { 762 .name = TYPE_PCI_BONITO, 763 .parent = TYPE_PCI_DEVICE, 764 .instance_size = sizeof(PCIBonitoState), 765 .class_init = bonito_class_init, 766 .interfaces = (InterfaceInfo[]) { 767 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 768 { }, 769 }, 770 }; 771 772 static void bonito_pcihost_class_init(ObjectClass *klass, void *data) 773 { 774 DeviceClass *dc = DEVICE_CLASS(klass); 775 776 dc->realize = bonito_pcihost_realize; 777 } 778 779 static const TypeInfo bonito_pcihost_info = { 780 .name = TYPE_BONITO_PCI_HOST_BRIDGE, 781 .parent = TYPE_PCI_HOST_BRIDGE, 782 .instance_size = sizeof(BonitoState), 783 .class_init = bonito_pcihost_class_init, 784 }; 785 786 static void bonito_register_types(void) 787 { 788 type_register_static(&bonito_pcihost_info); 789 type_register_static(&bonito_info); 790 } 791 792 type_init(bonito_register_types) 793