1 /* 2 * bonito north bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 6 * 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 /* 14 * fulong 2e mini pc has a bonito north bridge. 15 */ 16 17 /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? 18 * 19 * devfn pci_slot<<3 + funno 20 * one pci bus can have 32 devices and each device can have 8 functions. 21 * 22 * In bonito north bridge, pci slot = IDSEL bit - 12. 23 * For example, PCI_IDSEL_VIA686B = 17, 24 * pci slot = 17-12=5 25 * 26 * so 27 * VT686B_FUN0's devfn = (5<<3)+0 28 * VT686B_FUN1's devfn = (5<<3)+1 29 * 30 * qemu also uses pci address for north bridge to access pci config register. 31 * bus_no [23:16] 32 * dev_no [15:11] 33 * fun_no [10:8] 34 * reg_no [7:2] 35 * 36 * so function bonito_sbridge_pciaddr for the translation from 37 * north bridge address to pci address. 38 */ 39 40 #include "qemu/osdep.h" 41 #include "qemu/error-report.h" 42 #include "hw/hw.h" 43 #include "hw/pci/pci.h" 44 #include "hw/i386/pc.h" 45 #include "hw/mips/mips.h" 46 #include "hw/pci/pci_host.h" 47 #include "sysemu/reset.h" 48 #include "sysemu/sysemu.h" 49 #include "exec/address-spaces.h" 50 51 //#define DEBUG_BONITO 52 53 #ifdef DEBUG_BONITO 54 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) 55 #else 56 #define DPRINTF(fmt, ...) 57 #endif 58 59 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ 60 #define BONITO_BOOT_BASE 0x1fc00000 61 #define BONITO_BOOT_SIZE 0x00100000 62 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) 63 #define BONITO_FLASH_BASE 0x1c000000 64 #define BONITO_FLASH_SIZE 0x03000000 65 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) 66 #define BONITO_SOCKET_BASE 0x1f800000 67 #define BONITO_SOCKET_SIZE 0x00400000 68 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) 69 #define BONITO_REG_BASE 0x1fe00000 70 #define BONITO_REG_SIZE 0x00040000 71 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) 72 #define BONITO_DEV_BASE 0x1ff00000 73 #define BONITO_DEV_SIZE 0x00100000 74 #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) 75 #define BONITO_PCILO_BASE 0x10000000 76 #define BONITO_PCILO_BASE_VA 0xb0000000 77 #define BONITO_PCILO_SIZE 0x0c000000 78 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) 79 #define BONITO_PCILO0_BASE 0x10000000 80 #define BONITO_PCILO1_BASE 0x14000000 81 #define BONITO_PCILO2_BASE 0x18000000 82 #define BONITO_PCIHI_BASE 0x20000000 83 #define BONITO_PCIHI_SIZE 0x20000000 84 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) 85 #define BONITO_PCIIO_BASE 0x1fd00000 86 #define BONITO_PCIIO_BASE_VA 0xbfd00000 87 #define BONITO_PCIIO_SIZE 0x00010000 88 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) 89 #define BONITO_PCICFG_BASE 0x1fe80000 90 #define BONITO_PCICFG_SIZE 0x00080000 91 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) 92 93 94 #define BONITO_PCICONFIGBASE 0x00 95 #define BONITO_REGBASE 0x100 96 97 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) 98 #define BONITO_PCICONFIG_SIZE (0x100) 99 100 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) 101 #define BONITO_INTERNAL_REG_SIZE (0x70) 102 103 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) 104 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) 105 106 107 108 /* 1. Bonito h/w Configuration */ 109 /* Power on register */ 110 111 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ 112 #define BONITO_BONGENCFG_OFFSET 0x4 113 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ 114 115 /* 2. IO & IDE configuration */ 116 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ 117 118 /* 3. IO & IDE configuration */ 119 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ 120 121 /* 4. PCI address map control */ 122 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ 123 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ 124 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ 125 126 /* 5. ICU & GPIO regs */ 127 /* GPIO Regs - r/w */ 128 #define BONITO_GPIODATA_OFFSET 0x1c 129 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ 130 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ 131 132 /* ICU Configuration Regs - r/w */ 133 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ 134 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ 135 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ 136 137 /* ICU Enable Regs - IntEn & IntISR are r/o. */ 138 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ 139 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ 140 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ 141 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ 142 143 /* PCI mail boxes */ 144 #define BONITO_PCIMAIL0_OFFSET 0x40 145 #define BONITO_PCIMAIL1_OFFSET 0x44 146 #define BONITO_PCIMAIL2_OFFSET 0x48 147 #define BONITO_PCIMAIL3_OFFSET 0x4c 148 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ 149 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ 150 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ 151 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ 152 153 /* 6. PCI cache */ 154 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ 155 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ 156 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ 157 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ 158 159 /* 7. other*/ 160 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ 161 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ 162 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ 163 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ 164 165 #define BONITO_REGS (0x70 >> 2) 166 167 /* PCI config for south bridge. type 0 */ 168 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ 169 #define BONITO_PCICONF_IDSEL_OFFSET 11 170 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ 171 #define BONITO_PCICONF_FUN_OFFSET 8 172 #define BONITO_PCICONF_REG_MASK 0xFC 173 #define BONITO_PCICONF_REG_OFFSET 0 174 175 176 /* idsel BIT = pci slot number +12 */ 177 #define PCI_SLOT_BASE 12 178 #define PCI_IDSEL_VIA686B_BIT (17) 179 #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT) 180 181 #define PCI_ADDR(busno,devno,funno,regno) \ 182 ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) 183 184 typedef struct BonitoState BonitoState; 185 186 typedef struct PCIBonitoState 187 { 188 PCIDevice dev; 189 190 BonitoState *pcihost; 191 uint32_t regs[BONITO_REGS]; 192 193 struct bonldma { 194 uint32_t ldmactrl; 195 uint32_t ldmastat; 196 uint32_t ldmaaddr; 197 uint32_t ldmago; 198 } bonldma; 199 200 /* Based at 1fe00300, bonito Copier */ 201 struct boncop { 202 uint32_t copctrl; 203 uint32_t copstat; 204 uint32_t coppaddr; 205 uint32_t copgo; 206 } boncop; 207 208 /* Bonito registers */ 209 MemoryRegion iomem; 210 MemoryRegion iomem_ldma; 211 MemoryRegion iomem_cop; 212 MemoryRegion bonito_pciio; 213 MemoryRegion bonito_localio; 214 215 } PCIBonitoState; 216 217 struct BonitoState { 218 PCIHostState parent_obj; 219 qemu_irq *pic; 220 PCIBonitoState *pci_dev; 221 MemoryRegion pci_mem; 222 }; 223 224 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" 225 #define BONITO_PCI_HOST_BRIDGE(obj) \ 226 OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) 227 228 #define TYPE_PCI_BONITO "Bonito" 229 #define PCI_BONITO(obj) \ 230 OBJECT_CHECK(PCIBonitoState, (obj), TYPE_PCI_BONITO) 231 232 static void bonito_writel(void *opaque, hwaddr addr, 233 uint64_t val, unsigned size) 234 { 235 PCIBonitoState *s = opaque; 236 uint32_t saddr; 237 int reset = 0; 238 239 saddr = addr >> 2; 240 241 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr); 242 switch (saddr) { 243 case BONITO_BONPONCFG: 244 case BONITO_IODEVCFG: 245 case BONITO_SDCFG: 246 case BONITO_PCIMAP: 247 case BONITO_PCIMEMBASECFG: 248 case BONITO_PCIMAP_CFG: 249 case BONITO_GPIODATA: 250 case BONITO_GPIOIE: 251 case BONITO_INTEDGE: 252 case BONITO_INTSTEER: 253 case BONITO_INTPOL: 254 case BONITO_PCIMAIL0: 255 case BONITO_PCIMAIL1: 256 case BONITO_PCIMAIL2: 257 case BONITO_PCIMAIL3: 258 case BONITO_PCICACHECTRL: 259 case BONITO_PCICACHETAG: 260 case BONITO_PCIBADADDR: 261 case BONITO_PCIMSTAT: 262 case BONITO_TIMECFG: 263 case BONITO_CPUCFG: 264 case BONITO_DQCFG: 265 case BONITO_MEMSIZE: 266 s->regs[saddr] = val; 267 break; 268 case BONITO_BONGENCFG: 269 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { 270 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ 271 } 272 s->regs[saddr] = val; 273 if (reset) { 274 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 275 } 276 break; 277 case BONITO_INTENSET: 278 s->regs[BONITO_INTENSET] = val; 279 s->regs[BONITO_INTEN] |= val; 280 break; 281 case BONITO_INTENCLR: 282 s->regs[BONITO_INTENCLR] = val; 283 s->regs[BONITO_INTEN] &= ~val; 284 break; 285 case BONITO_INTEN: 286 case BONITO_INTISR: 287 DPRINTF("write to readonly bonito register %x\n", saddr); 288 break; 289 default: 290 DPRINTF("write to unknown bonito register %x\n", saddr); 291 break; 292 } 293 } 294 295 static uint64_t bonito_readl(void *opaque, hwaddr addr, 296 unsigned size) 297 { 298 PCIBonitoState *s = opaque; 299 uint32_t saddr; 300 301 saddr = addr >> 2; 302 303 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); 304 switch (saddr) { 305 case BONITO_INTISR: 306 return s->regs[saddr]; 307 default: 308 return s->regs[saddr]; 309 } 310 } 311 312 static const MemoryRegionOps bonito_ops = { 313 .read = bonito_readl, 314 .write = bonito_writel, 315 .endianness = DEVICE_NATIVE_ENDIAN, 316 .valid = { 317 .min_access_size = 4, 318 .max_access_size = 4, 319 }, 320 }; 321 322 static void bonito_pciconf_writel(void *opaque, hwaddr addr, 323 uint64_t val, unsigned size) 324 { 325 PCIBonitoState *s = opaque; 326 PCIDevice *d = PCI_DEVICE(s); 327 328 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 329 d->config_write(d, addr, val, 4); 330 } 331 332 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, 333 unsigned size) 334 { 335 336 PCIBonitoState *s = opaque; 337 PCIDevice *d = PCI_DEVICE(s); 338 339 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); 340 return d->config_read(d, addr, 4); 341 } 342 343 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ 344 345 static const MemoryRegionOps bonito_pciconf_ops = { 346 .read = bonito_pciconf_readl, 347 .write = bonito_pciconf_writel, 348 .endianness = DEVICE_NATIVE_ENDIAN, 349 .valid = { 350 .min_access_size = 4, 351 .max_access_size = 4, 352 }, 353 }; 354 355 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, 356 unsigned size) 357 { 358 uint32_t val; 359 PCIBonitoState *s = opaque; 360 361 if (addr >= sizeof(s->bonldma)) { 362 return 0; 363 } 364 365 val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)]; 366 367 return val; 368 } 369 370 static void bonito_ldma_writel(void *opaque, hwaddr addr, 371 uint64_t val, unsigned size) 372 { 373 PCIBonitoState *s = opaque; 374 375 if (addr >= sizeof(s->bonldma)) { 376 return; 377 } 378 379 ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff; 380 } 381 382 static const MemoryRegionOps bonito_ldma_ops = { 383 .read = bonito_ldma_readl, 384 .write = bonito_ldma_writel, 385 .endianness = DEVICE_NATIVE_ENDIAN, 386 .valid = { 387 .min_access_size = 4, 388 .max_access_size = 4, 389 }, 390 }; 391 392 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, 393 unsigned size) 394 { 395 uint32_t val; 396 PCIBonitoState *s = opaque; 397 398 if (addr >= sizeof(s->boncop)) { 399 return 0; 400 } 401 402 val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)]; 403 404 return val; 405 } 406 407 static void bonito_cop_writel(void *opaque, hwaddr addr, 408 uint64_t val, unsigned size) 409 { 410 PCIBonitoState *s = opaque; 411 412 if (addr >= sizeof(s->boncop)) { 413 return; 414 } 415 416 ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff; 417 } 418 419 static const MemoryRegionOps bonito_cop_ops = { 420 .read = bonito_cop_readl, 421 .write = bonito_cop_writel, 422 .endianness = DEVICE_NATIVE_ENDIAN, 423 .valid = { 424 .min_access_size = 4, 425 .max_access_size = 4, 426 }, 427 }; 428 429 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) 430 { 431 PCIBonitoState *s = opaque; 432 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 433 uint32_t cfgaddr; 434 uint32_t idsel; 435 uint32_t devno; 436 uint32_t funno; 437 uint32_t regno; 438 uint32_t pciaddr; 439 440 /* support type0 pci config */ 441 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { 442 return 0xffffffff; 443 } 444 445 cfgaddr = addr & 0xffff; 446 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; 447 448 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; 449 devno = ctz32(idsel); 450 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; 451 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; 452 453 if (idsel == 0) { 454 error_report("error in bonito pci config address " TARGET_FMT_plx 455 ",pcimap_cfg=%x", addr, s->regs[BONITO_PCIMAP_CFG]); 456 exit(1); 457 } 458 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); 459 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", 460 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); 461 462 return pciaddr; 463 } 464 465 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, 466 unsigned size) 467 { 468 PCIBonitoState *s = opaque; 469 PCIDevice *d = PCI_DEVICE(s); 470 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 471 uint32_t pciaddr; 472 uint16_t status; 473 474 DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %x\n", 475 addr, size, val); 476 477 pciaddr = bonito_sbridge_pciaddr(s, addr); 478 479 if (pciaddr == 0xffffffff) { 480 return; 481 } 482 483 /* set the pci address in s->config_reg */ 484 phb->config_reg = (pciaddr) | (1u << 31); 485 pci_data_write(phb->bus, phb->config_reg, val, size); 486 487 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 488 status = pci_get_word(d->config + PCI_STATUS); 489 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 490 pci_set_word(d->config + PCI_STATUS, status); 491 } 492 493 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) 494 { 495 PCIBonitoState *s = opaque; 496 PCIDevice *d = PCI_DEVICE(s); 497 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 498 uint32_t pciaddr; 499 uint16_t status; 500 501 DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size); 502 503 pciaddr = bonito_sbridge_pciaddr(s, addr); 504 505 if (pciaddr == 0xffffffff) { 506 return MAKE_64BIT_MASK(0, size * 8); 507 } 508 509 /* set the pci address in s->config_reg */ 510 phb->config_reg = (pciaddr) | (1u << 31); 511 512 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 513 status = pci_get_word(d->config + PCI_STATUS); 514 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 515 pci_set_word(d->config + PCI_STATUS, status); 516 517 return pci_data_read(phb->bus, phb->config_reg, size); 518 } 519 520 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ 521 static const MemoryRegionOps bonito_spciconf_ops = { 522 .read = bonito_spciconf_read, 523 .write = bonito_spciconf_write, 524 .valid.min_access_size = 1, 525 .valid.max_access_size = 4, 526 .impl.min_access_size = 1, 527 .impl.max_access_size = 4, 528 .endianness = DEVICE_NATIVE_ENDIAN, 529 }; 530 531 #define BONITO_IRQ_BASE 32 532 533 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) 534 { 535 BonitoState *s = opaque; 536 qemu_irq *pic = s->pic; 537 PCIBonitoState *bonito_state = s->pci_dev; 538 int internal_irq = irq_num - BONITO_IRQ_BASE; 539 540 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { 541 qemu_irq_pulse(*pic); 542 } else { /* level triggered */ 543 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { 544 qemu_irq_raise(*pic); 545 } else { 546 qemu_irq_lower(*pic); 547 } 548 } 549 } 550 551 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ 552 static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num) 553 { 554 int slot; 555 556 slot = (pci_dev->devfn >> 3); 557 558 switch (slot) { 559 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ 560 return irq_num % 4 + BONITO_IRQ_BASE; 561 case 6: /* FULONG2E_ATI_SLOT, VGA */ 562 return 4 + BONITO_IRQ_BASE; 563 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ 564 return 5 + BONITO_IRQ_BASE; 565 case 8 ... 12: /* PCI slot 1 to 4 */ 566 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; 567 default: /* Unknown device, don't do any translation */ 568 return irq_num; 569 } 570 } 571 572 static void bonito_reset(void *opaque) 573 { 574 PCIBonitoState *s = opaque; 575 576 /* set the default value of north bridge registers */ 577 578 s->regs[BONITO_BONPONCFG] = 0xc40; 579 s->regs[BONITO_BONGENCFG] = 0x1384; 580 s->regs[BONITO_IODEVCFG] = 0x2bff8010; 581 s->regs[BONITO_SDCFG] = 0x255e0091; 582 583 s->regs[BONITO_GPIODATA] = 0x1ff; 584 s->regs[BONITO_GPIOIE] = 0x1ff; 585 s->regs[BONITO_DQCFG] = 0x8; 586 s->regs[BONITO_MEMSIZE] = 0x10000000; 587 s->regs[BONITO_PCIMAP] = 0x6140; 588 } 589 590 static const VMStateDescription vmstate_bonito = { 591 .name = "Bonito", 592 .version_id = 1, 593 .minimum_version_id = 1, 594 .fields = (VMStateField[]) { 595 VMSTATE_PCI_DEVICE(dev, PCIBonitoState), 596 VMSTATE_END_OF_LIST() 597 } 598 }; 599 600 static void bonito_pcihost_realize(DeviceState *dev, Error **errp) 601 { 602 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 603 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev); 604 605 memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCILO_SIZE); 606 phb->bus = pci_register_root_bus(DEVICE(dev), "pci", 607 pci_bonito_set_irq, pci_bonito_map_irq, 608 dev, &bs->pci_mem, get_system_io(), 609 0x28, 32, TYPE_PCI_BUS); 610 memory_region_add_subregion(get_system_memory(), BONITO_PCILO_BASE, 611 &bs->pci_mem); 612 } 613 614 static void bonito_realize(PCIDevice *dev, Error **errp) 615 { 616 PCIBonitoState *s = PCI_BONITO(dev); 617 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); 618 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 619 620 /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */ 621 pci_config_set_prog_interface(dev->config, 0x00); 622 623 /* set the north bridge register mapping */ 624 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s, 625 "north-bridge-register", BONITO_INTERNAL_REG_SIZE); 626 sysbus_init_mmio(sysbus, &s->iomem); 627 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); 628 629 /* set the north bridge pci configure mapping */ 630 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s, 631 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); 632 sysbus_init_mmio(sysbus, &phb->conf_mem); 633 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); 634 635 /* set the south bridge pci configure mapping */ 636 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s, 637 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); 638 sysbus_init_mmio(sysbus, &phb->data_mem); 639 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); 640 641 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s, 642 "ldma", 0x100); 643 sysbus_init_mmio(sysbus, &s->iomem_ldma); 644 sysbus_mmio_map(sysbus, 3, 0xbfe00200); 645 646 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s, 647 "cop", 0x100); 648 sysbus_init_mmio(sysbus, &s->iomem_cop); 649 sysbus_mmio_map(sysbus, 4, 0xbfe00300); 650 651 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ 652 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio", 653 get_system_io(), 0, BONITO_PCIIO_SIZE); 654 sysbus_init_mmio(sysbus, &s->bonito_pciio); 655 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE); 656 657 /* add pci local io mapping */ 658 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "isa_mmio", 659 get_system_io(), 0, BONITO_DEV_SIZE); 660 sysbus_init_mmio(sysbus, &s->bonito_localio); 661 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE); 662 663 /* set the default value of north bridge pci config */ 664 pci_set_word(dev->config + PCI_COMMAND, 0x0000); 665 pci_set_word(dev->config + PCI_STATUS, 0x0000); 666 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); 667 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); 668 669 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); 670 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); 671 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); 672 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); 673 674 qemu_register_reset(bonito_reset, s); 675 } 676 677 PCIBus *bonito_init(qemu_irq *pic) 678 { 679 DeviceState *dev; 680 BonitoState *pcihost; 681 PCIHostState *phb; 682 PCIBonitoState *s; 683 PCIDevice *d; 684 685 dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE); 686 phb = PCI_HOST_BRIDGE(dev); 687 pcihost = BONITO_PCI_HOST_BRIDGE(dev); 688 pcihost->pic = pic; 689 qdev_init_nofail(dev); 690 691 d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO); 692 s = PCI_BONITO(d); 693 s->pcihost = pcihost; 694 pcihost->pci_dev = s; 695 qdev_init_nofail(DEVICE(d)); 696 697 return phb->bus; 698 } 699 700 static void bonito_class_init(ObjectClass *klass, void *data) 701 { 702 DeviceClass *dc = DEVICE_CLASS(klass); 703 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 704 705 k->realize = bonito_realize; 706 k->vendor_id = 0xdf53; 707 k->device_id = 0x00d5; 708 k->revision = 0x01; 709 k->class_id = PCI_CLASS_BRIDGE_HOST; 710 dc->desc = "Host bridge"; 711 dc->vmsd = &vmstate_bonito; 712 /* 713 * PCI-facing part of the host bridge, not usable without the 714 * host-facing part, which can't be device_add'ed, yet. 715 */ 716 dc->user_creatable = false; 717 } 718 719 static const TypeInfo bonito_info = { 720 .name = TYPE_PCI_BONITO, 721 .parent = TYPE_PCI_DEVICE, 722 .instance_size = sizeof(PCIBonitoState), 723 .class_init = bonito_class_init, 724 .interfaces = (InterfaceInfo[]) { 725 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 726 { }, 727 }, 728 }; 729 730 static void bonito_pcihost_class_init(ObjectClass *klass, void *data) 731 { 732 DeviceClass *dc = DEVICE_CLASS(klass); 733 734 dc->realize = bonito_pcihost_realize; 735 } 736 737 static const TypeInfo bonito_pcihost_info = { 738 .name = TYPE_BONITO_PCI_HOST_BRIDGE, 739 .parent = TYPE_PCI_HOST_BRIDGE, 740 .instance_size = sizeof(BonitoState), 741 .class_init = bonito_pcihost_class_init, 742 }; 743 744 static void bonito_register_types(void) 745 { 746 type_register_static(&bonito_pcihost_info); 747 type_register_static(&bonito_info); 748 } 749 750 type_init(bonito_register_types) 751