1 /* 2 * bonito north bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 6 * 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 /* 14 * fulong 2e mini pc has a bonito north bridge. 15 */ 16 17 /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? 18 * 19 * devfn pci_slot<<3 + funno 20 * one pci bus can have 32 devices and each device can have 8 functions. 21 * 22 * In bonito north bridge, pci slot = IDSEL bit - 12. 23 * For example, PCI_IDSEL_VIA686B = 17, 24 * pci slot = 17-12=5 25 * 26 * so 27 * VT686B_FUN0's devfn = (5<<3)+0 28 * VT686B_FUN1's devfn = (5<<3)+1 29 * 30 * qemu also uses pci address for north bridge to access pci config register. 31 * bus_no [23:16] 32 * dev_no [15:11] 33 * fun_no [10:8] 34 * reg_no [7:2] 35 * 36 * so function bonito_sbridge_pciaddr for the translation from 37 * north bridge address to pci address. 38 */ 39 40 #include <assert.h> 41 42 #include "hw.h" 43 #include "pci.h" 44 #include "pc.h" 45 #include "mips.h" 46 #include "pci_host.h" 47 #include "sysemu.h" 48 #include "exec-memory.h" 49 50 //#define DEBUG_BONITO 51 52 #ifdef DEBUG_BONITO 53 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) 54 #else 55 #define DPRINTF(fmt, ...) 56 #endif 57 58 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ 59 #define BONITO_BOOT_BASE 0x1fc00000 60 #define BONITO_BOOT_SIZE 0x00100000 61 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) 62 #define BONITO_FLASH_BASE 0x1c000000 63 #define BONITO_FLASH_SIZE 0x03000000 64 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) 65 #define BONITO_SOCKET_BASE 0x1f800000 66 #define BONITO_SOCKET_SIZE 0x00400000 67 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) 68 #define BONITO_REG_BASE 0x1fe00000 69 #define BONITO_REG_SIZE 0x00040000 70 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) 71 #define BONITO_DEV_BASE 0x1ff00000 72 #define BONITO_DEV_SIZE 0x00100000 73 #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) 74 #define BONITO_PCILO_BASE 0x10000000 75 #define BONITO_PCILO_BASE_VA 0xb0000000 76 #define BONITO_PCILO_SIZE 0x0c000000 77 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) 78 #define BONITO_PCILO0_BASE 0x10000000 79 #define BONITO_PCILO1_BASE 0x14000000 80 #define BONITO_PCILO2_BASE 0x18000000 81 #define BONITO_PCIHI_BASE 0x20000000 82 #define BONITO_PCIHI_SIZE 0x20000000 83 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) 84 #define BONITO_PCIIO_BASE 0x1fd00000 85 #define BONITO_PCIIO_BASE_VA 0xbfd00000 86 #define BONITO_PCIIO_SIZE 0x00010000 87 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) 88 #define BONITO_PCICFG_BASE 0x1fe80000 89 #define BONITO_PCICFG_SIZE 0x00080000 90 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) 91 92 93 #define BONITO_PCICONFIGBASE 0x00 94 #define BONITO_REGBASE 0x100 95 96 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) 97 #define BONITO_PCICONFIG_SIZE (0x100) 98 99 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) 100 #define BONITO_INTERNAL_REG_SIZE (0x70) 101 102 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) 103 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) 104 105 106 107 /* 1. Bonito h/w Configuration */ 108 /* Power on register */ 109 110 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ 111 #define BONITO_BONGENCFG_OFFSET 0x4 112 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ 113 114 /* 2. IO & IDE configuration */ 115 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ 116 117 /* 3. IO & IDE configuration */ 118 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ 119 120 /* 4. PCI address map control */ 121 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ 122 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ 123 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ 124 125 /* 5. ICU & GPIO regs */ 126 /* GPIO Regs - r/w */ 127 #define BONITO_GPIODATA_OFFSET 0x1c 128 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ 129 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ 130 131 /* ICU Configuration Regs - r/w */ 132 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ 133 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ 134 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ 135 136 /* ICU Enable Regs - IntEn & IntISR are r/o. */ 137 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ 138 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ 139 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ 140 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ 141 142 /* PCI mail boxes */ 143 #define BONITO_PCIMAIL0_OFFSET 0x40 144 #define BONITO_PCIMAIL1_OFFSET 0x44 145 #define BONITO_PCIMAIL2_OFFSET 0x48 146 #define BONITO_PCIMAIL3_OFFSET 0x4c 147 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ 148 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ 149 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ 150 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ 151 152 /* 6. PCI cache */ 153 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ 154 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ 155 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ 156 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ 157 158 /* 7. other*/ 159 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ 160 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ 161 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ 162 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ 163 164 #define BONITO_REGS (0x70 >> 2) 165 166 /* PCI config for south bridge. type 0 */ 167 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ 168 #define BONITO_PCICONF_IDSEL_OFFSET 11 169 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ 170 #define BONITO_PCICONF_FUN_OFFSET 8 171 #define BONITO_PCICONF_REG_MASK 0xFC 172 #define BONITO_PCICONF_REG_OFFSET 0 173 174 175 /* idsel BIT = pci slot number +12 */ 176 #define PCI_SLOT_BASE 12 177 #define PCI_IDSEL_VIA686B_BIT (17) 178 #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT) 179 180 #define PCI_ADDR(busno,devno,funno,regno) \ 181 ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) 182 183 typedef PCIHostState BonitoState; 184 185 typedef struct PCIBonitoState 186 { 187 PCIDevice dev; 188 BonitoState *pcihost; 189 uint32_t regs[BONITO_REGS]; 190 191 struct bonldma { 192 uint32_t ldmactrl; 193 uint32_t ldmastat; 194 uint32_t ldmaaddr; 195 uint32_t ldmago; 196 } bonldma; 197 198 /* Based at 1fe00300, bonito Copier */ 199 struct boncop { 200 uint32_t copctrl; 201 uint32_t copstat; 202 uint32_t coppaddr; 203 uint32_t copgo; 204 } boncop; 205 206 /* Bonito registers */ 207 MemoryRegion iomem; 208 MemoryRegion iomem_ldma; 209 MemoryRegion iomem_cop; 210 211 target_phys_addr_t bonito_pciio_start; 212 target_phys_addr_t bonito_pciio_length; 213 int bonito_pciio_handle; 214 215 target_phys_addr_t bonito_localio_start; 216 target_phys_addr_t bonito_localio_length; 217 int bonito_localio_handle; 218 219 } PCIBonitoState; 220 221 PCIBonitoState * bonito_state; 222 223 static void bonito_writel(void *opaque, target_phys_addr_t addr, 224 uint64_t val, unsigned size) 225 { 226 PCIBonitoState *s = opaque; 227 uint32_t saddr; 228 int reset = 0; 229 230 saddr = (addr - BONITO_REGBASE) >> 2; 231 232 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr); 233 switch (saddr) { 234 case BONITO_BONPONCFG: 235 case BONITO_IODEVCFG: 236 case BONITO_SDCFG: 237 case BONITO_PCIMAP: 238 case BONITO_PCIMEMBASECFG: 239 case BONITO_PCIMAP_CFG: 240 case BONITO_GPIODATA: 241 case BONITO_GPIOIE: 242 case BONITO_INTEDGE: 243 case BONITO_INTSTEER: 244 case BONITO_INTPOL: 245 case BONITO_PCIMAIL0: 246 case BONITO_PCIMAIL1: 247 case BONITO_PCIMAIL2: 248 case BONITO_PCIMAIL3: 249 case BONITO_PCICACHECTRL: 250 case BONITO_PCICACHETAG: 251 case BONITO_PCIBADADDR: 252 case BONITO_PCIMSTAT: 253 case BONITO_TIMECFG: 254 case BONITO_CPUCFG: 255 case BONITO_DQCFG: 256 case BONITO_MEMSIZE: 257 s->regs[saddr] = val; 258 break; 259 case BONITO_BONGENCFG: 260 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { 261 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ 262 } 263 s->regs[saddr] = val; 264 if (reset) { 265 qemu_system_reset_request(); 266 } 267 break; 268 case BONITO_INTENSET: 269 s->regs[BONITO_INTENSET] = val; 270 s->regs[BONITO_INTEN] |= val; 271 break; 272 case BONITO_INTENCLR: 273 s->regs[BONITO_INTENCLR] = val; 274 s->regs[BONITO_INTEN] &= ~val; 275 break; 276 case BONITO_INTEN: 277 case BONITO_INTISR: 278 DPRINTF("write to readonly bonito register %x\n", saddr); 279 break; 280 default: 281 DPRINTF("write to unknown bonito register %x\n", saddr); 282 break; 283 } 284 } 285 286 static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr, 287 unsigned size) 288 { 289 PCIBonitoState *s = opaque; 290 uint32_t saddr; 291 292 saddr = (addr - BONITO_REGBASE) >> 2; 293 294 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); 295 switch (saddr) { 296 case BONITO_INTISR: 297 return s->regs[saddr]; 298 default: 299 return s->regs[saddr]; 300 } 301 } 302 303 static const MemoryRegionOps bonito_ops = { 304 .read = bonito_readl, 305 .write = bonito_writel, 306 .endianness = DEVICE_NATIVE_ENDIAN, 307 .valid = { 308 .min_access_size = 4, 309 .max_access_size = 4, 310 }, 311 }; 312 313 static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr, 314 uint64_t val, unsigned size) 315 { 316 PCIBonitoState *s = opaque; 317 318 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 319 s->dev.config_write(&s->dev, addr, val, 4); 320 } 321 322 static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr, 323 unsigned size) 324 { 325 326 PCIBonitoState *s = opaque; 327 328 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); 329 return s->dev.config_read(&s->dev, addr, 4); 330 } 331 332 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ 333 334 static const MemoryRegionOps bonito_pciconf_ops = { 335 .read = bonito_pciconf_readl, 336 .write = bonito_pciconf_writel, 337 .endianness = DEVICE_NATIVE_ENDIAN, 338 .valid = { 339 .min_access_size = 4, 340 .max_access_size = 4, 341 }, 342 }; 343 344 static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr, 345 unsigned size) 346 { 347 uint32_t val; 348 PCIBonitoState *s = opaque; 349 350 val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)]; 351 352 return val; 353 } 354 355 static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr, 356 uint64_t val, unsigned size) 357 { 358 PCIBonitoState *s = opaque; 359 360 ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff; 361 } 362 363 static const MemoryRegionOps bonito_ldma_ops = { 364 .read = bonito_ldma_readl, 365 .write = bonito_ldma_writel, 366 .endianness = DEVICE_NATIVE_ENDIAN, 367 .valid = { 368 .min_access_size = 4, 369 .max_access_size = 4, 370 }, 371 }; 372 373 static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr, 374 unsigned size) 375 { 376 uint32_t val; 377 PCIBonitoState *s = opaque; 378 379 val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)]; 380 381 return val; 382 } 383 384 static void bonito_cop_writel(void *opaque, target_phys_addr_t addr, 385 uint64_t val, unsigned size) 386 { 387 PCIBonitoState *s = opaque; 388 389 ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff; 390 } 391 392 static const MemoryRegionOps bonito_cop_ops = { 393 .read = bonito_cop_readl, 394 .write = bonito_cop_writel, 395 .endianness = DEVICE_NATIVE_ENDIAN, 396 .valid = { 397 .min_access_size = 4, 398 .max_access_size = 4, 399 }, 400 }; 401 402 static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr) 403 { 404 PCIBonitoState *s = opaque; 405 uint32_t cfgaddr; 406 uint32_t idsel; 407 uint32_t devno; 408 uint32_t funno; 409 uint32_t regno; 410 uint32_t pciaddr; 411 412 /* support type0 pci config */ 413 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { 414 return 0xffffffff; 415 } 416 417 cfgaddr = addr & 0xffff; 418 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; 419 420 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; 421 devno = ffs(idsel) - 1; 422 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; 423 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; 424 425 if (idsel == 0) { 426 fprintf(stderr, "error in bonito pci config address" TARGET_FMT_plx 427 ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); 428 exit(1); 429 } 430 pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno); 431 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", 432 cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno); 433 434 return pciaddr; 435 } 436 437 static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr, 438 uint32_t val) 439 { 440 PCIBonitoState *s = opaque; 441 uint32_t pciaddr; 442 uint16_t status; 443 444 DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val); 445 pciaddr = bonito_sbridge_pciaddr(s, addr); 446 447 if (pciaddr == 0xffffffff) { 448 return; 449 } 450 451 /* set the pci address in s->config_reg */ 452 s->pcihost->config_reg = (pciaddr) | (1u << 31); 453 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val & 0xff, 1); 454 455 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 456 status = pci_get_word(s->dev.config + PCI_STATUS); 457 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 458 pci_set_word(s->dev.config + PCI_STATUS, status); 459 } 460 461 static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr, 462 uint32_t val) 463 { 464 PCIBonitoState *s = opaque; 465 uint32_t pciaddr; 466 uint16_t status; 467 468 DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val); 469 assert((addr&0x1)==0); 470 471 pciaddr = bonito_sbridge_pciaddr(s, addr); 472 473 if (pciaddr == 0xffffffff) { 474 return; 475 } 476 477 /* set the pci address in s->config_reg */ 478 s->pcihost->config_reg = (pciaddr) | (1u << 31); 479 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 2); 480 481 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 482 status = pci_get_word(s->dev.config + PCI_STATUS); 483 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 484 pci_set_word(s->dev.config + PCI_STATUS, status); 485 } 486 487 static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr, 488 uint32_t val) 489 { 490 PCIBonitoState *s = opaque; 491 uint32_t pciaddr; 492 uint16_t status; 493 494 DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 495 assert((addr&0x3)==0); 496 497 pciaddr = bonito_sbridge_pciaddr(s, addr); 498 499 if (pciaddr == 0xffffffff) { 500 return; 501 } 502 503 /* set the pci address in s->config_reg */ 504 s->pcihost->config_reg = (pciaddr) | (1u << 31); 505 pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4); 506 507 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 508 status = pci_get_word(s->dev.config + PCI_STATUS); 509 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 510 pci_set_word(s->dev.config + PCI_STATUS, status); 511 } 512 513 static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr) 514 { 515 PCIBonitoState *s = opaque; 516 uint32_t pciaddr; 517 uint16_t status; 518 519 DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr); 520 pciaddr = bonito_sbridge_pciaddr(s, addr); 521 522 if (pciaddr == 0xffffffff) { 523 return 0xff; 524 } 525 526 /* set the pci address in s->config_reg */ 527 s->pcihost->config_reg = (pciaddr) | (1u << 31); 528 529 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 530 status = pci_get_word(s->dev.config + PCI_STATUS); 531 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 532 pci_set_word(s->dev.config + PCI_STATUS, status); 533 534 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1); 535 } 536 537 static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr) 538 { 539 PCIBonitoState *s = opaque; 540 uint32_t pciaddr; 541 uint16_t status; 542 543 DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr); 544 assert((addr&0x1)==0); 545 546 pciaddr = bonito_sbridge_pciaddr(s, addr); 547 548 if (pciaddr == 0xffffffff) { 549 return 0xffff; 550 } 551 552 /* set the pci address in s->config_reg */ 553 s->pcihost->config_reg = (pciaddr) | (1u << 31); 554 555 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 556 status = pci_get_word(s->dev.config + PCI_STATUS); 557 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 558 pci_set_word(s->dev.config + PCI_STATUS, status); 559 560 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2); 561 } 562 563 static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr) 564 { 565 PCIBonitoState *s = opaque; 566 uint32_t pciaddr; 567 uint16_t status; 568 569 DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr); 570 assert((addr&0x3) == 0); 571 572 pciaddr = bonito_sbridge_pciaddr(s, addr); 573 574 if (pciaddr == 0xffffffff) { 575 return 0xffffffff; 576 } 577 578 /* set the pci address in s->config_reg */ 579 s->pcihost->config_reg = (pciaddr) | (1u << 31); 580 581 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 582 status = pci_get_word(s->dev.config + PCI_STATUS); 583 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 584 pci_set_word(s->dev.config + PCI_STATUS, status); 585 586 return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 4); 587 } 588 589 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ 590 static const MemoryRegionOps bonito_spciconf_ops = { 591 .old_mmio = { 592 .read = { 593 bonito_spciconf_readb, 594 bonito_spciconf_readw, 595 bonito_spciconf_readl, 596 }, 597 .write = { 598 bonito_spciconf_writeb, 599 bonito_spciconf_writew, 600 bonito_spciconf_writel, 601 }, 602 }, 603 .endianness = DEVICE_NATIVE_ENDIAN, 604 }; 605 606 #define BONITO_IRQ_BASE 32 607 608 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) 609 { 610 qemu_irq *pic = opaque; 611 int internal_irq = irq_num - BONITO_IRQ_BASE; 612 613 if (bonito_state->regs[BONITO_INTEDGE] & (1<<internal_irq)) { 614 qemu_irq_pulse(*pic); 615 } else { /* level triggered */ 616 if (bonito_state->regs[BONITO_INTPOL] & (1<<internal_irq)) { 617 qemu_irq_raise(*pic); 618 } else { 619 qemu_irq_lower(*pic); 620 } 621 } 622 } 623 624 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ 625 static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num) 626 { 627 int slot; 628 629 slot = (pci_dev->devfn >> 3); 630 631 switch (slot) { 632 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ 633 return irq_num % 4 + BONITO_IRQ_BASE; 634 case 6: /* FULONG2E_ATI_SLOT, VGA */ 635 return 4 + BONITO_IRQ_BASE; 636 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ 637 return 5 + BONITO_IRQ_BASE; 638 case 8 ... 12: /* PCI slot 1 to 4 */ 639 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; 640 default: /* Unknown device, don't do any translation */ 641 return irq_num; 642 } 643 } 644 645 static void bonito_reset(void *opaque) 646 { 647 PCIBonitoState *s = opaque; 648 649 /* set the default value of north bridge registers */ 650 651 s->regs[BONITO_BONPONCFG] = 0xc40; 652 s->regs[BONITO_BONGENCFG] = 0x1384; 653 s->regs[BONITO_IODEVCFG] = 0x2bff8010; 654 s->regs[BONITO_SDCFG] = 0x255e0091; 655 656 s->regs[BONITO_GPIODATA] = 0x1ff; 657 s->regs[BONITO_GPIOIE] = 0x1ff; 658 s->regs[BONITO_DQCFG] = 0x8; 659 s->regs[BONITO_MEMSIZE] = 0x10000000; 660 s->regs[BONITO_PCIMAP] = 0x6140; 661 } 662 663 static const VMStateDescription vmstate_bonito = { 664 .name = "Bonito", 665 .version_id = 1, 666 .minimum_version_id = 1, 667 .minimum_version_id_old = 1, 668 .fields = (VMStateField []) { 669 VMSTATE_PCI_DEVICE(dev, PCIBonitoState), 670 VMSTATE_END_OF_LIST() 671 } 672 }; 673 674 static int bonito_pcihost_initfn(SysBusDevice *dev) 675 { 676 return 0; 677 } 678 679 static int bonito_initfn(PCIDevice *dev) 680 { 681 PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev); 682 SysBusDevice *sysbus = &s->pcihost->busdev; 683 684 /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */ 685 pci_config_set_prog_interface(dev->config, 0x00); 686 687 /* set the north bridge register mapping */ 688 memory_region_init_io(&s->iomem, &bonito_ops, s, 689 "north-bridge-register", BONITO_INTERNAL_REG_SIZE); 690 sysbus_init_mmio(sysbus, &s->iomem); 691 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); 692 693 /* set the north bridge pci configure mapping */ 694 memory_region_init_io(&s->pcihost->conf_mem, &bonito_pciconf_ops, s, 695 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); 696 sysbus_init_mmio(sysbus, &s->pcihost->conf_mem); 697 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); 698 699 /* set the south bridge pci configure mapping */ 700 memory_region_init_io(&s->pcihost->data_mem, &bonito_spciconf_ops, s, 701 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); 702 sysbus_init_mmio(sysbus, &s->pcihost->data_mem); 703 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); 704 705 memory_region_init_io(&s->iomem_ldma, &bonito_ldma_ops, s, 706 "ldma", 0x100); 707 sysbus_init_mmio(sysbus, &s->iomem_ldma); 708 sysbus_mmio_map(sysbus, 3, 0xbfe00200); 709 710 memory_region_init_io(&s->iomem_cop, &bonito_cop_ops, s, 711 "cop", 0x100); 712 sysbus_init_mmio(sysbus, &s->iomem_cop); 713 sysbus_mmio_map(sysbus, 4, 0xbfe00300); 714 715 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ 716 s->bonito_pciio_start = BONITO_PCIIO_BASE; 717 s->bonito_pciio_length = BONITO_PCIIO_SIZE; 718 isa_mem_base = s->bonito_pciio_start; 719 isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length); 720 721 /* add pci local io mapping */ 722 s->bonito_localio_start = BONITO_DEV_BASE; 723 s->bonito_localio_length = BONITO_DEV_SIZE; 724 isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length); 725 726 /* set the default value of north bridge pci config */ 727 pci_set_word(dev->config + PCI_COMMAND, 0x0000); 728 pci_set_word(dev->config + PCI_STATUS, 0x0000); 729 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); 730 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); 731 732 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); 733 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); 734 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); 735 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); 736 737 qemu_register_reset(bonito_reset, s); 738 739 return 0; 740 } 741 742 PCIBus *bonito_init(qemu_irq *pic) 743 { 744 DeviceState *dev; 745 PCIBus *b; 746 BonitoState *pcihost; 747 PCIBonitoState *s; 748 PCIDevice *d; 749 750 dev = qdev_create(NULL, "Bonito-pcihost"); 751 pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev)); 752 b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq, 753 pci_bonito_map_irq, pic, get_system_memory(), 754 get_system_io(), 755 0x28, 32); 756 pcihost->bus = b; 757 qdev_init_nofail(dev); 758 759 /* set the pcihost pointer before bonito_initfn is called */ 760 d = pci_create(b, PCI_DEVFN(0, 0), "Bonito"); 761 s = DO_UPCAST(PCIBonitoState, dev, d); 762 s->pcihost = pcihost; 763 bonito_state = s; 764 qdev_init_nofail(&d->qdev); 765 766 return b; 767 } 768 769 static void bonito_class_init(ObjectClass *klass, void *data) 770 { 771 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 772 773 k->init = bonito_initfn; 774 k->vendor_id = 0xdf53; 775 k->device_id = 0x00d5; 776 k->revision = 0x01; 777 k->class_id = PCI_CLASS_BRIDGE_HOST; 778 } 779 780 static DeviceInfo bonito_info = { 781 .name = "Bonito", 782 .desc = "Host bridge", 783 .size = sizeof(PCIBonitoState), 784 .vmsd = &vmstate_bonito, 785 .no_user = 1, 786 .class_init = bonito_class_init, 787 }; 788 789 static SysBusDeviceInfo bonito_pcihost_info = { 790 .init = bonito_pcihost_initfn, 791 .qdev.name = "Bonito-pcihost", 792 .qdev.size = sizeof(BonitoState), 793 .qdev.no_user = 1, 794 }; 795 796 static void bonito_register(void) 797 { 798 sysbus_register_withprop(&bonito_pcihost_info); 799 pci_qdev_register(&bonito_info); 800 } 801 device_init(bonito_register); 802