xref: /qemu/hw/nvme/subsys.c (revision d64db833d6e3cbe9ea5f36342480f920f3675cea) 
1 /*
2  * QEMU NVM Express Subsystem: nvme-subsys
3  *
4  * Copyright (c) 2021 Minwoo Im <minwoo.im.dev@gmail.com>
5  *
6  * This code is licensed under the GNU GPL v2.  Refer COPYING.
7  */
8 
9 #include "qemu/osdep.h"
10 #include "qemu/units.h"
11 #include "qapi/error.h"
12 
13 #include "nvme.h"
14 
15 #define NVME_DEFAULT_RU_SIZE (96 * MiB)
16 
17 static int nvme_subsys_reserve_cntlids(NvmeCtrl *n, int start, int num)
18 {
19     NvmeSubsystem *subsys = n->subsys;
20     NvmeSecCtrlEntry *list = n->sec_ctrl_list;
21     NvmeSecCtrlEntry *sctrl;
22     int i, cnt = 0;
23 
24     for (i = start; i < ARRAY_SIZE(subsys->ctrls) && cnt < num; i++) {
25         if (!subsys->ctrls[i]) {
26             sctrl = &list[cnt];
27             sctrl->scid = cpu_to_le16(i);
28             subsys->ctrls[i] = SUBSYS_SLOT_RSVD;
29             cnt++;
30         }
31     }
32 
33     return cnt;
34 }
35 
36 static void nvme_subsys_unreserve_cntlids(NvmeCtrl *n)
37 {
38     NvmeSubsystem *subsys = n->subsys;
39     NvmeSecCtrlEntry *list = n->sec_ctrl_list;
40     NvmeSecCtrlEntry *sctrl;
41     int i, cntlid;
42 
43     for (i = 0; i < n->params.sriov_max_vfs; i++) {
44         sctrl = &list[i];
45         cntlid = le16_to_cpu(sctrl->scid);
46 
47         if (cntlid) {
48             assert(subsys->ctrls[cntlid] == SUBSYS_SLOT_RSVD);
49             subsys->ctrls[cntlid] = NULL;
50             sctrl->scid = 0;
51         }
52     }
53 }
54 
55 int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp)
56 {
57     NvmeSubsystem *subsys = n->subsys;
58     NvmeSecCtrlEntry *sctrl = nvme_sctrl(n);
59     int cntlid, num_rsvd, num_vfs = n->params.sriov_max_vfs;
60 
61     if (pci_is_vf(&n->parent_obj)) {
62         cntlid = le16_to_cpu(sctrl->scid);
63     } else {
64         n->sec_ctrl_list = g_new0(NvmeSecCtrlEntry, num_vfs);
65 
66         for (cntlid = 0; cntlid < ARRAY_SIZE(subsys->ctrls); cntlid++) {
67             if (!subsys->ctrls[cntlid]) {
68                 break;
69             }
70         }
71 
72         if (cntlid == ARRAY_SIZE(subsys->ctrls)) {
73             error_setg(errp, "no more free controller id");
74             return -1;
75         }
76 
77         num_rsvd = nvme_subsys_reserve_cntlids(n, cntlid + 1, num_vfs);
78         if (num_rsvd != num_vfs) {
79             nvme_subsys_unreserve_cntlids(n);
80             error_setg(errp,
81                        "no more free controller ids for secondary controllers");
82             return -1;
83         }
84     }
85 
86     if (!subsys->serial) {
87         subsys->serial = g_strdup(n->params.serial);
88     } else if (strcmp(subsys->serial, n->params.serial)) {
89         error_setg(errp, "invalid controller serial");
90         return -1;
91     }
92 
93     subsys->ctrls[cntlid] = n;
94 
95     return cntlid;
96 }
97 
98 void nvme_subsys_unregister_ctrl(NvmeSubsystem *subsys, NvmeCtrl *n)
99 {
100     if (pci_is_vf(&n->parent_obj)) {
101         subsys->ctrls[n->cntlid] = SUBSYS_SLOT_RSVD;
102     } else {
103         subsys->ctrls[n->cntlid] = NULL;
104         nvme_subsys_unreserve_cntlids(n);
105     }
106 
107     n->cntlid = -1;
108 }
109 
110 static bool nvme_calc_rgif(uint16_t nruh, uint16_t nrg, uint8_t *rgif)
111 {
112     uint16_t val;
113     unsigned int i;
114 
115     if (unlikely(nrg == 1)) {
116         /* PIDRG_NORGI scenario, all of pid is used for PHID */
117         *rgif = 0;
118         return true;
119     }
120 
121     val = nrg;
122     i = 0;
123     while (val) {
124         val >>= 1;
125         i++;
126     }
127     *rgif = i;
128 
129     /* ensure remaining bits suffice to represent number of phids in a RG */
130     if (unlikely((UINT16_MAX >> i) < nruh)) {
131         *rgif = 0;
132         return false;
133     }
134 
135     return true;
136 }
137 
138 static bool nvme_subsys_setup_fdp(NvmeSubsystem *subsys, Error **errp)
139 {
140     NvmeEnduranceGroup *endgrp = &subsys->endgrp;
141 
142     if (!subsys->params.fdp.runs) {
143         error_setg(errp, "fdp.runs must be non-zero");
144         return false;
145     }
146 
147     endgrp->fdp.runs = subsys->params.fdp.runs;
148 
149     if (!subsys->params.fdp.nrg) {
150         error_setg(errp, "fdp.nrg must be non-zero");
151         return false;
152     }
153 
154     endgrp->fdp.nrg = subsys->params.fdp.nrg;
155 
156     if (!subsys->params.fdp.nruh ||
157         subsys->params.fdp.nruh > NVME_FDP_MAXPIDS) {
158         error_setg(errp, "fdp.nruh must be non-zero and less than %u",
159                    NVME_FDP_MAXPIDS);
160         return false;
161     }
162 
163     endgrp->fdp.nruh = subsys->params.fdp.nruh;
164 
165     if (!nvme_calc_rgif(endgrp->fdp.nruh, endgrp->fdp.nrg, &endgrp->fdp.rgif)) {
166         error_setg(errp,
167                    "cannot derive a valid rgif (nruh %"PRIu16" nrg %"PRIu32")",
168                    endgrp->fdp.nruh, endgrp->fdp.nrg);
169         return false;
170     }
171 
172     endgrp->fdp.ruhs = g_new(NvmeRuHandle, endgrp->fdp.nruh);
173 
174     for (uint16_t ruhid = 0; ruhid < endgrp->fdp.nruh; ruhid++) {
175         endgrp->fdp.ruhs[ruhid] = (NvmeRuHandle) {
176             .ruht = NVME_RUHT_INITIALLY_ISOLATED,
177             .ruha = NVME_RUHA_UNUSED,
178         };
179 
180         endgrp->fdp.ruhs[ruhid].rus = g_new(NvmeReclaimUnit, endgrp->fdp.nrg);
181     }
182 
183     endgrp->fdp.enabled = true;
184 
185     return true;
186 }
187 
188 static bool nvme_subsys_setup(NvmeSubsystem *subsys, Error **errp)
189 {
190     const char *nqn = subsys->params.nqn ?
191         subsys->params.nqn : subsys->parent_obj.id;
192 
193     snprintf((char *)subsys->subnqn, sizeof(subsys->subnqn),
194              "nqn.2019-08.org.qemu:%s", nqn);
195 
196     if (subsys->params.fdp.enabled && !nvme_subsys_setup_fdp(subsys, errp)) {
197         return false;
198     }
199 
200     return true;
201 }
202 
203 static void nvme_subsys_realize(DeviceState *dev, Error **errp)
204 {
205     NvmeSubsystem *subsys = NVME_SUBSYS(dev);
206 
207     qbus_init(&subsys->bus, sizeof(NvmeBus), TYPE_NVME_BUS, dev, dev->id);
208 
209     nvme_subsys_setup(subsys, errp);
210 }
211 
212 static const Property nvme_subsystem_props[] = {
213     DEFINE_PROP_STRING("nqn", NvmeSubsystem, params.nqn),
214     DEFINE_PROP_BOOL("fdp", NvmeSubsystem, params.fdp.enabled, false),
215     DEFINE_PROP_SIZE("fdp.runs", NvmeSubsystem, params.fdp.runs,
216                      NVME_DEFAULT_RU_SIZE),
217     DEFINE_PROP_UINT32("fdp.nrg", NvmeSubsystem, params.fdp.nrg, 1),
218     DEFINE_PROP_UINT16("fdp.nruh", NvmeSubsystem, params.fdp.nruh, 0),
219 };
220 
221 static void nvme_subsys_class_init(ObjectClass *oc, const void *data)
222 {
223     DeviceClass *dc = DEVICE_CLASS(oc);
224 
225     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
226 
227     dc->realize = nvme_subsys_realize;
228     dc->desc = "Virtual NVMe subsystem";
229     dc->hotpluggable = false;
230 
231     device_class_set_props(dc, nvme_subsystem_props);
232 }
233 
234 static const TypeInfo nvme_subsys_info = {
235     .name = TYPE_NVME_SUBSYS,
236     .parent = TYPE_DEVICE,
237     .class_init = nvme_subsys_class_init,
238     .instance_size = sizeof(NvmeSubsystem),
239 };
240 
241 static void nvme_subsys_register_types(void)
242 {
243     type_register_static(&nvme_subsys_info);
244 }
245 
246 type_init(nvme_subsys_register_types)
247