1 /* 2 * QEMU NVM Express Controller 3 * 4 * Copyright (c) 2012, Intel Corporation 5 * 6 * Written by Keith Busch <keith.busch@intel.com> 7 * 8 * This code is licensed under the GNU GPL v2 or later. 9 */ 10 11 /** 12 * Reference Specs: http://www.nvmexpress.org, 1.4, 1.3, 1.2, 1.1, 1.0e 13 * 14 * https://nvmexpress.org/developers/nvme-specification/ 15 * 16 * 17 * Notes on coding style 18 * --------------------- 19 * While QEMU coding style prefers lowercase hexadecimals in constants, the 20 * NVMe subsystem use thes format from the NVMe specifications in the comments 21 * (i.e. 'h' suffix instead of '0x' prefix). 22 * 23 * Usage 24 * ----- 25 * See docs/system/nvme.rst for extensive documentation. 26 * 27 * Add options: 28 * -drive file=<file>,if=none,id=<drive_id> 29 * -device nvme-subsys,id=<subsys_id>,nqn=<nqn_id> 30 * -device nvme,serial=<serial>,id=<bus_name>, \ 31 * cmb_size_mb=<cmb_size_mb[optional]>, \ 32 * [pmrdev=<mem_backend_file_id>,] \ 33 * max_ioqpairs=<N[optional]>, \ 34 * aerl=<N[optional]>,aer_max_queued=<N[optional]>, \ 35 * mdts=<N[optional]>,vsl=<N[optional]>, \ 36 * zoned.zasl=<N[optional]>, \ 37 * zoned.auto_transition=<on|off[optional]>, \ 38 * sriov_max_vfs=<N[optional]> \ 39 * sriov_vq_flexible=<N[optional]> \ 40 * sriov_vi_flexible=<N[optional]> \ 41 * sriov_max_vi_per_vf=<N[optional]> \ 42 * sriov_max_vq_per_vf=<N[optional]> \ 43 * subsys=<subsys_id> 44 * -device nvme-ns,drive=<drive_id>,bus=<bus_name>,nsid=<nsid>,\ 45 * zoned=<true|false[optional]>, \ 46 * subsys=<subsys_id>,detached=<true|false[optional]> 47 * 48 * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at 49 * offset 0 in BAR2 and supports only WDS, RDS and SQS for now. By default, the 50 * device will use the "v1.4 CMB scheme" - use the `legacy-cmb` parameter to 51 * always enable the CMBLOC and CMBSZ registers (v1.3 behavior). 52 * 53 * Enabling pmr emulation can be achieved by pointing to memory-backend-file. 54 * For example: 55 * -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \ 56 * size=<size> .... -device nvme,...,pmrdev=<mem_id> 57 * 58 * The PMR will use BAR 4/5 exclusively. 59 * 60 * To place controller(s) and namespace(s) to a subsystem, then provide 61 * nvme-subsys device as above. 62 * 63 * nvme subsystem device parameters 64 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 65 * - `nqn` 66 * This parameter provides the `<nqn_id>` part of the string 67 * `nqn.2019-08.org.qemu:<nqn_id>` which will be reported in the SUBNQN field 68 * of subsystem controllers. Note that `<nqn_id>` should be unique per 69 * subsystem, but this is not enforced by QEMU. If not specified, it will 70 * default to the value of the `id` parameter (`<subsys_id>`). 71 * 72 * nvme device parameters 73 * ~~~~~~~~~~~~~~~~~~~~~~ 74 * - `subsys` 75 * Specifying this parameter attaches the controller to the subsystem and 76 * the SUBNQN field in the controller will report the NQN of the subsystem 77 * device. This also enables multi controller capability represented in 78 * Identify Controller data structure in CMIC (Controller Multi-path I/O and 79 * Namespace Sharing Capabilities). 80 * 81 * - `aerl` 82 * The Asynchronous Event Request Limit (AERL). Indicates the maximum number 83 * of concurrently outstanding Asynchronous Event Request commands support 84 * by the controller. This is a 0's based value. 85 * 86 * - `aer_max_queued` 87 * This is the maximum number of events that the device will enqueue for 88 * completion when there are no outstanding AERs. When the maximum number of 89 * enqueued events are reached, subsequent events will be dropped. 90 * 91 * - `mdts` 92 * Indicates the maximum data transfer size for a command that transfers data 93 * between host-accessible memory and the controller. The value is specified 94 * as a power of two (2^n) and is in units of the minimum memory page size 95 * (CAP.MPSMIN). The default value is 7 (i.e. 512 KiB). 96 * 97 * - `vsl` 98 * Indicates the maximum data size limit for the Verify command. Like `mdts`, 99 * this value is specified as a power of two (2^n) and is in units of the 100 * minimum memory page size (CAP.MPSMIN). The default value is 7 (i.e. 512 101 * KiB). 102 * 103 * - `zoned.zasl` 104 * Indicates the maximum data transfer size for the Zone Append command. Like 105 * `mdts`, the value is specified as a power of two (2^n) and is in units of 106 * the minimum memory page size (CAP.MPSMIN). The default value is 0 (i.e. 107 * defaulting to the value of `mdts`). 108 * 109 * - `zoned.auto_transition` 110 * Indicates if zones in zone state implicitly opened can be automatically 111 * transitioned to zone state closed for resource management purposes. 112 * Defaults to 'on'. 113 * 114 * - `sriov_max_vfs` 115 * Indicates the maximum number of PCIe virtual functions supported 116 * by the controller. The default value is 0. Specifying a non-zero value 117 * enables reporting of both SR-IOV and ARI capabilities by the NVMe device. 118 * Virtual function controllers will not report SR-IOV capability. 119 * 120 * NOTE: Single Root I/O Virtualization support is experimental. 121 * All the related parameters may be subject to change. 122 * 123 * - `sriov_vq_flexible` 124 * Indicates the total number of flexible queue resources assignable to all 125 * the secondary controllers. Implicitly sets the number of primary 126 * controller's private resources to `(max_ioqpairs - sriov_vq_flexible)`. 127 * 128 * - `sriov_vi_flexible` 129 * Indicates the total number of flexible interrupt resources assignable to 130 * all the secondary controllers. Implicitly sets the number of primary 131 * controller's private resources to `(msix_qsize - sriov_vi_flexible)`. 132 * 133 * - `sriov_max_vi_per_vf` 134 * Indicates the maximum number of virtual interrupt resources assignable 135 * to a secondary controller. The default 0 resolves to 136 * `(sriov_vi_flexible / sriov_max_vfs)`. 137 * 138 * - `sriov_max_vq_per_vf` 139 * Indicates the maximum number of virtual queue resources assignable to 140 * a secondary controller. The default 0 resolves to 141 * `(sriov_vq_flexible / sriov_max_vfs)`. 142 * 143 * nvme namespace device parameters 144 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 145 * - `shared` 146 * When the parent nvme device (as defined explicitly by the 'bus' parameter 147 * or implicitly by the most recently defined NvmeBus) is linked to an 148 * nvme-subsys device, the namespace will be attached to all controllers in 149 * the subsystem. If set to 'off' (the default), the namespace will remain a 150 * private namespace and may only be attached to a single controller at a 151 * time. 152 * 153 * - `detached` 154 * This parameter is only valid together with the `subsys` parameter. If left 155 * at the default value (`false/off`), the namespace will be attached to all 156 * controllers in the NVMe subsystem at boot-up. If set to `true/on`, the 157 * namespace will be available in the subsystem but not attached to any 158 * controllers. 159 * 160 * Setting `zoned` to true selects Zoned Command Set at the namespace. 161 * In this case, the following namespace properties are available to configure 162 * zoned operation: 163 * zoned.zone_size=<zone size in bytes, default: 128MiB> 164 * The number may be followed by K, M, G as in kilo-, mega- or giga-. 165 * 166 * zoned.zone_capacity=<zone capacity in bytes, default: zone size> 167 * The value 0 (default) forces zone capacity to be the same as zone 168 * size. The value of this property may not exceed zone size. 169 * 170 * zoned.descr_ext_size=<zone descriptor extension size, default 0> 171 * This value needs to be specified in 64B units. If it is zero, 172 * namespace(s) will not support zone descriptor extensions. 173 * 174 * zoned.max_active=<Maximum Active Resources (zones), default: 0> 175 * The default value means there is no limit to the number of 176 * concurrently active zones. 177 * 178 * zoned.max_open=<Maximum Open Resources (zones), default: 0> 179 * The default value means there is no limit to the number of 180 * concurrently open zones. 181 * 182 * zoned.cross_read=<enable RAZB, default: false> 183 * Setting this property to true enables Read Across Zone Boundaries. 184 */ 185 186 #include "qemu/osdep.h" 187 #include "qemu/cutils.h" 188 #include "qemu/error-report.h" 189 #include "qemu/log.h" 190 #include "qemu/units.h" 191 #include "qemu/range.h" 192 #include "qapi/error.h" 193 #include "qapi/visitor.h" 194 #include "sysemu/sysemu.h" 195 #include "sysemu/block-backend.h" 196 #include "sysemu/hostmem.h" 197 #include "hw/pci/msix.h" 198 #include "hw/pci/pcie_sriov.h" 199 #include "migration/vmstate.h" 200 201 #include "nvme.h" 202 #include "dif.h" 203 #include "trace.h" 204 205 #define NVME_MAX_IOQPAIRS 0xffff 206 #define NVME_DB_SIZE 4 207 #define NVME_SPEC_VER 0x00010400 208 #define NVME_CMB_BIR 2 209 #define NVME_PMR_BIR 4 210 #define NVME_TEMPERATURE 0x143 211 #define NVME_TEMPERATURE_WARNING 0x157 212 #define NVME_TEMPERATURE_CRITICAL 0x175 213 #define NVME_NUM_FW_SLOTS 1 214 #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) 215 #define NVME_MAX_VFS 127 216 #define NVME_VF_RES_GRANULARITY 1 217 #define NVME_VF_OFFSET 0x1 218 #define NVME_VF_STRIDE 1 219 220 #define NVME_GUEST_ERR(trace, fmt, ...) \ 221 do { \ 222 (trace_##trace)(__VA_ARGS__); \ 223 qemu_log_mask(LOG_GUEST_ERROR, #trace \ 224 " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \ 225 } while (0) 226 227 static const bool nvme_feature_support[NVME_FID_MAX] = { 228 [NVME_ARBITRATION] = true, 229 [NVME_POWER_MANAGEMENT] = true, 230 [NVME_TEMPERATURE_THRESHOLD] = true, 231 [NVME_ERROR_RECOVERY] = true, 232 [NVME_VOLATILE_WRITE_CACHE] = true, 233 [NVME_NUMBER_OF_QUEUES] = true, 234 [NVME_INTERRUPT_COALESCING] = true, 235 [NVME_INTERRUPT_VECTOR_CONF] = true, 236 [NVME_WRITE_ATOMICITY] = true, 237 [NVME_ASYNCHRONOUS_EVENT_CONF] = true, 238 [NVME_TIMESTAMP] = true, 239 [NVME_HOST_BEHAVIOR_SUPPORT] = true, 240 [NVME_COMMAND_SET_PROFILE] = true, 241 }; 242 243 static const uint32_t nvme_feature_cap[NVME_FID_MAX] = { 244 [NVME_TEMPERATURE_THRESHOLD] = NVME_FEAT_CAP_CHANGE, 245 [NVME_ERROR_RECOVERY] = NVME_FEAT_CAP_CHANGE | NVME_FEAT_CAP_NS, 246 [NVME_VOLATILE_WRITE_CACHE] = NVME_FEAT_CAP_CHANGE, 247 [NVME_NUMBER_OF_QUEUES] = NVME_FEAT_CAP_CHANGE, 248 [NVME_ASYNCHRONOUS_EVENT_CONF] = NVME_FEAT_CAP_CHANGE, 249 [NVME_TIMESTAMP] = NVME_FEAT_CAP_CHANGE, 250 [NVME_HOST_BEHAVIOR_SUPPORT] = NVME_FEAT_CAP_CHANGE, 251 [NVME_COMMAND_SET_PROFILE] = NVME_FEAT_CAP_CHANGE, 252 }; 253 254 static const uint32_t nvme_cse_acs[256] = { 255 [NVME_ADM_CMD_DELETE_SQ] = NVME_CMD_EFF_CSUPP, 256 [NVME_ADM_CMD_CREATE_SQ] = NVME_CMD_EFF_CSUPP, 257 [NVME_ADM_CMD_GET_LOG_PAGE] = NVME_CMD_EFF_CSUPP, 258 [NVME_ADM_CMD_DELETE_CQ] = NVME_CMD_EFF_CSUPP, 259 [NVME_ADM_CMD_CREATE_CQ] = NVME_CMD_EFF_CSUPP, 260 [NVME_ADM_CMD_IDENTIFY] = NVME_CMD_EFF_CSUPP, 261 [NVME_ADM_CMD_ABORT] = NVME_CMD_EFF_CSUPP, 262 [NVME_ADM_CMD_SET_FEATURES] = NVME_CMD_EFF_CSUPP, 263 [NVME_ADM_CMD_GET_FEATURES] = NVME_CMD_EFF_CSUPP, 264 [NVME_ADM_CMD_ASYNC_EV_REQ] = NVME_CMD_EFF_CSUPP, 265 [NVME_ADM_CMD_NS_ATTACHMENT] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_NIC, 266 [NVME_ADM_CMD_VIRT_MNGMT] = NVME_CMD_EFF_CSUPP, 267 [NVME_ADM_CMD_DBBUF_CONFIG] = NVME_CMD_EFF_CSUPP, 268 [NVME_ADM_CMD_FORMAT_NVM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 269 }; 270 271 static const uint32_t nvme_cse_iocs_none[256]; 272 273 static const uint32_t nvme_cse_iocs_nvm[256] = { 274 [NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 275 [NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 276 [NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 277 [NVME_CMD_READ] = NVME_CMD_EFF_CSUPP, 278 [NVME_CMD_DSM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 279 [NVME_CMD_VERIFY] = NVME_CMD_EFF_CSUPP, 280 [NVME_CMD_COPY] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 281 [NVME_CMD_COMPARE] = NVME_CMD_EFF_CSUPP, 282 }; 283 284 static const uint32_t nvme_cse_iocs_zoned[256] = { 285 [NVME_CMD_FLUSH] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 286 [NVME_CMD_WRITE_ZEROES] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 287 [NVME_CMD_WRITE] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 288 [NVME_CMD_READ] = NVME_CMD_EFF_CSUPP, 289 [NVME_CMD_DSM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 290 [NVME_CMD_VERIFY] = NVME_CMD_EFF_CSUPP, 291 [NVME_CMD_COPY] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 292 [NVME_CMD_COMPARE] = NVME_CMD_EFF_CSUPP, 293 [NVME_CMD_ZONE_APPEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 294 [NVME_CMD_ZONE_MGMT_SEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, 295 [NVME_CMD_ZONE_MGMT_RECV] = NVME_CMD_EFF_CSUPP, 296 }; 297 298 static void nvme_process_sq(void *opaque); 299 static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst); 300 301 static uint16_t nvme_sqid(NvmeRequest *req) 302 { 303 return le16_to_cpu(req->sq->sqid); 304 } 305 306 static void nvme_assign_zone_state(NvmeNamespace *ns, NvmeZone *zone, 307 NvmeZoneState state) 308 { 309 if (QTAILQ_IN_USE(zone, entry)) { 310 switch (nvme_get_zone_state(zone)) { 311 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 312 QTAILQ_REMOVE(&ns->exp_open_zones, zone, entry); 313 break; 314 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 315 QTAILQ_REMOVE(&ns->imp_open_zones, zone, entry); 316 break; 317 case NVME_ZONE_STATE_CLOSED: 318 QTAILQ_REMOVE(&ns->closed_zones, zone, entry); 319 break; 320 case NVME_ZONE_STATE_FULL: 321 QTAILQ_REMOVE(&ns->full_zones, zone, entry); 322 default: 323 ; 324 } 325 } 326 327 nvme_set_zone_state(zone, state); 328 329 switch (state) { 330 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 331 QTAILQ_INSERT_TAIL(&ns->exp_open_zones, zone, entry); 332 break; 333 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 334 QTAILQ_INSERT_TAIL(&ns->imp_open_zones, zone, entry); 335 break; 336 case NVME_ZONE_STATE_CLOSED: 337 QTAILQ_INSERT_TAIL(&ns->closed_zones, zone, entry); 338 break; 339 case NVME_ZONE_STATE_FULL: 340 QTAILQ_INSERT_TAIL(&ns->full_zones, zone, entry); 341 case NVME_ZONE_STATE_READ_ONLY: 342 break; 343 default: 344 zone->d.za = 0; 345 } 346 } 347 348 static uint16_t nvme_zns_check_resources(NvmeNamespace *ns, uint32_t act, 349 uint32_t opn, uint32_t zrwa) 350 { 351 if (ns->params.max_active_zones != 0 && 352 ns->nr_active_zones + act > ns->params.max_active_zones) { 353 trace_pci_nvme_err_insuff_active_res(ns->params.max_active_zones); 354 return NVME_ZONE_TOO_MANY_ACTIVE | NVME_DNR; 355 } 356 357 if (ns->params.max_open_zones != 0 && 358 ns->nr_open_zones + opn > ns->params.max_open_zones) { 359 trace_pci_nvme_err_insuff_open_res(ns->params.max_open_zones); 360 return NVME_ZONE_TOO_MANY_OPEN | NVME_DNR; 361 } 362 363 if (zrwa > ns->zns.numzrwa) { 364 return NVME_NOZRWA | NVME_DNR; 365 } 366 367 return NVME_SUCCESS; 368 } 369 370 /* 371 * Check if we can open a zone without exceeding open/active limits. 372 * AOR stands for "Active and Open Resources" (see TP 4053 section 2.5). 373 */ 374 static uint16_t nvme_aor_check(NvmeNamespace *ns, uint32_t act, uint32_t opn) 375 { 376 return nvme_zns_check_resources(ns, act, opn, 0); 377 } 378 379 static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) 380 { 381 hwaddr hi, lo; 382 383 if (!n->cmb.cmse) { 384 return false; 385 } 386 387 lo = n->params.legacy_cmb ? n->cmb.mem.addr : n->cmb.cba; 388 hi = lo + int128_get64(n->cmb.mem.size); 389 390 return addr >= lo && addr < hi; 391 } 392 393 static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr) 394 { 395 hwaddr base = n->params.legacy_cmb ? n->cmb.mem.addr : n->cmb.cba; 396 return &n->cmb.buf[addr - base]; 397 } 398 399 static bool nvme_addr_is_pmr(NvmeCtrl *n, hwaddr addr) 400 { 401 hwaddr hi; 402 403 if (!n->pmr.cmse) { 404 return false; 405 } 406 407 hi = n->pmr.cba + int128_get64(n->pmr.dev->mr.size); 408 409 return addr >= n->pmr.cba && addr < hi; 410 } 411 412 static inline void *nvme_addr_to_pmr(NvmeCtrl *n, hwaddr addr) 413 { 414 return memory_region_get_ram_ptr(&n->pmr.dev->mr) + (addr - n->pmr.cba); 415 } 416 417 static inline bool nvme_addr_is_iomem(NvmeCtrl *n, hwaddr addr) 418 { 419 hwaddr hi, lo; 420 421 /* 422 * The purpose of this check is to guard against invalid "local" access to 423 * the iomem (i.e. controller registers). Thus, we check against the range 424 * covered by the 'bar0' MemoryRegion since that is currently composed of 425 * two subregions (the NVMe "MBAR" and the MSI-X table/pba). Note, however, 426 * that if the device model is ever changed to allow the CMB to be located 427 * in BAR0 as well, then this must be changed. 428 */ 429 lo = n->bar0.addr; 430 hi = lo + int128_get64(n->bar0.size); 431 432 return addr >= lo && addr < hi; 433 } 434 435 static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) 436 { 437 hwaddr hi = addr + size - 1; 438 if (hi < addr) { 439 return 1; 440 } 441 442 if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr) && nvme_addr_is_cmb(n, hi)) { 443 memcpy(buf, nvme_addr_to_cmb(n, addr), size); 444 return 0; 445 } 446 447 if (nvme_addr_is_pmr(n, addr) && nvme_addr_is_pmr(n, hi)) { 448 memcpy(buf, nvme_addr_to_pmr(n, addr), size); 449 return 0; 450 } 451 452 return pci_dma_read(&n->parent_obj, addr, buf, size); 453 } 454 455 static int nvme_addr_write(NvmeCtrl *n, hwaddr addr, const void *buf, int size) 456 { 457 hwaddr hi = addr + size - 1; 458 if (hi < addr) { 459 return 1; 460 } 461 462 if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr) && nvme_addr_is_cmb(n, hi)) { 463 memcpy(nvme_addr_to_cmb(n, addr), buf, size); 464 return 0; 465 } 466 467 if (nvme_addr_is_pmr(n, addr) && nvme_addr_is_pmr(n, hi)) { 468 memcpy(nvme_addr_to_pmr(n, addr), buf, size); 469 return 0; 470 } 471 472 return pci_dma_write(&n->parent_obj, addr, buf, size); 473 } 474 475 static bool nvme_nsid_valid(NvmeCtrl *n, uint32_t nsid) 476 { 477 return nsid && 478 (nsid == NVME_NSID_BROADCAST || nsid <= NVME_MAX_NAMESPACES); 479 } 480 481 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) 482 { 483 return sqid < n->conf_ioqpairs + 1 && n->sq[sqid] != NULL ? 0 : -1; 484 } 485 486 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) 487 { 488 return cqid < n->conf_ioqpairs + 1 && n->cq[cqid] != NULL ? 0 : -1; 489 } 490 491 static void nvme_inc_cq_tail(NvmeCQueue *cq) 492 { 493 cq->tail++; 494 if (cq->tail >= cq->size) { 495 cq->tail = 0; 496 cq->phase = !cq->phase; 497 } 498 } 499 500 static void nvme_inc_sq_head(NvmeSQueue *sq) 501 { 502 sq->head = (sq->head + 1) % sq->size; 503 } 504 505 static uint8_t nvme_cq_full(NvmeCQueue *cq) 506 { 507 return (cq->tail + 1) % cq->size == cq->head; 508 } 509 510 static uint8_t nvme_sq_empty(NvmeSQueue *sq) 511 { 512 return sq->head == sq->tail; 513 } 514 515 static void nvme_irq_check(NvmeCtrl *n) 516 { 517 uint32_t intms = ldl_le_p(&n->bar.intms); 518 519 if (msix_enabled(&(n->parent_obj))) { 520 return; 521 } 522 if (~intms & n->irq_status) { 523 pci_irq_assert(&n->parent_obj); 524 } else { 525 pci_irq_deassert(&n->parent_obj); 526 } 527 } 528 529 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq) 530 { 531 if (cq->irq_enabled) { 532 if (msix_enabled(&(n->parent_obj))) { 533 trace_pci_nvme_irq_msix(cq->vector); 534 msix_notify(&(n->parent_obj), cq->vector); 535 } else { 536 trace_pci_nvme_irq_pin(); 537 assert(cq->vector < 32); 538 n->irq_status |= 1 << cq->vector; 539 nvme_irq_check(n); 540 } 541 } else { 542 trace_pci_nvme_irq_masked(); 543 } 544 } 545 546 static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq) 547 { 548 if (cq->irq_enabled) { 549 if (msix_enabled(&(n->parent_obj))) { 550 return; 551 } else { 552 assert(cq->vector < 32); 553 if (!n->cq_pending) { 554 n->irq_status &= ~(1 << cq->vector); 555 } 556 nvme_irq_check(n); 557 } 558 } 559 } 560 561 static void nvme_req_clear(NvmeRequest *req) 562 { 563 req->ns = NULL; 564 req->opaque = NULL; 565 req->aiocb = NULL; 566 memset(&req->cqe, 0x0, sizeof(req->cqe)); 567 req->status = NVME_SUCCESS; 568 } 569 570 static inline void nvme_sg_init(NvmeCtrl *n, NvmeSg *sg, bool dma) 571 { 572 if (dma) { 573 pci_dma_sglist_init(&sg->qsg, &n->parent_obj, 0); 574 sg->flags = NVME_SG_DMA; 575 } else { 576 qemu_iovec_init(&sg->iov, 0); 577 } 578 579 sg->flags |= NVME_SG_ALLOC; 580 } 581 582 static inline void nvme_sg_unmap(NvmeSg *sg) 583 { 584 if (!(sg->flags & NVME_SG_ALLOC)) { 585 return; 586 } 587 588 if (sg->flags & NVME_SG_DMA) { 589 qemu_sglist_destroy(&sg->qsg); 590 } else { 591 qemu_iovec_destroy(&sg->iov); 592 } 593 594 memset(sg, 0x0, sizeof(*sg)); 595 } 596 597 /* 598 * When metadata is transfered as extended LBAs, the DPTR mapped into `sg` 599 * holds both data and metadata. This function splits the data and metadata 600 * into two separate QSG/IOVs. 601 */ 602 static void nvme_sg_split(NvmeSg *sg, NvmeNamespace *ns, NvmeSg *data, 603 NvmeSg *mdata) 604 { 605 NvmeSg *dst = data; 606 uint32_t trans_len, count = ns->lbasz; 607 uint64_t offset = 0; 608 bool dma = sg->flags & NVME_SG_DMA; 609 size_t sge_len; 610 size_t sg_len = dma ? sg->qsg.size : sg->iov.size; 611 int sg_idx = 0; 612 613 assert(sg->flags & NVME_SG_ALLOC); 614 615 while (sg_len) { 616 sge_len = dma ? sg->qsg.sg[sg_idx].len : sg->iov.iov[sg_idx].iov_len; 617 618 trans_len = MIN(sg_len, count); 619 trans_len = MIN(trans_len, sge_len - offset); 620 621 if (dst) { 622 if (dma) { 623 qemu_sglist_add(&dst->qsg, sg->qsg.sg[sg_idx].base + offset, 624 trans_len); 625 } else { 626 qemu_iovec_add(&dst->iov, 627 sg->iov.iov[sg_idx].iov_base + offset, 628 trans_len); 629 } 630 } 631 632 sg_len -= trans_len; 633 count -= trans_len; 634 offset += trans_len; 635 636 if (count == 0) { 637 dst = (dst == data) ? mdata : data; 638 count = (dst == data) ? ns->lbasz : ns->lbaf.ms; 639 } 640 641 if (sge_len == offset) { 642 offset = 0; 643 sg_idx++; 644 } 645 } 646 } 647 648 static uint16_t nvme_map_addr_cmb(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr, 649 size_t len) 650 { 651 if (!len) { 652 return NVME_SUCCESS; 653 } 654 655 trace_pci_nvme_map_addr_cmb(addr, len); 656 657 if (!nvme_addr_is_cmb(n, addr) || !nvme_addr_is_cmb(n, addr + len - 1)) { 658 return NVME_DATA_TRAS_ERROR; 659 } 660 661 qemu_iovec_add(iov, nvme_addr_to_cmb(n, addr), len); 662 663 return NVME_SUCCESS; 664 } 665 666 static uint16_t nvme_map_addr_pmr(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr, 667 size_t len) 668 { 669 if (!len) { 670 return NVME_SUCCESS; 671 } 672 673 if (!nvme_addr_is_pmr(n, addr) || !nvme_addr_is_pmr(n, addr + len - 1)) { 674 return NVME_DATA_TRAS_ERROR; 675 } 676 677 qemu_iovec_add(iov, nvme_addr_to_pmr(n, addr), len); 678 679 return NVME_SUCCESS; 680 } 681 682 static uint16_t nvme_map_addr(NvmeCtrl *n, NvmeSg *sg, hwaddr addr, size_t len) 683 { 684 bool cmb = false, pmr = false; 685 686 if (!len) { 687 return NVME_SUCCESS; 688 } 689 690 trace_pci_nvme_map_addr(addr, len); 691 692 if (nvme_addr_is_iomem(n, addr)) { 693 return NVME_DATA_TRAS_ERROR; 694 } 695 696 if (nvme_addr_is_cmb(n, addr)) { 697 cmb = true; 698 } else if (nvme_addr_is_pmr(n, addr)) { 699 pmr = true; 700 } 701 702 if (cmb || pmr) { 703 if (sg->flags & NVME_SG_DMA) { 704 return NVME_INVALID_USE_OF_CMB | NVME_DNR; 705 } 706 707 if (sg->iov.niov + 1 > IOV_MAX) { 708 goto max_mappings_exceeded; 709 } 710 711 if (cmb) { 712 return nvme_map_addr_cmb(n, &sg->iov, addr, len); 713 } else { 714 return nvme_map_addr_pmr(n, &sg->iov, addr, len); 715 } 716 } 717 718 if (!(sg->flags & NVME_SG_DMA)) { 719 return NVME_INVALID_USE_OF_CMB | NVME_DNR; 720 } 721 722 if (sg->qsg.nsg + 1 > IOV_MAX) { 723 goto max_mappings_exceeded; 724 } 725 726 qemu_sglist_add(&sg->qsg, addr, len); 727 728 return NVME_SUCCESS; 729 730 max_mappings_exceeded: 731 NVME_GUEST_ERR(pci_nvme_ub_too_many_mappings, 732 "number of mappings exceed 1024"); 733 return NVME_INTERNAL_DEV_ERROR | NVME_DNR; 734 } 735 736 static inline bool nvme_addr_is_dma(NvmeCtrl *n, hwaddr addr) 737 { 738 return !(nvme_addr_is_cmb(n, addr) || nvme_addr_is_pmr(n, addr)); 739 } 740 741 static uint16_t nvme_map_prp(NvmeCtrl *n, NvmeSg *sg, uint64_t prp1, 742 uint64_t prp2, uint32_t len) 743 { 744 hwaddr trans_len = n->page_size - (prp1 % n->page_size); 745 trans_len = MIN(len, trans_len); 746 int num_prps = (len >> n->page_bits) + 1; 747 uint16_t status; 748 int ret; 749 750 trace_pci_nvme_map_prp(trans_len, len, prp1, prp2, num_prps); 751 752 nvme_sg_init(n, sg, nvme_addr_is_dma(n, prp1)); 753 754 status = nvme_map_addr(n, sg, prp1, trans_len); 755 if (status) { 756 goto unmap; 757 } 758 759 len -= trans_len; 760 if (len) { 761 if (len > n->page_size) { 762 uint64_t prp_list[n->max_prp_ents]; 763 uint32_t nents, prp_trans; 764 int i = 0; 765 766 /* 767 * The first PRP list entry, pointed to by PRP2 may contain offset. 768 * Hence, we need to calculate the number of entries in based on 769 * that offset. 770 */ 771 nents = (n->page_size - (prp2 & (n->page_size - 1))) >> 3; 772 prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t); 773 ret = nvme_addr_read(n, prp2, (void *)prp_list, prp_trans); 774 if (ret) { 775 trace_pci_nvme_err_addr_read(prp2); 776 status = NVME_DATA_TRAS_ERROR; 777 goto unmap; 778 } 779 while (len != 0) { 780 uint64_t prp_ent = le64_to_cpu(prp_list[i]); 781 782 if (i == nents - 1 && len > n->page_size) { 783 if (unlikely(prp_ent & (n->page_size - 1))) { 784 trace_pci_nvme_err_invalid_prplist_ent(prp_ent); 785 status = NVME_INVALID_PRP_OFFSET | NVME_DNR; 786 goto unmap; 787 } 788 789 i = 0; 790 nents = (len + n->page_size - 1) >> n->page_bits; 791 nents = MIN(nents, n->max_prp_ents); 792 prp_trans = nents * sizeof(uint64_t); 793 ret = nvme_addr_read(n, prp_ent, (void *)prp_list, 794 prp_trans); 795 if (ret) { 796 trace_pci_nvme_err_addr_read(prp_ent); 797 status = NVME_DATA_TRAS_ERROR; 798 goto unmap; 799 } 800 prp_ent = le64_to_cpu(prp_list[i]); 801 } 802 803 if (unlikely(prp_ent & (n->page_size - 1))) { 804 trace_pci_nvme_err_invalid_prplist_ent(prp_ent); 805 status = NVME_INVALID_PRP_OFFSET | NVME_DNR; 806 goto unmap; 807 } 808 809 trans_len = MIN(len, n->page_size); 810 status = nvme_map_addr(n, sg, prp_ent, trans_len); 811 if (status) { 812 goto unmap; 813 } 814 815 len -= trans_len; 816 i++; 817 } 818 } else { 819 if (unlikely(prp2 & (n->page_size - 1))) { 820 trace_pci_nvme_err_invalid_prp2_align(prp2); 821 status = NVME_INVALID_PRP_OFFSET | NVME_DNR; 822 goto unmap; 823 } 824 status = nvme_map_addr(n, sg, prp2, len); 825 if (status) { 826 goto unmap; 827 } 828 } 829 } 830 831 return NVME_SUCCESS; 832 833 unmap: 834 nvme_sg_unmap(sg); 835 return status; 836 } 837 838 /* 839 * Map 'nsgld' data descriptors from 'segment'. The function will subtract the 840 * number of bytes mapped in len. 841 */ 842 static uint16_t nvme_map_sgl_data(NvmeCtrl *n, NvmeSg *sg, 843 NvmeSglDescriptor *segment, uint64_t nsgld, 844 size_t *len, NvmeCmd *cmd) 845 { 846 dma_addr_t addr, trans_len; 847 uint32_t dlen; 848 uint16_t status; 849 850 for (int i = 0; i < nsgld; i++) { 851 uint8_t type = NVME_SGL_TYPE(segment[i].type); 852 853 switch (type) { 854 case NVME_SGL_DESCR_TYPE_DATA_BLOCK: 855 break; 856 case NVME_SGL_DESCR_TYPE_SEGMENT: 857 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT: 858 return NVME_INVALID_NUM_SGL_DESCRS | NVME_DNR; 859 default: 860 return NVME_SGL_DESCR_TYPE_INVALID | NVME_DNR; 861 } 862 863 dlen = le32_to_cpu(segment[i].len); 864 865 if (!dlen) { 866 continue; 867 } 868 869 if (*len == 0) { 870 /* 871 * All data has been mapped, but the SGL contains additional 872 * segments and/or descriptors. The controller might accept 873 * ignoring the rest of the SGL. 874 */ 875 uint32_t sgls = le32_to_cpu(n->id_ctrl.sgls); 876 if (sgls & NVME_CTRL_SGLS_EXCESS_LENGTH) { 877 break; 878 } 879 880 trace_pci_nvme_err_invalid_sgl_excess_length(dlen); 881 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR; 882 } 883 884 trans_len = MIN(*len, dlen); 885 886 addr = le64_to_cpu(segment[i].addr); 887 888 if (UINT64_MAX - addr < dlen) { 889 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR; 890 } 891 892 status = nvme_map_addr(n, sg, addr, trans_len); 893 if (status) { 894 return status; 895 } 896 897 *len -= trans_len; 898 } 899 900 return NVME_SUCCESS; 901 } 902 903 static uint16_t nvme_map_sgl(NvmeCtrl *n, NvmeSg *sg, NvmeSglDescriptor sgl, 904 size_t len, NvmeCmd *cmd) 905 { 906 /* 907 * Read the segment in chunks of 256 descriptors (one 4k page) to avoid 908 * dynamically allocating a potentially huge SGL. The spec allows the SGL 909 * to be larger (as in number of bytes required to describe the SGL 910 * descriptors and segment chain) than the command transfer size, so it is 911 * not bounded by MDTS. 912 */ 913 const int SEG_CHUNK_SIZE = 256; 914 915 NvmeSglDescriptor segment[SEG_CHUNK_SIZE], *sgld, *last_sgld; 916 uint64_t nsgld; 917 uint32_t seg_len; 918 uint16_t status; 919 hwaddr addr; 920 int ret; 921 922 sgld = &sgl; 923 addr = le64_to_cpu(sgl.addr); 924 925 trace_pci_nvme_map_sgl(NVME_SGL_TYPE(sgl.type), len); 926 927 nvme_sg_init(n, sg, nvme_addr_is_dma(n, addr)); 928 929 /* 930 * If the entire transfer can be described with a single data block it can 931 * be mapped directly. 932 */ 933 if (NVME_SGL_TYPE(sgl.type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) { 934 status = nvme_map_sgl_data(n, sg, sgld, 1, &len, cmd); 935 if (status) { 936 goto unmap; 937 } 938 939 goto out; 940 } 941 942 for (;;) { 943 switch (NVME_SGL_TYPE(sgld->type)) { 944 case NVME_SGL_DESCR_TYPE_SEGMENT: 945 case NVME_SGL_DESCR_TYPE_LAST_SEGMENT: 946 break; 947 default: 948 return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR; 949 } 950 951 seg_len = le32_to_cpu(sgld->len); 952 953 /* check the length of the (Last) Segment descriptor */ 954 if (!seg_len || seg_len & 0xf) { 955 return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR; 956 } 957 958 if (UINT64_MAX - addr < seg_len) { 959 return NVME_DATA_SGL_LEN_INVALID | NVME_DNR; 960 } 961 962 nsgld = seg_len / sizeof(NvmeSglDescriptor); 963 964 while (nsgld > SEG_CHUNK_SIZE) { 965 if (nvme_addr_read(n, addr, segment, sizeof(segment))) { 966 trace_pci_nvme_err_addr_read(addr); 967 status = NVME_DATA_TRAS_ERROR; 968 goto unmap; 969 } 970 971 status = nvme_map_sgl_data(n, sg, segment, SEG_CHUNK_SIZE, 972 &len, cmd); 973 if (status) { 974 goto unmap; 975 } 976 977 nsgld -= SEG_CHUNK_SIZE; 978 addr += SEG_CHUNK_SIZE * sizeof(NvmeSglDescriptor); 979 } 980 981 ret = nvme_addr_read(n, addr, segment, nsgld * 982 sizeof(NvmeSglDescriptor)); 983 if (ret) { 984 trace_pci_nvme_err_addr_read(addr); 985 status = NVME_DATA_TRAS_ERROR; 986 goto unmap; 987 } 988 989 last_sgld = &segment[nsgld - 1]; 990 991 /* 992 * If the segment ends with a Data Block, then we are done. 993 */ 994 if (NVME_SGL_TYPE(last_sgld->type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) { 995 status = nvme_map_sgl_data(n, sg, segment, nsgld, &len, cmd); 996 if (status) { 997 goto unmap; 998 } 999 1000 goto out; 1001 } 1002 1003 /* 1004 * If the last descriptor was not a Data Block, then the current 1005 * segment must not be a Last Segment. 1006 */ 1007 if (NVME_SGL_TYPE(sgld->type) == NVME_SGL_DESCR_TYPE_LAST_SEGMENT) { 1008 status = NVME_INVALID_SGL_SEG_DESCR | NVME_DNR; 1009 goto unmap; 1010 } 1011 1012 sgld = last_sgld; 1013 addr = le64_to_cpu(sgld->addr); 1014 1015 /* 1016 * Do not map the last descriptor; it will be a Segment or Last Segment 1017 * descriptor and is handled by the next iteration. 1018 */ 1019 status = nvme_map_sgl_data(n, sg, segment, nsgld - 1, &len, cmd); 1020 if (status) { 1021 goto unmap; 1022 } 1023 } 1024 1025 out: 1026 /* if there is any residual left in len, the SGL was too short */ 1027 if (len) { 1028 status = NVME_DATA_SGL_LEN_INVALID | NVME_DNR; 1029 goto unmap; 1030 } 1031 1032 return NVME_SUCCESS; 1033 1034 unmap: 1035 nvme_sg_unmap(sg); 1036 return status; 1037 } 1038 1039 uint16_t nvme_map_dptr(NvmeCtrl *n, NvmeSg *sg, size_t len, 1040 NvmeCmd *cmd) 1041 { 1042 uint64_t prp1, prp2; 1043 1044 switch (NVME_CMD_FLAGS_PSDT(cmd->flags)) { 1045 case NVME_PSDT_PRP: 1046 prp1 = le64_to_cpu(cmd->dptr.prp1); 1047 prp2 = le64_to_cpu(cmd->dptr.prp2); 1048 1049 return nvme_map_prp(n, sg, prp1, prp2, len); 1050 case NVME_PSDT_SGL_MPTR_CONTIGUOUS: 1051 case NVME_PSDT_SGL_MPTR_SGL: 1052 return nvme_map_sgl(n, sg, cmd->dptr.sgl, len, cmd); 1053 default: 1054 return NVME_INVALID_FIELD; 1055 } 1056 } 1057 1058 static uint16_t nvme_map_mptr(NvmeCtrl *n, NvmeSg *sg, size_t len, 1059 NvmeCmd *cmd) 1060 { 1061 int psdt = NVME_CMD_FLAGS_PSDT(cmd->flags); 1062 hwaddr mptr = le64_to_cpu(cmd->mptr); 1063 uint16_t status; 1064 1065 if (psdt == NVME_PSDT_SGL_MPTR_SGL) { 1066 NvmeSglDescriptor sgl; 1067 1068 if (nvme_addr_read(n, mptr, &sgl, sizeof(sgl))) { 1069 return NVME_DATA_TRAS_ERROR; 1070 } 1071 1072 status = nvme_map_sgl(n, sg, sgl, len, cmd); 1073 if (status && (status & 0x7ff) == NVME_DATA_SGL_LEN_INVALID) { 1074 status = NVME_MD_SGL_LEN_INVALID | NVME_DNR; 1075 } 1076 1077 return status; 1078 } 1079 1080 nvme_sg_init(n, sg, nvme_addr_is_dma(n, mptr)); 1081 status = nvme_map_addr(n, sg, mptr, len); 1082 if (status) { 1083 nvme_sg_unmap(sg); 1084 } 1085 1086 return status; 1087 } 1088 1089 static uint16_t nvme_map_data(NvmeCtrl *n, uint32_t nlb, NvmeRequest *req) 1090 { 1091 NvmeNamespace *ns = req->ns; 1092 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 1093 bool pi = !!NVME_ID_NS_DPS_TYPE(ns->id_ns.dps); 1094 bool pract = !!(le16_to_cpu(rw->control) & NVME_RW_PRINFO_PRACT); 1095 size_t len = nvme_l2b(ns, nlb); 1096 uint16_t status; 1097 1098 if (nvme_ns_ext(ns) && 1099 !(pi && pract && ns->lbaf.ms == nvme_pi_tuple_size(ns))) { 1100 NvmeSg sg; 1101 1102 len += nvme_m2b(ns, nlb); 1103 1104 status = nvme_map_dptr(n, &sg, len, &req->cmd); 1105 if (status) { 1106 return status; 1107 } 1108 1109 nvme_sg_init(n, &req->sg, sg.flags & NVME_SG_DMA); 1110 nvme_sg_split(&sg, ns, &req->sg, NULL); 1111 nvme_sg_unmap(&sg); 1112 1113 return NVME_SUCCESS; 1114 } 1115 1116 return nvme_map_dptr(n, &req->sg, len, &req->cmd); 1117 } 1118 1119 static uint16_t nvme_map_mdata(NvmeCtrl *n, uint32_t nlb, NvmeRequest *req) 1120 { 1121 NvmeNamespace *ns = req->ns; 1122 size_t len = nvme_m2b(ns, nlb); 1123 uint16_t status; 1124 1125 if (nvme_ns_ext(ns)) { 1126 NvmeSg sg; 1127 1128 len += nvme_l2b(ns, nlb); 1129 1130 status = nvme_map_dptr(n, &sg, len, &req->cmd); 1131 if (status) { 1132 return status; 1133 } 1134 1135 nvme_sg_init(n, &req->sg, sg.flags & NVME_SG_DMA); 1136 nvme_sg_split(&sg, ns, NULL, &req->sg); 1137 nvme_sg_unmap(&sg); 1138 1139 return NVME_SUCCESS; 1140 } 1141 1142 return nvme_map_mptr(n, &req->sg, len, &req->cmd); 1143 } 1144 1145 static uint16_t nvme_tx_interleaved(NvmeCtrl *n, NvmeSg *sg, uint8_t *ptr, 1146 uint32_t len, uint32_t bytes, 1147 int32_t skip_bytes, int64_t offset, 1148 NvmeTxDirection dir) 1149 { 1150 hwaddr addr; 1151 uint32_t trans_len, count = bytes; 1152 bool dma = sg->flags & NVME_SG_DMA; 1153 int64_t sge_len; 1154 int sg_idx = 0; 1155 int ret; 1156 1157 assert(sg->flags & NVME_SG_ALLOC); 1158 1159 while (len) { 1160 sge_len = dma ? sg->qsg.sg[sg_idx].len : sg->iov.iov[sg_idx].iov_len; 1161 1162 if (sge_len - offset < 0) { 1163 offset -= sge_len; 1164 sg_idx++; 1165 continue; 1166 } 1167 1168 if (sge_len == offset) { 1169 offset = 0; 1170 sg_idx++; 1171 continue; 1172 } 1173 1174 trans_len = MIN(len, count); 1175 trans_len = MIN(trans_len, sge_len - offset); 1176 1177 if (dma) { 1178 addr = sg->qsg.sg[sg_idx].base + offset; 1179 } else { 1180 addr = (hwaddr)(uintptr_t)sg->iov.iov[sg_idx].iov_base + offset; 1181 } 1182 1183 if (dir == NVME_TX_DIRECTION_TO_DEVICE) { 1184 ret = nvme_addr_read(n, addr, ptr, trans_len); 1185 } else { 1186 ret = nvme_addr_write(n, addr, ptr, trans_len); 1187 } 1188 1189 if (ret) { 1190 return NVME_DATA_TRAS_ERROR; 1191 } 1192 1193 ptr += trans_len; 1194 len -= trans_len; 1195 count -= trans_len; 1196 offset += trans_len; 1197 1198 if (count == 0) { 1199 count = bytes; 1200 offset += skip_bytes; 1201 } 1202 } 1203 1204 return NVME_SUCCESS; 1205 } 1206 1207 static uint16_t nvme_tx(NvmeCtrl *n, NvmeSg *sg, void *ptr, uint32_t len, 1208 NvmeTxDirection dir) 1209 { 1210 assert(sg->flags & NVME_SG_ALLOC); 1211 1212 if (sg->flags & NVME_SG_DMA) { 1213 const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; 1214 dma_addr_t residual; 1215 1216 if (dir == NVME_TX_DIRECTION_TO_DEVICE) { 1217 dma_buf_write(ptr, len, &residual, &sg->qsg, attrs); 1218 } else { 1219 dma_buf_read(ptr, len, &residual, &sg->qsg, attrs); 1220 } 1221 1222 if (unlikely(residual)) { 1223 trace_pci_nvme_err_invalid_dma(); 1224 return NVME_INVALID_FIELD | NVME_DNR; 1225 } 1226 } else { 1227 size_t bytes; 1228 1229 if (dir == NVME_TX_DIRECTION_TO_DEVICE) { 1230 bytes = qemu_iovec_to_buf(&sg->iov, 0, ptr, len); 1231 } else { 1232 bytes = qemu_iovec_from_buf(&sg->iov, 0, ptr, len); 1233 } 1234 1235 if (unlikely(bytes != len)) { 1236 trace_pci_nvme_err_invalid_dma(); 1237 return NVME_INVALID_FIELD | NVME_DNR; 1238 } 1239 } 1240 1241 return NVME_SUCCESS; 1242 } 1243 1244 static inline uint16_t nvme_c2h(NvmeCtrl *n, void *ptr, uint32_t len, 1245 NvmeRequest *req) 1246 { 1247 uint16_t status; 1248 1249 status = nvme_map_dptr(n, &req->sg, len, &req->cmd); 1250 if (status) { 1251 return status; 1252 } 1253 1254 return nvme_tx(n, &req->sg, ptr, len, NVME_TX_DIRECTION_FROM_DEVICE); 1255 } 1256 1257 static inline uint16_t nvme_h2c(NvmeCtrl *n, void *ptr, uint32_t len, 1258 NvmeRequest *req) 1259 { 1260 uint16_t status; 1261 1262 status = nvme_map_dptr(n, &req->sg, len, &req->cmd); 1263 if (status) { 1264 return status; 1265 } 1266 1267 return nvme_tx(n, &req->sg, ptr, len, NVME_TX_DIRECTION_TO_DEVICE); 1268 } 1269 1270 uint16_t nvme_bounce_data(NvmeCtrl *n, void *ptr, uint32_t len, 1271 NvmeTxDirection dir, NvmeRequest *req) 1272 { 1273 NvmeNamespace *ns = req->ns; 1274 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 1275 bool pi = !!NVME_ID_NS_DPS_TYPE(ns->id_ns.dps); 1276 bool pract = !!(le16_to_cpu(rw->control) & NVME_RW_PRINFO_PRACT); 1277 1278 if (nvme_ns_ext(ns) && 1279 !(pi && pract && ns->lbaf.ms == nvme_pi_tuple_size(ns))) { 1280 return nvme_tx_interleaved(n, &req->sg, ptr, len, ns->lbasz, 1281 ns->lbaf.ms, 0, dir); 1282 } 1283 1284 return nvme_tx(n, &req->sg, ptr, len, dir); 1285 } 1286 1287 uint16_t nvme_bounce_mdata(NvmeCtrl *n, void *ptr, uint32_t len, 1288 NvmeTxDirection dir, NvmeRequest *req) 1289 { 1290 NvmeNamespace *ns = req->ns; 1291 uint16_t status; 1292 1293 if (nvme_ns_ext(ns)) { 1294 return nvme_tx_interleaved(n, &req->sg, ptr, len, ns->lbaf.ms, 1295 ns->lbasz, ns->lbasz, dir); 1296 } 1297 1298 nvme_sg_unmap(&req->sg); 1299 1300 status = nvme_map_mptr(n, &req->sg, len, &req->cmd); 1301 if (status) { 1302 return status; 1303 } 1304 1305 return nvme_tx(n, &req->sg, ptr, len, dir); 1306 } 1307 1308 static inline void nvme_blk_read(BlockBackend *blk, int64_t offset, 1309 BlockCompletionFunc *cb, NvmeRequest *req) 1310 { 1311 assert(req->sg.flags & NVME_SG_ALLOC); 1312 1313 if (req->sg.flags & NVME_SG_DMA) { 1314 req->aiocb = dma_blk_read(blk, &req->sg.qsg, offset, BDRV_SECTOR_SIZE, 1315 cb, req); 1316 } else { 1317 req->aiocb = blk_aio_preadv(blk, offset, &req->sg.iov, 0, cb, req); 1318 } 1319 } 1320 1321 static inline void nvme_blk_write(BlockBackend *blk, int64_t offset, 1322 BlockCompletionFunc *cb, NvmeRequest *req) 1323 { 1324 assert(req->sg.flags & NVME_SG_ALLOC); 1325 1326 if (req->sg.flags & NVME_SG_DMA) { 1327 req->aiocb = dma_blk_write(blk, &req->sg.qsg, offset, BDRV_SECTOR_SIZE, 1328 cb, req); 1329 } else { 1330 req->aiocb = blk_aio_pwritev(blk, offset, &req->sg.iov, 0, cb, req); 1331 } 1332 } 1333 1334 static void nvme_update_cq_head(NvmeCQueue *cq) 1335 { 1336 pci_dma_read(&cq->ctrl->parent_obj, cq->db_addr, &cq->head, 1337 sizeof(cq->head)); 1338 trace_pci_nvme_shadow_doorbell_cq(cq->cqid, cq->head); 1339 } 1340 1341 static void nvme_post_cqes(void *opaque) 1342 { 1343 NvmeCQueue *cq = opaque; 1344 NvmeCtrl *n = cq->ctrl; 1345 NvmeRequest *req, *next; 1346 bool pending = cq->head != cq->tail; 1347 int ret; 1348 1349 QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) { 1350 NvmeSQueue *sq; 1351 hwaddr addr; 1352 1353 if (n->dbbuf_enabled) { 1354 nvme_update_cq_head(cq); 1355 } 1356 1357 if (nvme_cq_full(cq)) { 1358 break; 1359 } 1360 1361 sq = req->sq; 1362 req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase); 1363 req->cqe.sq_id = cpu_to_le16(sq->sqid); 1364 req->cqe.sq_head = cpu_to_le16(sq->head); 1365 addr = cq->dma_addr + cq->tail * n->cqe_size; 1366 ret = pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe, 1367 sizeof(req->cqe)); 1368 if (ret) { 1369 trace_pci_nvme_err_addr_write(addr); 1370 trace_pci_nvme_err_cfs(); 1371 stl_le_p(&n->bar.csts, NVME_CSTS_FAILED); 1372 break; 1373 } 1374 QTAILQ_REMOVE(&cq->req_list, req, entry); 1375 nvme_inc_cq_tail(cq); 1376 nvme_sg_unmap(&req->sg); 1377 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry); 1378 } 1379 if (cq->tail != cq->head) { 1380 if (cq->irq_enabled && !pending) { 1381 n->cq_pending++; 1382 } 1383 1384 nvme_irq_assert(n, cq); 1385 } 1386 } 1387 1388 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req) 1389 { 1390 assert(cq->cqid == req->sq->cqid); 1391 trace_pci_nvme_enqueue_req_completion(nvme_cid(req), cq->cqid, 1392 le32_to_cpu(req->cqe.result), 1393 le32_to_cpu(req->cqe.dw1), 1394 req->status); 1395 1396 if (req->status) { 1397 trace_pci_nvme_err_req_status(nvme_cid(req), nvme_nsid(req->ns), 1398 req->status, req->cmd.opcode); 1399 } 1400 1401 QTAILQ_REMOVE(&req->sq->out_req_list, req, entry); 1402 QTAILQ_INSERT_TAIL(&cq->req_list, req, entry); 1403 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); 1404 } 1405 1406 static void nvme_process_aers(void *opaque) 1407 { 1408 NvmeCtrl *n = opaque; 1409 NvmeAsyncEvent *event, *next; 1410 1411 trace_pci_nvme_process_aers(n->aer_queued); 1412 1413 QTAILQ_FOREACH_SAFE(event, &n->aer_queue, entry, next) { 1414 NvmeRequest *req; 1415 NvmeAerResult *result; 1416 1417 /* can't post cqe if there is nothing to complete */ 1418 if (!n->outstanding_aers) { 1419 trace_pci_nvme_no_outstanding_aers(); 1420 break; 1421 } 1422 1423 /* ignore if masked (cqe posted, but event not cleared) */ 1424 if (n->aer_mask & (1 << event->result.event_type)) { 1425 trace_pci_nvme_aer_masked(event->result.event_type, n->aer_mask); 1426 continue; 1427 } 1428 1429 QTAILQ_REMOVE(&n->aer_queue, event, entry); 1430 n->aer_queued--; 1431 1432 n->aer_mask |= 1 << event->result.event_type; 1433 n->outstanding_aers--; 1434 1435 req = n->aer_reqs[n->outstanding_aers]; 1436 1437 result = (NvmeAerResult *) &req->cqe.result; 1438 result->event_type = event->result.event_type; 1439 result->event_info = event->result.event_info; 1440 result->log_page = event->result.log_page; 1441 g_free(event); 1442 1443 trace_pci_nvme_aer_post_cqe(result->event_type, result->event_info, 1444 result->log_page); 1445 1446 nvme_enqueue_req_completion(&n->admin_cq, req); 1447 } 1448 } 1449 1450 static void nvme_enqueue_event(NvmeCtrl *n, uint8_t event_type, 1451 uint8_t event_info, uint8_t log_page) 1452 { 1453 NvmeAsyncEvent *event; 1454 1455 trace_pci_nvme_enqueue_event(event_type, event_info, log_page); 1456 1457 if (n->aer_queued == n->params.aer_max_queued) { 1458 trace_pci_nvme_enqueue_event_noqueue(n->aer_queued); 1459 return; 1460 } 1461 1462 event = g_new(NvmeAsyncEvent, 1); 1463 event->result = (NvmeAerResult) { 1464 .event_type = event_type, 1465 .event_info = event_info, 1466 .log_page = log_page, 1467 }; 1468 1469 QTAILQ_INSERT_TAIL(&n->aer_queue, event, entry); 1470 n->aer_queued++; 1471 1472 nvme_process_aers(n); 1473 } 1474 1475 static void nvme_smart_event(NvmeCtrl *n, uint8_t event) 1476 { 1477 uint8_t aer_info; 1478 1479 /* Ref SPEC <Asynchronous Event Information 0x2013 SMART / Health Status> */ 1480 if (!(NVME_AEC_SMART(n->features.async_config) & event)) { 1481 return; 1482 } 1483 1484 switch (event) { 1485 case NVME_SMART_SPARE: 1486 aer_info = NVME_AER_INFO_SMART_SPARE_THRESH; 1487 break; 1488 case NVME_SMART_TEMPERATURE: 1489 aer_info = NVME_AER_INFO_SMART_TEMP_THRESH; 1490 break; 1491 case NVME_SMART_RELIABILITY: 1492 case NVME_SMART_MEDIA_READ_ONLY: 1493 case NVME_SMART_FAILED_VOLATILE_MEDIA: 1494 case NVME_SMART_PMR_UNRELIABLE: 1495 aer_info = NVME_AER_INFO_SMART_RELIABILITY; 1496 break; 1497 default: 1498 return; 1499 } 1500 1501 nvme_enqueue_event(n, NVME_AER_TYPE_SMART, aer_info, NVME_LOG_SMART_INFO); 1502 } 1503 1504 static void nvme_clear_events(NvmeCtrl *n, uint8_t event_type) 1505 { 1506 n->aer_mask &= ~(1 << event_type); 1507 if (!QTAILQ_EMPTY(&n->aer_queue)) { 1508 nvme_process_aers(n); 1509 } 1510 } 1511 1512 static inline uint16_t nvme_check_mdts(NvmeCtrl *n, size_t len) 1513 { 1514 uint8_t mdts = n->params.mdts; 1515 1516 if (mdts && len > n->page_size << mdts) { 1517 trace_pci_nvme_err_mdts(len); 1518 return NVME_INVALID_FIELD | NVME_DNR; 1519 } 1520 1521 return NVME_SUCCESS; 1522 } 1523 1524 static inline uint16_t nvme_check_bounds(NvmeNamespace *ns, uint64_t slba, 1525 uint32_t nlb) 1526 { 1527 uint64_t nsze = le64_to_cpu(ns->id_ns.nsze); 1528 1529 if (unlikely(UINT64_MAX - slba < nlb || slba + nlb > nsze)) { 1530 trace_pci_nvme_err_invalid_lba_range(slba, nlb, nsze); 1531 return NVME_LBA_RANGE | NVME_DNR; 1532 } 1533 1534 return NVME_SUCCESS; 1535 } 1536 1537 static int nvme_block_status_all(NvmeNamespace *ns, uint64_t slba, 1538 uint32_t nlb, int flags) 1539 { 1540 BlockDriverState *bs = blk_bs(ns->blkconf.blk); 1541 1542 int64_t pnum = 0, bytes = nvme_l2b(ns, nlb); 1543 int64_t offset = nvme_l2b(ns, slba); 1544 int ret; 1545 1546 /* 1547 * `pnum` holds the number of bytes after offset that shares the same 1548 * allocation status as the byte at offset. If `pnum` is different from 1549 * `bytes`, we should check the allocation status of the next range and 1550 * continue this until all bytes have been checked. 1551 */ 1552 do { 1553 bytes -= pnum; 1554 1555 ret = bdrv_block_status(bs, offset, bytes, &pnum, NULL, NULL); 1556 if (ret < 0) { 1557 return ret; 1558 } 1559 1560 1561 trace_pci_nvme_block_status(offset, bytes, pnum, ret, 1562 !!(ret & BDRV_BLOCK_ZERO)); 1563 1564 if (!(ret & flags)) { 1565 return 1; 1566 } 1567 1568 offset += pnum; 1569 } while (pnum != bytes); 1570 1571 return 0; 1572 } 1573 1574 static uint16_t nvme_check_dulbe(NvmeNamespace *ns, uint64_t slba, 1575 uint32_t nlb) 1576 { 1577 int ret; 1578 Error *err = NULL; 1579 1580 ret = nvme_block_status_all(ns, slba, nlb, BDRV_BLOCK_DATA); 1581 if (ret) { 1582 if (ret < 0) { 1583 error_setg_errno(&err, -ret, "unable to get block status"); 1584 error_report_err(err); 1585 1586 return NVME_INTERNAL_DEV_ERROR; 1587 } 1588 1589 return NVME_DULB; 1590 } 1591 1592 return NVME_SUCCESS; 1593 } 1594 1595 static void nvme_aio_err(NvmeRequest *req, int ret) 1596 { 1597 uint16_t status = NVME_SUCCESS; 1598 Error *local_err = NULL; 1599 1600 switch (req->cmd.opcode) { 1601 case NVME_CMD_READ: 1602 status = NVME_UNRECOVERED_READ; 1603 break; 1604 case NVME_CMD_FLUSH: 1605 case NVME_CMD_WRITE: 1606 case NVME_CMD_WRITE_ZEROES: 1607 case NVME_CMD_ZONE_APPEND: 1608 status = NVME_WRITE_FAULT; 1609 break; 1610 default: 1611 status = NVME_INTERNAL_DEV_ERROR; 1612 break; 1613 } 1614 1615 trace_pci_nvme_err_aio(nvme_cid(req), strerror(-ret), status); 1616 1617 error_setg_errno(&local_err, -ret, "aio failed"); 1618 error_report_err(local_err); 1619 1620 /* 1621 * Set the command status code to the first encountered error but allow a 1622 * subsequent Internal Device Error to trump it. 1623 */ 1624 if (req->status && status != NVME_INTERNAL_DEV_ERROR) { 1625 return; 1626 } 1627 1628 req->status = status; 1629 } 1630 1631 static inline uint32_t nvme_zone_idx(NvmeNamespace *ns, uint64_t slba) 1632 { 1633 return ns->zone_size_log2 > 0 ? slba >> ns->zone_size_log2 : 1634 slba / ns->zone_size; 1635 } 1636 1637 static inline NvmeZone *nvme_get_zone_by_slba(NvmeNamespace *ns, uint64_t slba) 1638 { 1639 uint32_t zone_idx = nvme_zone_idx(ns, slba); 1640 1641 if (zone_idx >= ns->num_zones) { 1642 return NULL; 1643 } 1644 1645 return &ns->zone_array[zone_idx]; 1646 } 1647 1648 static uint16_t nvme_check_zone_state_for_write(NvmeZone *zone) 1649 { 1650 uint64_t zslba = zone->d.zslba; 1651 1652 switch (nvme_get_zone_state(zone)) { 1653 case NVME_ZONE_STATE_EMPTY: 1654 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 1655 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 1656 case NVME_ZONE_STATE_CLOSED: 1657 return NVME_SUCCESS; 1658 case NVME_ZONE_STATE_FULL: 1659 trace_pci_nvme_err_zone_is_full(zslba); 1660 return NVME_ZONE_FULL; 1661 case NVME_ZONE_STATE_OFFLINE: 1662 trace_pci_nvme_err_zone_is_offline(zslba); 1663 return NVME_ZONE_OFFLINE; 1664 case NVME_ZONE_STATE_READ_ONLY: 1665 trace_pci_nvme_err_zone_is_read_only(zslba); 1666 return NVME_ZONE_READ_ONLY; 1667 default: 1668 assert(false); 1669 } 1670 1671 return NVME_INTERNAL_DEV_ERROR; 1672 } 1673 1674 static uint16_t nvme_check_zone_write(NvmeNamespace *ns, NvmeZone *zone, 1675 uint64_t slba, uint32_t nlb) 1676 { 1677 uint64_t zcap = nvme_zone_wr_boundary(zone); 1678 uint16_t status; 1679 1680 status = nvme_check_zone_state_for_write(zone); 1681 if (status) { 1682 return status; 1683 } 1684 1685 if (zone->d.za & NVME_ZA_ZRWA_VALID) { 1686 uint64_t ezrwa = zone->w_ptr + 2 * ns->zns.zrwas; 1687 1688 if (slba < zone->w_ptr || slba + nlb > ezrwa) { 1689 trace_pci_nvme_err_zone_invalid_write(slba, zone->w_ptr); 1690 return NVME_ZONE_INVALID_WRITE; 1691 } 1692 } else { 1693 if (unlikely(slba != zone->w_ptr)) { 1694 trace_pci_nvme_err_write_not_at_wp(slba, zone->d.zslba, 1695 zone->w_ptr); 1696 return NVME_ZONE_INVALID_WRITE; 1697 } 1698 } 1699 1700 if (unlikely((slba + nlb) > zcap)) { 1701 trace_pci_nvme_err_zone_boundary(slba, nlb, zcap); 1702 return NVME_ZONE_BOUNDARY_ERROR; 1703 } 1704 1705 return NVME_SUCCESS; 1706 } 1707 1708 static uint16_t nvme_check_zone_state_for_read(NvmeZone *zone) 1709 { 1710 switch (nvme_get_zone_state(zone)) { 1711 case NVME_ZONE_STATE_EMPTY: 1712 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 1713 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 1714 case NVME_ZONE_STATE_FULL: 1715 case NVME_ZONE_STATE_CLOSED: 1716 case NVME_ZONE_STATE_READ_ONLY: 1717 return NVME_SUCCESS; 1718 case NVME_ZONE_STATE_OFFLINE: 1719 trace_pci_nvme_err_zone_is_offline(zone->d.zslba); 1720 return NVME_ZONE_OFFLINE; 1721 default: 1722 assert(false); 1723 } 1724 1725 return NVME_INTERNAL_DEV_ERROR; 1726 } 1727 1728 static uint16_t nvme_check_zone_read(NvmeNamespace *ns, uint64_t slba, 1729 uint32_t nlb) 1730 { 1731 NvmeZone *zone; 1732 uint64_t bndry, end; 1733 uint16_t status; 1734 1735 zone = nvme_get_zone_by_slba(ns, slba); 1736 assert(zone); 1737 1738 bndry = nvme_zone_rd_boundary(ns, zone); 1739 end = slba + nlb; 1740 1741 status = nvme_check_zone_state_for_read(zone); 1742 if (status) { 1743 ; 1744 } else if (unlikely(end > bndry)) { 1745 if (!ns->params.cross_zone_read) { 1746 status = NVME_ZONE_BOUNDARY_ERROR; 1747 } else { 1748 /* 1749 * Read across zone boundary - check that all subsequent 1750 * zones that are being read have an appropriate state. 1751 */ 1752 do { 1753 zone++; 1754 status = nvme_check_zone_state_for_read(zone); 1755 if (status) { 1756 break; 1757 } 1758 } while (end > nvme_zone_rd_boundary(ns, zone)); 1759 } 1760 } 1761 1762 return status; 1763 } 1764 1765 static uint16_t nvme_zrm_finish(NvmeNamespace *ns, NvmeZone *zone) 1766 { 1767 switch (nvme_get_zone_state(zone)) { 1768 case NVME_ZONE_STATE_FULL: 1769 return NVME_SUCCESS; 1770 1771 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 1772 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 1773 nvme_aor_dec_open(ns); 1774 /* fallthrough */ 1775 case NVME_ZONE_STATE_CLOSED: 1776 nvme_aor_dec_active(ns); 1777 1778 if (zone->d.za & NVME_ZA_ZRWA_VALID) { 1779 zone->d.za &= ~NVME_ZA_ZRWA_VALID; 1780 if (ns->params.numzrwa) { 1781 ns->zns.numzrwa++; 1782 } 1783 } 1784 1785 /* fallthrough */ 1786 case NVME_ZONE_STATE_EMPTY: 1787 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_FULL); 1788 return NVME_SUCCESS; 1789 1790 default: 1791 return NVME_ZONE_INVAL_TRANSITION; 1792 } 1793 } 1794 1795 static uint16_t nvme_zrm_close(NvmeNamespace *ns, NvmeZone *zone) 1796 { 1797 switch (nvme_get_zone_state(zone)) { 1798 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 1799 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 1800 nvme_aor_dec_open(ns); 1801 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_CLOSED); 1802 /* fall through */ 1803 case NVME_ZONE_STATE_CLOSED: 1804 return NVME_SUCCESS; 1805 1806 default: 1807 return NVME_ZONE_INVAL_TRANSITION; 1808 } 1809 } 1810 1811 static uint16_t nvme_zrm_reset(NvmeNamespace *ns, NvmeZone *zone) 1812 { 1813 switch (nvme_get_zone_state(zone)) { 1814 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 1815 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 1816 nvme_aor_dec_open(ns); 1817 /* fallthrough */ 1818 case NVME_ZONE_STATE_CLOSED: 1819 nvme_aor_dec_active(ns); 1820 1821 if (zone->d.za & NVME_ZA_ZRWA_VALID) { 1822 if (ns->params.numzrwa) { 1823 ns->zns.numzrwa++; 1824 } 1825 } 1826 1827 /* fallthrough */ 1828 case NVME_ZONE_STATE_FULL: 1829 zone->w_ptr = zone->d.zslba; 1830 zone->d.wp = zone->w_ptr; 1831 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_EMPTY); 1832 /* fallthrough */ 1833 case NVME_ZONE_STATE_EMPTY: 1834 return NVME_SUCCESS; 1835 1836 default: 1837 return NVME_ZONE_INVAL_TRANSITION; 1838 } 1839 } 1840 1841 static void nvme_zrm_auto_transition_zone(NvmeNamespace *ns) 1842 { 1843 NvmeZone *zone; 1844 1845 if (ns->params.max_open_zones && 1846 ns->nr_open_zones == ns->params.max_open_zones) { 1847 zone = QTAILQ_FIRST(&ns->imp_open_zones); 1848 if (zone) { 1849 /* 1850 * Automatically close this implicitly open zone. 1851 */ 1852 QTAILQ_REMOVE(&ns->imp_open_zones, zone, entry); 1853 nvme_zrm_close(ns, zone); 1854 } 1855 } 1856 } 1857 1858 enum { 1859 NVME_ZRM_AUTO = 1 << 0, 1860 NVME_ZRM_ZRWA = 1 << 1, 1861 }; 1862 1863 static uint16_t nvme_zrm_open_flags(NvmeCtrl *n, NvmeNamespace *ns, 1864 NvmeZone *zone, int flags) 1865 { 1866 int act = 0; 1867 uint16_t status; 1868 1869 switch (nvme_get_zone_state(zone)) { 1870 case NVME_ZONE_STATE_EMPTY: 1871 act = 1; 1872 1873 /* fallthrough */ 1874 1875 case NVME_ZONE_STATE_CLOSED: 1876 if (n->params.auto_transition_zones) { 1877 nvme_zrm_auto_transition_zone(ns); 1878 } 1879 status = nvme_zns_check_resources(ns, act, 1, 1880 (flags & NVME_ZRM_ZRWA) ? 1 : 0); 1881 if (status) { 1882 return status; 1883 } 1884 1885 if (act) { 1886 nvme_aor_inc_active(ns); 1887 } 1888 1889 nvme_aor_inc_open(ns); 1890 1891 if (flags & NVME_ZRM_AUTO) { 1892 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_IMPLICITLY_OPEN); 1893 return NVME_SUCCESS; 1894 } 1895 1896 /* fallthrough */ 1897 1898 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 1899 if (flags & NVME_ZRM_AUTO) { 1900 return NVME_SUCCESS; 1901 } 1902 1903 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_EXPLICITLY_OPEN); 1904 1905 /* fallthrough */ 1906 1907 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 1908 if (flags & NVME_ZRM_ZRWA) { 1909 ns->zns.numzrwa--; 1910 1911 zone->d.za |= NVME_ZA_ZRWA_VALID; 1912 } 1913 1914 return NVME_SUCCESS; 1915 1916 default: 1917 return NVME_ZONE_INVAL_TRANSITION; 1918 } 1919 } 1920 1921 static inline uint16_t nvme_zrm_auto(NvmeCtrl *n, NvmeNamespace *ns, 1922 NvmeZone *zone) 1923 { 1924 return nvme_zrm_open_flags(n, ns, zone, NVME_ZRM_AUTO); 1925 } 1926 1927 static void nvme_advance_zone_wp(NvmeNamespace *ns, NvmeZone *zone, 1928 uint32_t nlb) 1929 { 1930 zone->d.wp += nlb; 1931 1932 if (zone->d.wp == nvme_zone_wr_boundary(zone)) { 1933 nvme_zrm_finish(ns, zone); 1934 } 1935 } 1936 1937 static void nvme_zoned_zrwa_implicit_flush(NvmeNamespace *ns, NvmeZone *zone, 1938 uint32_t nlbc) 1939 { 1940 uint16_t nzrwafgs = DIV_ROUND_UP(nlbc, ns->zns.zrwafg); 1941 1942 nlbc = nzrwafgs * ns->zns.zrwafg; 1943 1944 trace_pci_nvme_zoned_zrwa_implicit_flush(zone->d.zslba, nlbc); 1945 1946 zone->w_ptr += nlbc; 1947 1948 nvme_advance_zone_wp(ns, zone, nlbc); 1949 } 1950 1951 static void nvme_finalize_zoned_write(NvmeNamespace *ns, NvmeRequest *req) 1952 { 1953 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 1954 NvmeZone *zone; 1955 uint64_t slba; 1956 uint32_t nlb; 1957 1958 slba = le64_to_cpu(rw->slba); 1959 nlb = le16_to_cpu(rw->nlb) + 1; 1960 zone = nvme_get_zone_by_slba(ns, slba); 1961 assert(zone); 1962 1963 if (zone->d.za & NVME_ZA_ZRWA_VALID) { 1964 uint64_t ezrwa = zone->w_ptr + ns->zns.zrwas - 1; 1965 uint64_t elba = slba + nlb - 1; 1966 1967 if (elba > ezrwa) { 1968 nvme_zoned_zrwa_implicit_flush(ns, zone, elba - ezrwa); 1969 } 1970 1971 return; 1972 } 1973 1974 nvme_advance_zone_wp(ns, zone, nlb); 1975 } 1976 1977 static inline bool nvme_is_write(NvmeRequest *req) 1978 { 1979 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 1980 1981 return rw->opcode == NVME_CMD_WRITE || 1982 rw->opcode == NVME_CMD_ZONE_APPEND || 1983 rw->opcode == NVME_CMD_WRITE_ZEROES; 1984 } 1985 1986 static AioContext *nvme_get_aio_context(BlockAIOCB *acb) 1987 { 1988 return qemu_get_aio_context(); 1989 } 1990 1991 static void nvme_misc_cb(void *opaque, int ret) 1992 { 1993 NvmeRequest *req = opaque; 1994 1995 trace_pci_nvme_misc_cb(nvme_cid(req)); 1996 1997 if (ret) { 1998 nvme_aio_err(req, ret); 1999 } 2000 2001 nvme_enqueue_req_completion(nvme_cq(req), req); 2002 } 2003 2004 void nvme_rw_complete_cb(void *opaque, int ret) 2005 { 2006 NvmeRequest *req = opaque; 2007 NvmeNamespace *ns = req->ns; 2008 BlockBackend *blk = ns->blkconf.blk; 2009 BlockAcctCookie *acct = &req->acct; 2010 BlockAcctStats *stats = blk_get_stats(blk); 2011 2012 trace_pci_nvme_rw_complete_cb(nvme_cid(req), blk_name(blk)); 2013 2014 if (ret) { 2015 block_acct_failed(stats, acct); 2016 nvme_aio_err(req, ret); 2017 } else { 2018 block_acct_done(stats, acct); 2019 } 2020 2021 if (ns->params.zoned && nvme_is_write(req)) { 2022 nvme_finalize_zoned_write(ns, req); 2023 } 2024 2025 nvme_enqueue_req_completion(nvme_cq(req), req); 2026 } 2027 2028 static void nvme_rw_cb(void *opaque, int ret) 2029 { 2030 NvmeRequest *req = opaque; 2031 NvmeNamespace *ns = req->ns; 2032 2033 BlockBackend *blk = ns->blkconf.blk; 2034 2035 trace_pci_nvme_rw_cb(nvme_cid(req), blk_name(blk)); 2036 2037 if (ret) { 2038 goto out; 2039 } 2040 2041 if (ns->lbaf.ms) { 2042 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 2043 uint64_t slba = le64_to_cpu(rw->slba); 2044 uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1; 2045 uint64_t offset = nvme_moff(ns, slba); 2046 2047 if (req->cmd.opcode == NVME_CMD_WRITE_ZEROES) { 2048 size_t mlen = nvme_m2b(ns, nlb); 2049 2050 req->aiocb = blk_aio_pwrite_zeroes(blk, offset, mlen, 2051 BDRV_REQ_MAY_UNMAP, 2052 nvme_rw_complete_cb, req); 2053 return; 2054 } 2055 2056 if (nvme_ns_ext(ns) || req->cmd.mptr) { 2057 uint16_t status; 2058 2059 nvme_sg_unmap(&req->sg); 2060 status = nvme_map_mdata(nvme_ctrl(req), nlb, req); 2061 if (status) { 2062 ret = -EFAULT; 2063 goto out; 2064 } 2065 2066 if (req->cmd.opcode == NVME_CMD_READ) { 2067 return nvme_blk_read(blk, offset, nvme_rw_complete_cb, req); 2068 } 2069 2070 return nvme_blk_write(blk, offset, nvme_rw_complete_cb, req); 2071 } 2072 } 2073 2074 out: 2075 nvme_rw_complete_cb(req, ret); 2076 } 2077 2078 static void nvme_verify_cb(void *opaque, int ret) 2079 { 2080 NvmeBounceContext *ctx = opaque; 2081 NvmeRequest *req = ctx->req; 2082 NvmeNamespace *ns = req->ns; 2083 BlockBackend *blk = ns->blkconf.blk; 2084 BlockAcctCookie *acct = &req->acct; 2085 BlockAcctStats *stats = blk_get_stats(blk); 2086 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 2087 uint64_t slba = le64_to_cpu(rw->slba); 2088 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control)); 2089 uint16_t apptag = le16_to_cpu(rw->apptag); 2090 uint16_t appmask = le16_to_cpu(rw->appmask); 2091 uint64_t reftag = le32_to_cpu(rw->reftag); 2092 uint64_t cdw3 = le32_to_cpu(rw->cdw3); 2093 uint16_t status; 2094 2095 reftag |= cdw3 << 32; 2096 2097 trace_pci_nvme_verify_cb(nvme_cid(req), prinfo, apptag, appmask, reftag); 2098 2099 if (ret) { 2100 block_acct_failed(stats, acct); 2101 nvme_aio_err(req, ret); 2102 goto out; 2103 } 2104 2105 block_acct_done(stats, acct); 2106 2107 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 2108 status = nvme_dif_mangle_mdata(ns, ctx->mdata.bounce, 2109 ctx->mdata.iov.size, slba); 2110 if (status) { 2111 req->status = status; 2112 goto out; 2113 } 2114 2115 req->status = nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size, 2116 ctx->mdata.bounce, ctx->mdata.iov.size, 2117 prinfo, slba, apptag, appmask, &reftag); 2118 } 2119 2120 out: 2121 qemu_iovec_destroy(&ctx->data.iov); 2122 g_free(ctx->data.bounce); 2123 2124 qemu_iovec_destroy(&ctx->mdata.iov); 2125 g_free(ctx->mdata.bounce); 2126 2127 g_free(ctx); 2128 2129 nvme_enqueue_req_completion(nvme_cq(req), req); 2130 } 2131 2132 2133 static void nvme_verify_mdata_in_cb(void *opaque, int ret) 2134 { 2135 NvmeBounceContext *ctx = opaque; 2136 NvmeRequest *req = ctx->req; 2137 NvmeNamespace *ns = req->ns; 2138 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 2139 uint64_t slba = le64_to_cpu(rw->slba); 2140 uint32_t nlb = le16_to_cpu(rw->nlb) + 1; 2141 size_t mlen = nvme_m2b(ns, nlb); 2142 uint64_t offset = nvme_moff(ns, slba); 2143 BlockBackend *blk = ns->blkconf.blk; 2144 2145 trace_pci_nvme_verify_mdata_in_cb(nvme_cid(req), blk_name(blk)); 2146 2147 if (ret) { 2148 goto out; 2149 } 2150 2151 ctx->mdata.bounce = g_malloc(mlen); 2152 2153 qemu_iovec_reset(&ctx->mdata.iov); 2154 qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen); 2155 2156 req->aiocb = blk_aio_preadv(blk, offset, &ctx->mdata.iov, 0, 2157 nvme_verify_cb, ctx); 2158 return; 2159 2160 out: 2161 nvme_verify_cb(ctx, ret); 2162 } 2163 2164 struct nvme_compare_ctx { 2165 struct { 2166 QEMUIOVector iov; 2167 uint8_t *bounce; 2168 } data; 2169 2170 struct { 2171 QEMUIOVector iov; 2172 uint8_t *bounce; 2173 } mdata; 2174 }; 2175 2176 static void nvme_compare_mdata_cb(void *opaque, int ret) 2177 { 2178 NvmeRequest *req = opaque; 2179 NvmeNamespace *ns = req->ns; 2180 NvmeCtrl *n = nvme_ctrl(req); 2181 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 2182 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control)); 2183 uint16_t apptag = le16_to_cpu(rw->apptag); 2184 uint16_t appmask = le16_to_cpu(rw->appmask); 2185 uint64_t reftag = le32_to_cpu(rw->reftag); 2186 uint64_t cdw3 = le32_to_cpu(rw->cdw3); 2187 struct nvme_compare_ctx *ctx = req->opaque; 2188 g_autofree uint8_t *buf = NULL; 2189 BlockBackend *blk = ns->blkconf.blk; 2190 BlockAcctCookie *acct = &req->acct; 2191 BlockAcctStats *stats = blk_get_stats(blk); 2192 uint16_t status = NVME_SUCCESS; 2193 2194 reftag |= cdw3 << 32; 2195 2196 trace_pci_nvme_compare_mdata_cb(nvme_cid(req)); 2197 2198 if (ret) { 2199 block_acct_failed(stats, acct); 2200 nvme_aio_err(req, ret); 2201 goto out; 2202 } 2203 2204 buf = g_malloc(ctx->mdata.iov.size); 2205 2206 status = nvme_bounce_mdata(n, buf, ctx->mdata.iov.size, 2207 NVME_TX_DIRECTION_TO_DEVICE, req); 2208 if (status) { 2209 req->status = status; 2210 goto out; 2211 } 2212 2213 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 2214 uint64_t slba = le64_to_cpu(rw->slba); 2215 uint8_t *bufp; 2216 uint8_t *mbufp = ctx->mdata.bounce; 2217 uint8_t *end = mbufp + ctx->mdata.iov.size; 2218 int16_t pil = 0; 2219 2220 status = nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size, 2221 ctx->mdata.bounce, ctx->mdata.iov.size, prinfo, 2222 slba, apptag, appmask, &reftag); 2223 if (status) { 2224 req->status = status; 2225 goto out; 2226 } 2227 2228 /* 2229 * When formatted with protection information, do not compare the DIF 2230 * tuple. 2231 */ 2232 if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) { 2233 pil = ns->lbaf.ms - nvme_pi_tuple_size(ns); 2234 } 2235 2236 for (bufp = buf; mbufp < end; bufp += ns->lbaf.ms, mbufp += ns->lbaf.ms) { 2237 if (memcmp(bufp + pil, mbufp + pil, ns->lbaf.ms - pil)) { 2238 req->status = NVME_CMP_FAILURE; 2239 goto out; 2240 } 2241 } 2242 2243 goto out; 2244 } 2245 2246 if (memcmp(buf, ctx->mdata.bounce, ctx->mdata.iov.size)) { 2247 req->status = NVME_CMP_FAILURE; 2248 goto out; 2249 } 2250 2251 block_acct_done(stats, acct); 2252 2253 out: 2254 qemu_iovec_destroy(&ctx->data.iov); 2255 g_free(ctx->data.bounce); 2256 2257 qemu_iovec_destroy(&ctx->mdata.iov); 2258 g_free(ctx->mdata.bounce); 2259 2260 g_free(ctx); 2261 2262 nvme_enqueue_req_completion(nvme_cq(req), req); 2263 } 2264 2265 static void nvme_compare_data_cb(void *opaque, int ret) 2266 { 2267 NvmeRequest *req = opaque; 2268 NvmeCtrl *n = nvme_ctrl(req); 2269 NvmeNamespace *ns = req->ns; 2270 BlockBackend *blk = ns->blkconf.blk; 2271 BlockAcctCookie *acct = &req->acct; 2272 BlockAcctStats *stats = blk_get_stats(blk); 2273 2274 struct nvme_compare_ctx *ctx = req->opaque; 2275 g_autofree uint8_t *buf = NULL; 2276 uint16_t status; 2277 2278 trace_pci_nvme_compare_data_cb(nvme_cid(req)); 2279 2280 if (ret) { 2281 block_acct_failed(stats, acct); 2282 nvme_aio_err(req, ret); 2283 goto out; 2284 } 2285 2286 buf = g_malloc(ctx->data.iov.size); 2287 2288 status = nvme_bounce_data(n, buf, ctx->data.iov.size, 2289 NVME_TX_DIRECTION_TO_DEVICE, req); 2290 if (status) { 2291 req->status = status; 2292 goto out; 2293 } 2294 2295 if (memcmp(buf, ctx->data.bounce, ctx->data.iov.size)) { 2296 req->status = NVME_CMP_FAILURE; 2297 goto out; 2298 } 2299 2300 if (ns->lbaf.ms) { 2301 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 2302 uint64_t slba = le64_to_cpu(rw->slba); 2303 uint32_t nlb = le16_to_cpu(rw->nlb) + 1; 2304 size_t mlen = nvme_m2b(ns, nlb); 2305 uint64_t offset = nvme_moff(ns, slba); 2306 2307 ctx->mdata.bounce = g_malloc(mlen); 2308 2309 qemu_iovec_init(&ctx->mdata.iov, 1); 2310 qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen); 2311 2312 req->aiocb = blk_aio_preadv(blk, offset, &ctx->mdata.iov, 0, 2313 nvme_compare_mdata_cb, req); 2314 return; 2315 } 2316 2317 block_acct_done(stats, acct); 2318 2319 out: 2320 qemu_iovec_destroy(&ctx->data.iov); 2321 g_free(ctx->data.bounce); 2322 g_free(ctx); 2323 2324 nvme_enqueue_req_completion(nvme_cq(req), req); 2325 } 2326 2327 typedef struct NvmeDSMAIOCB { 2328 BlockAIOCB common; 2329 BlockAIOCB *aiocb; 2330 NvmeRequest *req; 2331 QEMUBH *bh; 2332 int ret; 2333 2334 NvmeDsmRange *range; 2335 unsigned int nr; 2336 unsigned int idx; 2337 } NvmeDSMAIOCB; 2338 2339 static void nvme_dsm_cancel(BlockAIOCB *aiocb) 2340 { 2341 NvmeDSMAIOCB *iocb = container_of(aiocb, NvmeDSMAIOCB, common); 2342 2343 /* break nvme_dsm_cb loop */ 2344 iocb->idx = iocb->nr; 2345 iocb->ret = -ECANCELED; 2346 2347 if (iocb->aiocb) { 2348 blk_aio_cancel_async(iocb->aiocb); 2349 iocb->aiocb = NULL; 2350 } else { 2351 /* 2352 * We only reach this if nvme_dsm_cancel() has already been called or 2353 * the command ran to completion and nvme_dsm_bh is scheduled to run. 2354 */ 2355 assert(iocb->idx == iocb->nr); 2356 } 2357 } 2358 2359 static const AIOCBInfo nvme_dsm_aiocb_info = { 2360 .aiocb_size = sizeof(NvmeDSMAIOCB), 2361 .cancel_async = nvme_dsm_cancel, 2362 }; 2363 2364 static void nvme_dsm_bh(void *opaque) 2365 { 2366 NvmeDSMAIOCB *iocb = opaque; 2367 2368 iocb->common.cb(iocb->common.opaque, iocb->ret); 2369 2370 qemu_bh_delete(iocb->bh); 2371 iocb->bh = NULL; 2372 qemu_aio_unref(iocb); 2373 } 2374 2375 static void nvme_dsm_cb(void *opaque, int ret); 2376 2377 static void nvme_dsm_md_cb(void *opaque, int ret) 2378 { 2379 NvmeDSMAIOCB *iocb = opaque; 2380 NvmeRequest *req = iocb->req; 2381 NvmeNamespace *ns = req->ns; 2382 NvmeDsmRange *range; 2383 uint64_t slba; 2384 uint32_t nlb; 2385 2386 if (ret < 0) { 2387 iocb->ret = ret; 2388 goto done; 2389 } 2390 2391 if (!ns->lbaf.ms) { 2392 nvme_dsm_cb(iocb, 0); 2393 return; 2394 } 2395 2396 range = &iocb->range[iocb->idx - 1]; 2397 slba = le64_to_cpu(range->slba); 2398 nlb = le32_to_cpu(range->nlb); 2399 2400 /* 2401 * Check that all block were discarded (zeroed); otherwise we do not zero 2402 * the metadata. 2403 */ 2404 2405 ret = nvme_block_status_all(ns, slba, nlb, BDRV_BLOCK_ZERO); 2406 if (ret) { 2407 if (ret < 0) { 2408 iocb->ret = ret; 2409 goto done; 2410 } 2411 2412 nvme_dsm_cb(iocb, 0); 2413 return; 2414 } 2415 2416 iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, nvme_moff(ns, slba), 2417 nvme_m2b(ns, nlb), BDRV_REQ_MAY_UNMAP, 2418 nvme_dsm_cb, iocb); 2419 return; 2420 2421 done: 2422 iocb->aiocb = NULL; 2423 qemu_bh_schedule(iocb->bh); 2424 } 2425 2426 static void nvme_dsm_cb(void *opaque, int ret) 2427 { 2428 NvmeDSMAIOCB *iocb = opaque; 2429 NvmeRequest *req = iocb->req; 2430 NvmeCtrl *n = nvme_ctrl(req); 2431 NvmeNamespace *ns = req->ns; 2432 NvmeDsmRange *range; 2433 uint64_t slba; 2434 uint32_t nlb; 2435 2436 if (ret < 0) { 2437 iocb->ret = ret; 2438 goto done; 2439 } 2440 2441 next: 2442 if (iocb->idx == iocb->nr) { 2443 goto done; 2444 } 2445 2446 range = &iocb->range[iocb->idx++]; 2447 slba = le64_to_cpu(range->slba); 2448 nlb = le32_to_cpu(range->nlb); 2449 2450 trace_pci_nvme_dsm_deallocate(slba, nlb); 2451 2452 if (nlb > n->dmrsl) { 2453 trace_pci_nvme_dsm_single_range_limit_exceeded(nlb, n->dmrsl); 2454 goto next; 2455 } 2456 2457 if (nvme_check_bounds(ns, slba, nlb)) { 2458 trace_pci_nvme_err_invalid_lba_range(slba, nlb, 2459 ns->id_ns.nsze); 2460 goto next; 2461 } 2462 2463 iocb->aiocb = blk_aio_pdiscard(ns->blkconf.blk, nvme_l2b(ns, slba), 2464 nvme_l2b(ns, nlb), 2465 nvme_dsm_md_cb, iocb); 2466 return; 2467 2468 done: 2469 iocb->aiocb = NULL; 2470 qemu_bh_schedule(iocb->bh); 2471 } 2472 2473 static uint16_t nvme_dsm(NvmeCtrl *n, NvmeRequest *req) 2474 { 2475 NvmeNamespace *ns = req->ns; 2476 NvmeDsmCmd *dsm = (NvmeDsmCmd *) &req->cmd; 2477 uint32_t attr = le32_to_cpu(dsm->attributes); 2478 uint32_t nr = (le32_to_cpu(dsm->nr) & 0xff) + 1; 2479 uint16_t status = NVME_SUCCESS; 2480 2481 trace_pci_nvme_dsm(nr, attr); 2482 2483 if (attr & NVME_DSMGMT_AD) { 2484 NvmeDSMAIOCB *iocb = blk_aio_get(&nvme_dsm_aiocb_info, ns->blkconf.blk, 2485 nvme_misc_cb, req); 2486 2487 iocb->req = req; 2488 iocb->bh = qemu_bh_new(nvme_dsm_bh, iocb); 2489 iocb->ret = 0; 2490 iocb->range = g_new(NvmeDsmRange, nr); 2491 iocb->nr = nr; 2492 iocb->idx = 0; 2493 2494 status = nvme_h2c(n, (uint8_t *)iocb->range, sizeof(NvmeDsmRange) * nr, 2495 req); 2496 if (status) { 2497 return status; 2498 } 2499 2500 req->aiocb = &iocb->common; 2501 nvme_dsm_cb(iocb, 0); 2502 2503 return NVME_NO_COMPLETE; 2504 } 2505 2506 return status; 2507 } 2508 2509 static uint16_t nvme_verify(NvmeCtrl *n, NvmeRequest *req) 2510 { 2511 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 2512 NvmeNamespace *ns = req->ns; 2513 BlockBackend *blk = ns->blkconf.blk; 2514 uint64_t slba = le64_to_cpu(rw->slba); 2515 uint32_t nlb = le16_to_cpu(rw->nlb) + 1; 2516 size_t len = nvme_l2b(ns, nlb); 2517 int64_t offset = nvme_l2b(ns, slba); 2518 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control)); 2519 uint32_t reftag = le32_to_cpu(rw->reftag); 2520 NvmeBounceContext *ctx = NULL; 2521 uint16_t status; 2522 2523 trace_pci_nvme_verify(nvme_cid(req), nvme_nsid(ns), slba, nlb); 2524 2525 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 2526 status = nvme_check_prinfo(ns, prinfo, slba, reftag); 2527 if (status) { 2528 return status; 2529 } 2530 2531 if (prinfo & NVME_PRINFO_PRACT) { 2532 return NVME_INVALID_PROT_INFO | NVME_DNR; 2533 } 2534 } 2535 2536 if (len > n->page_size << n->params.vsl) { 2537 return NVME_INVALID_FIELD | NVME_DNR; 2538 } 2539 2540 status = nvme_check_bounds(ns, slba, nlb); 2541 if (status) { 2542 return status; 2543 } 2544 2545 if (NVME_ERR_REC_DULBE(ns->features.err_rec)) { 2546 status = nvme_check_dulbe(ns, slba, nlb); 2547 if (status) { 2548 return status; 2549 } 2550 } 2551 2552 ctx = g_new0(NvmeBounceContext, 1); 2553 ctx->req = req; 2554 2555 ctx->data.bounce = g_malloc(len); 2556 2557 qemu_iovec_init(&ctx->data.iov, 1); 2558 qemu_iovec_add(&ctx->data.iov, ctx->data.bounce, len); 2559 2560 block_acct_start(blk_get_stats(blk), &req->acct, ctx->data.iov.size, 2561 BLOCK_ACCT_READ); 2562 2563 req->aiocb = blk_aio_preadv(ns->blkconf.blk, offset, &ctx->data.iov, 0, 2564 nvme_verify_mdata_in_cb, ctx); 2565 return NVME_NO_COMPLETE; 2566 } 2567 2568 typedef struct NvmeCopyAIOCB { 2569 BlockAIOCB common; 2570 BlockAIOCB *aiocb; 2571 NvmeRequest *req; 2572 QEMUBH *bh; 2573 int ret; 2574 2575 void *ranges; 2576 unsigned int format; 2577 int nr; 2578 int idx; 2579 2580 uint8_t *bounce; 2581 QEMUIOVector iov; 2582 struct { 2583 BlockAcctCookie read; 2584 BlockAcctCookie write; 2585 } acct; 2586 2587 uint64_t reftag; 2588 uint64_t slba; 2589 2590 NvmeZone *zone; 2591 } NvmeCopyAIOCB; 2592 2593 static void nvme_copy_cancel(BlockAIOCB *aiocb) 2594 { 2595 NvmeCopyAIOCB *iocb = container_of(aiocb, NvmeCopyAIOCB, common); 2596 2597 iocb->ret = -ECANCELED; 2598 2599 if (iocb->aiocb) { 2600 blk_aio_cancel_async(iocb->aiocb); 2601 iocb->aiocb = NULL; 2602 } 2603 } 2604 2605 static const AIOCBInfo nvme_copy_aiocb_info = { 2606 .aiocb_size = sizeof(NvmeCopyAIOCB), 2607 .cancel_async = nvme_copy_cancel, 2608 }; 2609 2610 static void nvme_copy_bh(void *opaque) 2611 { 2612 NvmeCopyAIOCB *iocb = opaque; 2613 NvmeRequest *req = iocb->req; 2614 NvmeNamespace *ns = req->ns; 2615 BlockAcctStats *stats = blk_get_stats(ns->blkconf.blk); 2616 2617 if (iocb->idx != iocb->nr) { 2618 req->cqe.result = cpu_to_le32(iocb->idx); 2619 } 2620 2621 qemu_iovec_destroy(&iocb->iov); 2622 g_free(iocb->bounce); 2623 2624 qemu_bh_delete(iocb->bh); 2625 iocb->bh = NULL; 2626 2627 if (iocb->ret < 0) { 2628 block_acct_failed(stats, &iocb->acct.read); 2629 block_acct_failed(stats, &iocb->acct.write); 2630 } else { 2631 block_acct_done(stats, &iocb->acct.read); 2632 block_acct_done(stats, &iocb->acct.write); 2633 } 2634 2635 iocb->common.cb(iocb->common.opaque, iocb->ret); 2636 qemu_aio_unref(iocb); 2637 } 2638 2639 static void nvme_copy_cb(void *opaque, int ret); 2640 2641 static void nvme_copy_source_range_parse_format0(void *ranges, int idx, 2642 uint64_t *slba, uint32_t *nlb, 2643 uint16_t *apptag, 2644 uint16_t *appmask, 2645 uint64_t *reftag) 2646 { 2647 NvmeCopySourceRangeFormat0 *_ranges = ranges; 2648 2649 if (slba) { 2650 *slba = le64_to_cpu(_ranges[idx].slba); 2651 } 2652 2653 if (nlb) { 2654 *nlb = le16_to_cpu(_ranges[idx].nlb) + 1; 2655 } 2656 2657 if (apptag) { 2658 *apptag = le16_to_cpu(_ranges[idx].apptag); 2659 } 2660 2661 if (appmask) { 2662 *appmask = le16_to_cpu(_ranges[idx].appmask); 2663 } 2664 2665 if (reftag) { 2666 *reftag = le32_to_cpu(_ranges[idx].reftag); 2667 } 2668 } 2669 2670 static void nvme_copy_source_range_parse_format1(void *ranges, int idx, 2671 uint64_t *slba, uint32_t *nlb, 2672 uint16_t *apptag, 2673 uint16_t *appmask, 2674 uint64_t *reftag) 2675 { 2676 NvmeCopySourceRangeFormat1 *_ranges = ranges; 2677 2678 if (slba) { 2679 *slba = le64_to_cpu(_ranges[idx].slba); 2680 } 2681 2682 if (nlb) { 2683 *nlb = le16_to_cpu(_ranges[idx].nlb) + 1; 2684 } 2685 2686 if (apptag) { 2687 *apptag = le16_to_cpu(_ranges[idx].apptag); 2688 } 2689 2690 if (appmask) { 2691 *appmask = le16_to_cpu(_ranges[idx].appmask); 2692 } 2693 2694 if (reftag) { 2695 *reftag = 0; 2696 2697 *reftag |= (uint64_t)_ranges[idx].sr[4] << 40; 2698 *reftag |= (uint64_t)_ranges[idx].sr[5] << 32; 2699 *reftag |= (uint64_t)_ranges[idx].sr[6] << 24; 2700 *reftag |= (uint64_t)_ranges[idx].sr[7] << 16; 2701 *reftag |= (uint64_t)_ranges[idx].sr[8] << 8; 2702 *reftag |= (uint64_t)_ranges[idx].sr[9]; 2703 } 2704 } 2705 2706 static void nvme_copy_source_range_parse(void *ranges, int idx, uint8_t format, 2707 uint64_t *slba, uint32_t *nlb, 2708 uint16_t *apptag, uint16_t *appmask, 2709 uint64_t *reftag) 2710 { 2711 switch (format) { 2712 case NVME_COPY_FORMAT_0: 2713 nvme_copy_source_range_parse_format0(ranges, idx, slba, nlb, apptag, 2714 appmask, reftag); 2715 break; 2716 2717 case NVME_COPY_FORMAT_1: 2718 nvme_copy_source_range_parse_format1(ranges, idx, slba, nlb, apptag, 2719 appmask, reftag); 2720 break; 2721 2722 default: 2723 abort(); 2724 } 2725 } 2726 2727 static void nvme_copy_out_completed_cb(void *opaque, int ret) 2728 { 2729 NvmeCopyAIOCB *iocb = opaque; 2730 NvmeRequest *req = iocb->req; 2731 NvmeNamespace *ns = req->ns; 2732 uint32_t nlb; 2733 2734 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, NULL, 2735 &nlb, NULL, NULL, NULL); 2736 2737 if (ret < 0) { 2738 iocb->ret = ret; 2739 goto out; 2740 } else if (iocb->ret < 0) { 2741 goto out; 2742 } 2743 2744 if (ns->params.zoned) { 2745 nvme_advance_zone_wp(ns, iocb->zone, nlb); 2746 } 2747 2748 iocb->idx++; 2749 iocb->slba += nlb; 2750 out: 2751 nvme_copy_cb(iocb, iocb->ret); 2752 } 2753 2754 static void nvme_copy_out_cb(void *opaque, int ret) 2755 { 2756 NvmeCopyAIOCB *iocb = opaque; 2757 NvmeRequest *req = iocb->req; 2758 NvmeNamespace *ns = req->ns; 2759 uint32_t nlb; 2760 size_t mlen; 2761 uint8_t *mbounce; 2762 2763 if (ret < 0) { 2764 iocb->ret = ret; 2765 goto out; 2766 } else if (iocb->ret < 0) { 2767 goto out; 2768 } 2769 2770 if (!ns->lbaf.ms) { 2771 nvme_copy_out_completed_cb(iocb, 0); 2772 return; 2773 } 2774 2775 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, NULL, 2776 &nlb, NULL, NULL, NULL); 2777 2778 mlen = nvme_m2b(ns, nlb); 2779 mbounce = iocb->bounce + nvme_l2b(ns, nlb); 2780 2781 qemu_iovec_reset(&iocb->iov); 2782 qemu_iovec_add(&iocb->iov, mbounce, mlen); 2783 2784 iocb->aiocb = blk_aio_pwritev(ns->blkconf.blk, nvme_moff(ns, iocb->slba), 2785 &iocb->iov, 0, nvme_copy_out_completed_cb, 2786 iocb); 2787 2788 return; 2789 2790 out: 2791 nvme_copy_cb(iocb, ret); 2792 } 2793 2794 static void nvme_copy_in_completed_cb(void *opaque, int ret) 2795 { 2796 NvmeCopyAIOCB *iocb = opaque; 2797 NvmeRequest *req = iocb->req; 2798 NvmeNamespace *ns = req->ns; 2799 uint32_t nlb; 2800 uint64_t slba; 2801 uint16_t apptag, appmask; 2802 uint64_t reftag; 2803 size_t len; 2804 uint16_t status; 2805 2806 if (ret < 0) { 2807 iocb->ret = ret; 2808 goto out; 2809 } else if (iocb->ret < 0) { 2810 goto out; 2811 } 2812 2813 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, &slba, 2814 &nlb, &apptag, &appmask, &reftag); 2815 len = nvme_l2b(ns, nlb); 2816 2817 trace_pci_nvme_copy_out(iocb->slba, nlb); 2818 2819 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 2820 NvmeCopyCmd *copy = (NvmeCopyCmd *)&req->cmd; 2821 2822 uint16_t prinfor = ((copy->control[0] >> 4) & 0xf); 2823 uint16_t prinfow = ((copy->control[2] >> 2) & 0xf); 2824 2825 size_t mlen = nvme_m2b(ns, nlb); 2826 uint8_t *mbounce = iocb->bounce + nvme_l2b(ns, nlb); 2827 2828 status = nvme_dif_mangle_mdata(ns, mbounce, mlen, slba); 2829 if (status) { 2830 goto invalid; 2831 } 2832 status = nvme_dif_check(ns, iocb->bounce, len, mbounce, mlen, prinfor, 2833 slba, apptag, appmask, &reftag); 2834 if (status) { 2835 goto invalid; 2836 } 2837 2838 apptag = le16_to_cpu(copy->apptag); 2839 appmask = le16_to_cpu(copy->appmask); 2840 2841 if (prinfow & NVME_PRINFO_PRACT) { 2842 status = nvme_check_prinfo(ns, prinfow, iocb->slba, iocb->reftag); 2843 if (status) { 2844 goto invalid; 2845 } 2846 2847 nvme_dif_pract_generate_dif(ns, iocb->bounce, len, mbounce, mlen, 2848 apptag, &iocb->reftag); 2849 } else { 2850 status = nvme_dif_check(ns, iocb->bounce, len, mbounce, mlen, 2851 prinfow, iocb->slba, apptag, appmask, 2852 &iocb->reftag); 2853 if (status) { 2854 goto invalid; 2855 } 2856 } 2857 } 2858 2859 status = nvme_check_bounds(ns, iocb->slba, nlb); 2860 if (status) { 2861 goto invalid; 2862 } 2863 2864 if (ns->params.zoned) { 2865 status = nvme_check_zone_write(ns, iocb->zone, iocb->slba, nlb); 2866 if (status) { 2867 goto invalid; 2868 } 2869 2870 if (!(iocb->zone->d.za & NVME_ZA_ZRWA_VALID)) { 2871 iocb->zone->w_ptr += nlb; 2872 } 2873 } 2874 2875 qemu_iovec_reset(&iocb->iov); 2876 qemu_iovec_add(&iocb->iov, iocb->bounce, len); 2877 2878 iocb->aiocb = blk_aio_pwritev(ns->blkconf.blk, nvme_l2b(ns, iocb->slba), 2879 &iocb->iov, 0, nvme_copy_out_cb, iocb); 2880 2881 return; 2882 2883 invalid: 2884 req->status = status; 2885 iocb->aiocb = NULL; 2886 if (iocb->bh) { 2887 qemu_bh_schedule(iocb->bh); 2888 } 2889 2890 return; 2891 2892 out: 2893 nvme_copy_cb(iocb, ret); 2894 } 2895 2896 static void nvme_copy_in_cb(void *opaque, int ret) 2897 { 2898 NvmeCopyAIOCB *iocb = opaque; 2899 NvmeRequest *req = iocb->req; 2900 NvmeNamespace *ns = req->ns; 2901 uint64_t slba; 2902 uint32_t nlb; 2903 2904 if (ret < 0) { 2905 iocb->ret = ret; 2906 goto out; 2907 } else if (iocb->ret < 0) { 2908 goto out; 2909 } 2910 2911 if (!ns->lbaf.ms) { 2912 nvme_copy_in_completed_cb(iocb, 0); 2913 return; 2914 } 2915 2916 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, &slba, 2917 &nlb, NULL, NULL, NULL); 2918 2919 qemu_iovec_reset(&iocb->iov); 2920 qemu_iovec_add(&iocb->iov, iocb->bounce + nvme_l2b(ns, nlb), 2921 nvme_m2b(ns, nlb)); 2922 2923 iocb->aiocb = blk_aio_preadv(ns->blkconf.blk, nvme_moff(ns, slba), 2924 &iocb->iov, 0, nvme_copy_in_completed_cb, 2925 iocb); 2926 return; 2927 2928 out: 2929 nvme_copy_cb(iocb, iocb->ret); 2930 } 2931 2932 static void nvme_copy_cb(void *opaque, int ret) 2933 { 2934 NvmeCopyAIOCB *iocb = opaque; 2935 NvmeRequest *req = iocb->req; 2936 NvmeNamespace *ns = req->ns; 2937 uint64_t slba; 2938 uint32_t nlb; 2939 size_t len; 2940 uint16_t status; 2941 2942 if (ret < 0) { 2943 iocb->ret = ret; 2944 goto done; 2945 } else if (iocb->ret < 0) { 2946 goto done; 2947 } 2948 2949 if (iocb->idx == iocb->nr) { 2950 goto done; 2951 } 2952 2953 nvme_copy_source_range_parse(iocb->ranges, iocb->idx, iocb->format, &slba, 2954 &nlb, NULL, NULL, NULL); 2955 len = nvme_l2b(ns, nlb); 2956 2957 trace_pci_nvme_copy_source_range(slba, nlb); 2958 2959 if (nlb > le16_to_cpu(ns->id_ns.mssrl)) { 2960 status = NVME_CMD_SIZE_LIMIT | NVME_DNR; 2961 goto invalid; 2962 } 2963 2964 status = nvme_check_bounds(ns, slba, nlb); 2965 if (status) { 2966 goto invalid; 2967 } 2968 2969 if (NVME_ERR_REC_DULBE(ns->features.err_rec)) { 2970 status = nvme_check_dulbe(ns, slba, nlb); 2971 if (status) { 2972 goto invalid; 2973 } 2974 } 2975 2976 if (ns->params.zoned) { 2977 status = nvme_check_zone_read(ns, slba, nlb); 2978 if (status) { 2979 goto invalid; 2980 } 2981 } 2982 2983 qemu_iovec_reset(&iocb->iov); 2984 qemu_iovec_add(&iocb->iov, iocb->bounce, len); 2985 2986 iocb->aiocb = blk_aio_preadv(ns->blkconf.blk, nvme_l2b(ns, slba), 2987 &iocb->iov, 0, nvme_copy_in_cb, iocb); 2988 return; 2989 2990 invalid: 2991 req->status = status; 2992 done: 2993 iocb->aiocb = NULL; 2994 if (iocb->bh) { 2995 qemu_bh_schedule(iocb->bh); 2996 } 2997 } 2998 2999 3000 static uint16_t nvme_copy(NvmeCtrl *n, NvmeRequest *req) 3001 { 3002 NvmeNamespace *ns = req->ns; 3003 NvmeCopyCmd *copy = (NvmeCopyCmd *)&req->cmd; 3004 NvmeCopyAIOCB *iocb = blk_aio_get(&nvme_copy_aiocb_info, ns->blkconf.blk, 3005 nvme_misc_cb, req); 3006 uint16_t nr = copy->nr + 1; 3007 uint8_t format = copy->control[0] & 0xf; 3008 uint16_t prinfor = ((copy->control[0] >> 4) & 0xf); 3009 uint16_t prinfow = ((copy->control[2] >> 2) & 0xf); 3010 size_t len = sizeof(NvmeCopySourceRangeFormat0); 3011 3012 uint16_t status; 3013 3014 trace_pci_nvme_copy(nvme_cid(req), nvme_nsid(ns), nr, format); 3015 3016 iocb->ranges = NULL; 3017 iocb->zone = NULL; 3018 3019 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) && 3020 ((prinfor & NVME_PRINFO_PRACT) != (prinfow & NVME_PRINFO_PRACT))) { 3021 status = NVME_INVALID_FIELD | NVME_DNR; 3022 goto invalid; 3023 } 3024 3025 if (!(n->id_ctrl.ocfs & (1 << format))) { 3026 trace_pci_nvme_err_copy_invalid_format(format); 3027 status = NVME_INVALID_FIELD | NVME_DNR; 3028 goto invalid; 3029 } 3030 3031 if (nr > ns->id_ns.msrc + 1) { 3032 status = NVME_CMD_SIZE_LIMIT | NVME_DNR; 3033 goto invalid; 3034 } 3035 3036 if (ns->pif && format != 0x1) { 3037 status = NVME_INVALID_FORMAT | NVME_DNR; 3038 goto invalid; 3039 } 3040 3041 if (ns->pif) { 3042 len = sizeof(NvmeCopySourceRangeFormat1); 3043 } 3044 3045 iocb->format = format; 3046 iocb->ranges = g_malloc_n(nr, len); 3047 status = nvme_h2c(n, (uint8_t *)iocb->ranges, len * nr, req); 3048 if (status) { 3049 goto invalid; 3050 } 3051 3052 iocb->slba = le64_to_cpu(copy->sdlba); 3053 3054 if (ns->params.zoned) { 3055 iocb->zone = nvme_get_zone_by_slba(ns, iocb->slba); 3056 if (!iocb->zone) { 3057 status = NVME_LBA_RANGE | NVME_DNR; 3058 goto invalid; 3059 } 3060 3061 status = nvme_zrm_auto(n, ns, iocb->zone); 3062 if (status) { 3063 goto invalid; 3064 } 3065 } 3066 3067 iocb->req = req; 3068 iocb->bh = qemu_bh_new(nvme_copy_bh, iocb); 3069 iocb->ret = 0; 3070 iocb->nr = nr; 3071 iocb->idx = 0; 3072 iocb->reftag = le32_to_cpu(copy->reftag); 3073 iocb->reftag |= (uint64_t)le32_to_cpu(copy->cdw3) << 32; 3074 iocb->bounce = g_malloc_n(le16_to_cpu(ns->id_ns.mssrl), 3075 ns->lbasz + ns->lbaf.ms); 3076 3077 qemu_iovec_init(&iocb->iov, 1); 3078 3079 block_acct_start(blk_get_stats(ns->blkconf.blk), &iocb->acct.read, 0, 3080 BLOCK_ACCT_READ); 3081 block_acct_start(blk_get_stats(ns->blkconf.blk), &iocb->acct.write, 0, 3082 BLOCK_ACCT_WRITE); 3083 3084 req->aiocb = &iocb->common; 3085 nvme_copy_cb(iocb, 0); 3086 3087 return NVME_NO_COMPLETE; 3088 3089 invalid: 3090 g_free(iocb->ranges); 3091 qemu_aio_unref(iocb); 3092 return status; 3093 } 3094 3095 static uint16_t nvme_compare(NvmeCtrl *n, NvmeRequest *req) 3096 { 3097 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 3098 NvmeNamespace *ns = req->ns; 3099 BlockBackend *blk = ns->blkconf.blk; 3100 uint64_t slba = le64_to_cpu(rw->slba); 3101 uint32_t nlb = le16_to_cpu(rw->nlb) + 1; 3102 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control)); 3103 size_t data_len = nvme_l2b(ns, nlb); 3104 size_t len = data_len; 3105 int64_t offset = nvme_l2b(ns, slba); 3106 struct nvme_compare_ctx *ctx = NULL; 3107 uint16_t status; 3108 3109 trace_pci_nvme_compare(nvme_cid(req), nvme_nsid(ns), slba, nlb); 3110 3111 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) && (prinfo & NVME_PRINFO_PRACT)) { 3112 return NVME_INVALID_PROT_INFO | NVME_DNR; 3113 } 3114 3115 if (nvme_ns_ext(ns)) { 3116 len += nvme_m2b(ns, nlb); 3117 } 3118 3119 status = nvme_check_mdts(n, len); 3120 if (status) { 3121 return status; 3122 } 3123 3124 status = nvme_check_bounds(ns, slba, nlb); 3125 if (status) { 3126 return status; 3127 } 3128 3129 if (NVME_ERR_REC_DULBE(ns->features.err_rec)) { 3130 status = nvme_check_dulbe(ns, slba, nlb); 3131 if (status) { 3132 return status; 3133 } 3134 } 3135 3136 status = nvme_map_dptr(n, &req->sg, len, &req->cmd); 3137 if (status) { 3138 return status; 3139 } 3140 3141 ctx = g_new(struct nvme_compare_ctx, 1); 3142 ctx->data.bounce = g_malloc(data_len); 3143 3144 req->opaque = ctx; 3145 3146 qemu_iovec_init(&ctx->data.iov, 1); 3147 qemu_iovec_add(&ctx->data.iov, ctx->data.bounce, data_len); 3148 3149 block_acct_start(blk_get_stats(blk), &req->acct, data_len, 3150 BLOCK_ACCT_READ); 3151 req->aiocb = blk_aio_preadv(blk, offset, &ctx->data.iov, 0, 3152 nvme_compare_data_cb, req); 3153 3154 return NVME_NO_COMPLETE; 3155 } 3156 3157 typedef struct NvmeFlushAIOCB { 3158 BlockAIOCB common; 3159 BlockAIOCB *aiocb; 3160 NvmeRequest *req; 3161 QEMUBH *bh; 3162 int ret; 3163 3164 NvmeNamespace *ns; 3165 uint32_t nsid; 3166 bool broadcast; 3167 } NvmeFlushAIOCB; 3168 3169 static void nvme_flush_cancel(BlockAIOCB *acb) 3170 { 3171 NvmeFlushAIOCB *iocb = container_of(acb, NvmeFlushAIOCB, common); 3172 3173 iocb->ret = -ECANCELED; 3174 3175 if (iocb->aiocb) { 3176 blk_aio_cancel_async(iocb->aiocb); 3177 } 3178 } 3179 3180 static const AIOCBInfo nvme_flush_aiocb_info = { 3181 .aiocb_size = sizeof(NvmeFlushAIOCB), 3182 .cancel_async = nvme_flush_cancel, 3183 .get_aio_context = nvme_get_aio_context, 3184 }; 3185 3186 static void nvme_flush_ns_cb(void *opaque, int ret) 3187 { 3188 NvmeFlushAIOCB *iocb = opaque; 3189 NvmeNamespace *ns = iocb->ns; 3190 3191 if (ret < 0) { 3192 iocb->ret = ret; 3193 goto out; 3194 } else if (iocb->ret < 0) { 3195 goto out; 3196 } 3197 3198 if (ns) { 3199 trace_pci_nvme_flush_ns(iocb->nsid); 3200 3201 iocb->ns = NULL; 3202 iocb->aiocb = blk_aio_flush(ns->blkconf.blk, nvme_flush_ns_cb, iocb); 3203 return; 3204 } 3205 3206 out: 3207 iocb->aiocb = NULL; 3208 qemu_bh_schedule(iocb->bh); 3209 } 3210 3211 static void nvme_flush_bh(void *opaque) 3212 { 3213 NvmeFlushAIOCB *iocb = opaque; 3214 NvmeRequest *req = iocb->req; 3215 NvmeCtrl *n = nvme_ctrl(req); 3216 int i; 3217 3218 if (iocb->ret < 0) { 3219 goto done; 3220 } 3221 3222 if (iocb->broadcast) { 3223 for (i = iocb->nsid + 1; i <= NVME_MAX_NAMESPACES; i++) { 3224 iocb->ns = nvme_ns(n, i); 3225 if (iocb->ns) { 3226 iocb->nsid = i; 3227 break; 3228 } 3229 } 3230 } 3231 3232 if (!iocb->ns) { 3233 goto done; 3234 } 3235 3236 nvme_flush_ns_cb(iocb, 0); 3237 return; 3238 3239 done: 3240 qemu_bh_delete(iocb->bh); 3241 iocb->bh = NULL; 3242 3243 iocb->common.cb(iocb->common.opaque, iocb->ret); 3244 3245 qemu_aio_unref(iocb); 3246 3247 return; 3248 } 3249 3250 static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req) 3251 { 3252 NvmeFlushAIOCB *iocb; 3253 uint32_t nsid = le32_to_cpu(req->cmd.nsid); 3254 uint16_t status; 3255 3256 iocb = qemu_aio_get(&nvme_flush_aiocb_info, NULL, nvme_misc_cb, req); 3257 3258 iocb->req = req; 3259 iocb->bh = qemu_bh_new(nvme_flush_bh, iocb); 3260 iocb->ret = 0; 3261 iocb->ns = NULL; 3262 iocb->nsid = 0; 3263 iocb->broadcast = (nsid == NVME_NSID_BROADCAST); 3264 3265 if (!iocb->broadcast) { 3266 if (!nvme_nsid_valid(n, nsid)) { 3267 status = NVME_INVALID_NSID | NVME_DNR; 3268 goto out; 3269 } 3270 3271 iocb->ns = nvme_ns(n, nsid); 3272 if (!iocb->ns) { 3273 status = NVME_INVALID_FIELD | NVME_DNR; 3274 goto out; 3275 } 3276 3277 iocb->nsid = nsid; 3278 } 3279 3280 req->aiocb = &iocb->common; 3281 qemu_bh_schedule(iocb->bh); 3282 3283 return NVME_NO_COMPLETE; 3284 3285 out: 3286 qemu_bh_delete(iocb->bh); 3287 iocb->bh = NULL; 3288 qemu_aio_unref(iocb); 3289 3290 return status; 3291 } 3292 3293 static uint16_t nvme_read(NvmeCtrl *n, NvmeRequest *req) 3294 { 3295 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 3296 NvmeNamespace *ns = req->ns; 3297 uint64_t slba = le64_to_cpu(rw->slba); 3298 uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1; 3299 uint8_t prinfo = NVME_RW_PRINFO(le16_to_cpu(rw->control)); 3300 uint64_t data_size = nvme_l2b(ns, nlb); 3301 uint64_t mapped_size = data_size; 3302 uint64_t data_offset; 3303 BlockBackend *blk = ns->blkconf.blk; 3304 uint16_t status; 3305 3306 if (nvme_ns_ext(ns)) { 3307 mapped_size += nvme_m2b(ns, nlb); 3308 3309 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 3310 bool pract = prinfo & NVME_PRINFO_PRACT; 3311 3312 if (pract && ns->lbaf.ms == nvme_pi_tuple_size(ns)) { 3313 mapped_size = data_size; 3314 } 3315 } 3316 } 3317 3318 trace_pci_nvme_read(nvme_cid(req), nvme_nsid(ns), nlb, mapped_size, slba); 3319 3320 status = nvme_check_mdts(n, mapped_size); 3321 if (status) { 3322 goto invalid; 3323 } 3324 3325 status = nvme_check_bounds(ns, slba, nlb); 3326 if (status) { 3327 goto invalid; 3328 } 3329 3330 if (ns->params.zoned) { 3331 status = nvme_check_zone_read(ns, slba, nlb); 3332 if (status) { 3333 trace_pci_nvme_err_zone_read_not_ok(slba, nlb, status); 3334 goto invalid; 3335 } 3336 } 3337 3338 if (NVME_ERR_REC_DULBE(ns->features.err_rec)) { 3339 status = nvme_check_dulbe(ns, slba, nlb); 3340 if (status) { 3341 goto invalid; 3342 } 3343 } 3344 3345 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 3346 return nvme_dif_rw(n, req); 3347 } 3348 3349 status = nvme_map_data(n, nlb, req); 3350 if (status) { 3351 goto invalid; 3352 } 3353 3354 data_offset = nvme_l2b(ns, slba); 3355 3356 block_acct_start(blk_get_stats(blk), &req->acct, data_size, 3357 BLOCK_ACCT_READ); 3358 nvme_blk_read(blk, data_offset, nvme_rw_cb, req); 3359 return NVME_NO_COMPLETE; 3360 3361 invalid: 3362 block_acct_invalid(blk_get_stats(blk), BLOCK_ACCT_READ); 3363 return status | NVME_DNR; 3364 } 3365 3366 static uint16_t nvme_do_write(NvmeCtrl *n, NvmeRequest *req, bool append, 3367 bool wrz) 3368 { 3369 NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd; 3370 NvmeNamespace *ns = req->ns; 3371 uint64_t slba = le64_to_cpu(rw->slba); 3372 uint32_t nlb = (uint32_t)le16_to_cpu(rw->nlb) + 1; 3373 uint16_t ctrl = le16_to_cpu(rw->control); 3374 uint8_t prinfo = NVME_RW_PRINFO(ctrl); 3375 uint64_t data_size = nvme_l2b(ns, nlb); 3376 uint64_t mapped_size = data_size; 3377 uint64_t data_offset; 3378 NvmeZone *zone; 3379 NvmeZonedResult *res = (NvmeZonedResult *)&req->cqe; 3380 BlockBackend *blk = ns->blkconf.blk; 3381 uint16_t status; 3382 3383 if (nvme_ns_ext(ns)) { 3384 mapped_size += nvme_m2b(ns, nlb); 3385 3386 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 3387 bool pract = prinfo & NVME_PRINFO_PRACT; 3388 3389 if (pract && ns->lbaf.ms == nvme_pi_tuple_size(ns)) { 3390 mapped_size -= nvme_m2b(ns, nlb); 3391 } 3392 } 3393 } 3394 3395 trace_pci_nvme_write(nvme_cid(req), nvme_io_opc_str(rw->opcode), 3396 nvme_nsid(ns), nlb, mapped_size, slba); 3397 3398 if (!wrz) { 3399 status = nvme_check_mdts(n, mapped_size); 3400 if (status) { 3401 goto invalid; 3402 } 3403 } 3404 3405 status = nvme_check_bounds(ns, slba, nlb); 3406 if (status) { 3407 goto invalid; 3408 } 3409 3410 if (ns->params.zoned) { 3411 zone = nvme_get_zone_by_slba(ns, slba); 3412 assert(zone); 3413 3414 if (append) { 3415 bool piremap = !!(ctrl & NVME_RW_PIREMAP); 3416 3417 if (unlikely(zone->d.za & NVME_ZA_ZRWA_VALID)) { 3418 return NVME_INVALID_ZONE_OP | NVME_DNR; 3419 } 3420 3421 if (unlikely(slba != zone->d.zslba)) { 3422 trace_pci_nvme_err_append_not_at_start(slba, zone->d.zslba); 3423 status = NVME_INVALID_FIELD; 3424 goto invalid; 3425 } 3426 3427 if (n->params.zasl && 3428 data_size > (uint64_t)n->page_size << n->params.zasl) { 3429 trace_pci_nvme_err_zasl(data_size); 3430 return NVME_INVALID_FIELD | NVME_DNR; 3431 } 3432 3433 slba = zone->w_ptr; 3434 rw->slba = cpu_to_le64(slba); 3435 res->slba = cpu_to_le64(slba); 3436 3437 switch (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 3438 case NVME_ID_NS_DPS_TYPE_1: 3439 if (!piremap) { 3440 return NVME_INVALID_PROT_INFO | NVME_DNR; 3441 } 3442 3443 /* fallthrough */ 3444 3445 case NVME_ID_NS_DPS_TYPE_2: 3446 if (piremap) { 3447 uint32_t reftag = le32_to_cpu(rw->reftag); 3448 rw->reftag = cpu_to_le32(reftag + (slba - zone->d.zslba)); 3449 } 3450 3451 break; 3452 3453 case NVME_ID_NS_DPS_TYPE_3: 3454 if (piremap) { 3455 return NVME_INVALID_PROT_INFO | NVME_DNR; 3456 } 3457 3458 break; 3459 } 3460 } 3461 3462 status = nvme_check_zone_write(ns, zone, slba, nlb); 3463 if (status) { 3464 goto invalid; 3465 } 3466 3467 status = nvme_zrm_auto(n, ns, zone); 3468 if (status) { 3469 goto invalid; 3470 } 3471 3472 if (!(zone->d.za & NVME_ZA_ZRWA_VALID)) { 3473 zone->w_ptr += nlb; 3474 } 3475 } 3476 3477 data_offset = nvme_l2b(ns, slba); 3478 3479 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { 3480 return nvme_dif_rw(n, req); 3481 } 3482 3483 if (!wrz) { 3484 status = nvme_map_data(n, nlb, req); 3485 if (status) { 3486 goto invalid; 3487 } 3488 3489 block_acct_start(blk_get_stats(blk), &req->acct, data_size, 3490 BLOCK_ACCT_WRITE); 3491 nvme_blk_write(blk, data_offset, nvme_rw_cb, req); 3492 } else { 3493 req->aiocb = blk_aio_pwrite_zeroes(blk, data_offset, data_size, 3494 BDRV_REQ_MAY_UNMAP, nvme_rw_cb, 3495 req); 3496 } 3497 3498 return NVME_NO_COMPLETE; 3499 3500 invalid: 3501 block_acct_invalid(blk_get_stats(blk), BLOCK_ACCT_WRITE); 3502 return status | NVME_DNR; 3503 } 3504 3505 static inline uint16_t nvme_write(NvmeCtrl *n, NvmeRequest *req) 3506 { 3507 return nvme_do_write(n, req, false, false); 3508 } 3509 3510 static inline uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req) 3511 { 3512 return nvme_do_write(n, req, false, true); 3513 } 3514 3515 static inline uint16_t nvme_zone_append(NvmeCtrl *n, NvmeRequest *req) 3516 { 3517 return nvme_do_write(n, req, true, false); 3518 } 3519 3520 static uint16_t nvme_get_mgmt_zone_slba_idx(NvmeNamespace *ns, NvmeCmd *c, 3521 uint64_t *slba, uint32_t *zone_idx) 3522 { 3523 uint32_t dw10 = le32_to_cpu(c->cdw10); 3524 uint32_t dw11 = le32_to_cpu(c->cdw11); 3525 3526 if (!ns->params.zoned) { 3527 trace_pci_nvme_err_invalid_opc(c->opcode); 3528 return NVME_INVALID_OPCODE | NVME_DNR; 3529 } 3530 3531 *slba = ((uint64_t)dw11) << 32 | dw10; 3532 if (unlikely(*slba >= ns->id_ns.nsze)) { 3533 trace_pci_nvme_err_invalid_lba_range(*slba, 0, ns->id_ns.nsze); 3534 *slba = 0; 3535 return NVME_LBA_RANGE | NVME_DNR; 3536 } 3537 3538 *zone_idx = nvme_zone_idx(ns, *slba); 3539 assert(*zone_idx < ns->num_zones); 3540 3541 return NVME_SUCCESS; 3542 } 3543 3544 typedef uint16_t (*op_handler_t)(NvmeNamespace *, NvmeZone *, NvmeZoneState, 3545 NvmeRequest *); 3546 3547 enum NvmeZoneProcessingMask { 3548 NVME_PROC_CURRENT_ZONE = 0, 3549 NVME_PROC_OPENED_ZONES = 1 << 0, 3550 NVME_PROC_CLOSED_ZONES = 1 << 1, 3551 NVME_PROC_READ_ONLY_ZONES = 1 << 2, 3552 NVME_PROC_FULL_ZONES = 1 << 3, 3553 }; 3554 3555 static uint16_t nvme_open_zone(NvmeNamespace *ns, NvmeZone *zone, 3556 NvmeZoneState state, NvmeRequest *req) 3557 { 3558 NvmeZoneSendCmd *cmd = (NvmeZoneSendCmd *)&req->cmd; 3559 int flags = 0; 3560 3561 if (cmd->zsflags & NVME_ZSFLAG_ZRWA_ALLOC) { 3562 uint16_t ozcs = le16_to_cpu(ns->id_ns_zoned->ozcs); 3563 3564 if (!(ozcs & NVME_ID_NS_ZONED_OZCS_ZRWASUP)) { 3565 return NVME_INVALID_ZONE_OP | NVME_DNR; 3566 } 3567 3568 if (zone->w_ptr % ns->zns.zrwafg) { 3569 return NVME_NOZRWA | NVME_DNR; 3570 } 3571 3572 flags = NVME_ZRM_ZRWA; 3573 } 3574 3575 return nvme_zrm_open_flags(nvme_ctrl(req), ns, zone, flags); 3576 } 3577 3578 static uint16_t nvme_close_zone(NvmeNamespace *ns, NvmeZone *zone, 3579 NvmeZoneState state, NvmeRequest *req) 3580 { 3581 return nvme_zrm_close(ns, zone); 3582 } 3583 3584 static uint16_t nvme_finish_zone(NvmeNamespace *ns, NvmeZone *zone, 3585 NvmeZoneState state, NvmeRequest *req) 3586 { 3587 return nvme_zrm_finish(ns, zone); 3588 } 3589 3590 static uint16_t nvme_offline_zone(NvmeNamespace *ns, NvmeZone *zone, 3591 NvmeZoneState state, NvmeRequest *req) 3592 { 3593 switch (state) { 3594 case NVME_ZONE_STATE_READ_ONLY: 3595 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_OFFLINE); 3596 /* fall through */ 3597 case NVME_ZONE_STATE_OFFLINE: 3598 return NVME_SUCCESS; 3599 default: 3600 return NVME_ZONE_INVAL_TRANSITION; 3601 } 3602 } 3603 3604 static uint16_t nvme_set_zd_ext(NvmeNamespace *ns, NvmeZone *zone) 3605 { 3606 uint16_t status; 3607 uint8_t state = nvme_get_zone_state(zone); 3608 3609 if (state == NVME_ZONE_STATE_EMPTY) { 3610 status = nvme_aor_check(ns, 1, 0); 3611 if (status) { 3612 return status; 3613 } 3614 nvme_aor_inc_active(ns); 3615 zone->d.za |= NVME_ZA_ZD_EXT_VALID; 3616 nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_CLOSED); 3617 return NVME_SUCCESS; 3618 } 3619 3620 return NVME_ZONE_INVAL_TRANSITION; 3621 } 3622 3623 static uint16_t nvme_bulk_proc_zone(NvmeNamespace *ns, NvmeZone *zone, 3624 enum NvmeZoneProcessingMask proc_mask, 3625 op_handler_t op_hndlr, NvmeRequest *req) 3626 { 3627 uint16_t status = NVME_SUCCESS; 3628 NvmeZoneState zs = nvme_get_zone_state(zone); 3629 bool proc_zone; 3630 3631 switch (zs) { 3632 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 3633 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 3634 proc_zone = proc_mask & NVME_PROC_OPENED_ZONES; 3635 break; 3636 case NVME_ZONE_STATE_CLOSED: 3637 proc_zone = proc_mask & NVME_PROC_CLOSED_ZONES; 3638 break; 3639 case NVME_ZONE_STATE_READ_ONLY: 3640 proc_zone = proc_mask & NVME_PROC_READ_ONLY_ZONES; 3641 break; 3642 case NVME_ZONE_STATE_FULL: 3643 proc_zone = proc_mask & NVME_PROC_FULL_ZONES; 3644 break; 3645 default: 3646 proc_zone = false; 3647 } 3648 3649 if (proc_zone) { 3650 status = op_hndlr(ns, zone, zs, req); 3651 } 3652 3653 return status; 3654 } 3655 3656 static uint16_t nvme_do_zone_op(NvmeNamespace *ns, NvmeZone *zone, 3657 enum NvmeZoneProcessingMask proc_mask, 3658 op_handler_t op_hndlr, NvmeRequest *req) 3659 { 3660 NvmeZone *next; 3661 uint16_t status = NVME_SUCCESS; 3662 int i; 3663 3664 if (!proc_mask) { 3665 status = op_hndlr(ns, zone, nvme_get_zone_state(zone), req); 3666 } else { 3667 if (proc_mask & NVME_PROC_CLOSED_ZONES) { 3668 QTAILQ_FOREACH_SAFE(zone, &ns->closed_zones, entry, next) { 3669 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr, 3670 req); 3671 if (status && status != NVME_NO_COMPLETE) { 3672 goto out; 3673 } 3674 } 3675 } 3676 if (proc_mask & NVME_PROC_OPENED_ZONES) { 3677 QTAILQ_FOREACH_SAFE(zone, &ns->imp_open_zones, entry, next) { 3678 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr, 3679 req); 3680 if (status && status != NVME_NO_COMPLETE) { 3681 goto out; 3682 } 3683 } 3684 3685 QTAILQ_FOREACH_SAFE(zone, &ns->exp_open_zones, entry, next) { 3686 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr, 3687 req); 3688 if (status && status != NVME_NO_COMPLETE) { 3689 goto out; 3690 } 3691 } 3692 } 3693 if (proc_mask & NVME_PROC_FULL_ZONES) { 3694 QTAILQ_FOREACH_SAFE(zone, &ns->full_zones, entry, next) { 3695 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr, 3696 req); 3697 if (status && status != NVME_NO_COMPLETE) { 3698 goto out; 3699 } 3700 } 3701 } 3702 3703 if (proc_mask & NVME_PROC_READ_ONLY_ZONES) { 3704 for (i = 0; i < ns->num_zones; i++, zone++) { 3705 status = nvme_bulk_proc_zone(ns, zone, proc_mask, op_hndlr, 3706 req); 3707 if (status && status != NVME_NO_COMPLETE) { 3708 goto out; 3709 } 3710 } 3711 } 3712 } 3713 3714 out: 3715 return status; 3716 } 3717 3718 typedef struct NvmeZoneResetAIOCB { 3719 BlockAIOCB common; 3720 BlockAIOCB *aiocb; 3721 NvmeRequest *req; 3722 QEMUBH *bh; 3723 int ret; 3724 3725 bool all; 3726 int idx; 3727 NvmeZone *zone; 3728 } NvmeZoneResetAIOCB; 3729 3730 static void nvme_zone_reset_cancel(BlockAIOCB *aiocb) 3731 { 3732 NvmeZoneResetAIOCB *iocb = container_of(aiocb, NvmeZoneResetAIOCB, common); 3733 NvmeRequest *req = iocb->req; 3734 NvmeNamespace *ns = req->ns; 3735 3736 iocb->idx = ns->num_zones; 3737 3738 iocb->ret = -ECANCELED; 3739 3740 if (iocb->aiocb) { 3741 blk_aio_cancel_async(iocb->aiocb); 3742 iocb->aiocb = NULL; 3743 } 3744 } 3745 3746 static const AIOCBInfo nvme_zone_reset_aiocb_info = { 3747 .aiocb_size = sizeof(NvmeZoneResetAIOCB), 3748 .cancel_async = nvme_zone_reset_cancel, 3749 }; 3750 3751 static void nvme_zone_reset_bh(void *opaque) 3752 { 3753 NvmeZoneResetAIOCB *iocb = opaque; 3754 3755 iocb->common.cb(iocb->common.opaque, iocb->ret); 3756 3757 qemu_bh_delete(iocb->bh); 3758 iocb->bh = NULL; 3759 qemu_aio_unref(iocb); 3760 } 3761 3762 static void nvme_zone_reset_cb(void *opaque, int ret); 3763 3764 static void nvme_zone_reset_epilogue_cb(void *opaque, int ret) 3765 { 3766 NvmeZoneResetAIOCB *iocb = opaque; 3767 NvmeRequest *req = iocb->req; 3768 NvmeNamespace *ns = req->ns; 3769 int64_t moff; 3770 int count; 3771 3772 if (ret < 0) { 3773 nvme_zone_reset_cb(iocb, ret); 3774 return; 3775 } 3776 3777 if (!ns->lbaf.ms) { 3778 nvme_zone_reset_cb(iocb, 0); 3779 return; 3780 } 3781 3782 moff = nvme_moff(ns, iocb->zone->d.zslba); 3783 count = nvme_m2b(ns, ns->zone_size); 3784 3785 iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, moff, count, 3786 BDRV_REQ_MAY_UNMAP, 3787 nvme_zone_reset_cb, iocb); 3788 return; 3789 } 3790 3791 static void nvme_zone_reset_cb(void *opaque, int ret) 3792 { 3793 NvmeZoneResetAIOCB *iocb = opaque; 3794 NvmeRequest *req = iocb->req; 3795 NvmeNamespace *ns = req->ns; 3796 3797 if (ret < 0) { 3798 iocb->ret = ret; 3799 goto done; 3800 } 3801 3802 if (iocb->zone) { 3803 nvme_zrm_reset(ns, iocb->zone); 3804 3805 if (!iocb->all) { 3806 goto done; 3807 } 3808 } 3809 3810 while (iocb->idx < ns->num_zones) { 3811 NvmeZone *zone = &ns->zone_array[iocb->idx++]; 3812 3813 switch (nvme_get_zone_state(zone)) { 3814 case NVME_ZONE_STATE_EMPTY: 3815 if (!iocb->all) { 3816 goto done; 3817 } 3818 3819 continue; 3820 3821 case NVME_ZONE_STATE_EXPLICITLY_OPEN: 3822 case NVME_ZONE_STATE_IMPLICITLY_OPEN: 3823 case NVME_ZONE_STATE_CLOSED: 3824 case NVME_ZONE_STATE_FULL: 3825 iocb->zone = zone; 3826 break; 3827 3828 default: 3829 continue; 3830 } 3831 3832 trace_pci_nvme_zns_zone_reset(zone->d.zslba); 3833 3834 iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, 3835 nvme_l2b(ns, zone->d.zslba), 3836 nvme_l2b(ns, ns->zone_size), 3837 BDRV_REQ_MAY_UNMAP, 3838 nvme_zone_reset_epilogue_cb, 3839 iocb); 3840 return; 3841 } 3842 3843 done: 3844 iocb->aiocb = NULL; 3845 if (iocb->bh) { 3846 qemu_bh_schedule(iocb->bh); 3847 } 3848 } 3849 3850 static uint16_t nvme_zone_mgmt_send_zrwa_flush(NvmeCtrl *n, NvmeZone *zone, 3851 uint64_t elba, NvmeRequest *req) 3852 { 3853 NvmeNamespace *ns = req->ns; 3854 uint16_t ozcs = le16_to_cpu(ns->id_ns_zoned->ozcs); 3855 uint64_t wp = zone->d.wp; 3856 uint32_t nlb = elba - wp + 1; 3857 uint16_t status; 3858 3859 3860 if (!(ozcs & NVME_ID_NS_ZONED_OZCS_ZRWASUP)) { 3861 return NVME_INVALID_ZONE_OP | NVME_DNR; 3862 } 3863 3864 if (!(zone->d.za & NVME_ZA_ZRWA_VALID)) { 3865 return NVME_INVALID_FIELD | NVME_DNR; 3866 } 3867 3868 if (elba < wp || elba > wp + ns->zns.zrwas) { 3869 return NVME_ZONE_BOUNDARY_ERROR | NVME_DNR; 3870 } 3871 3872 if (nlb % ns->zns.zrwafg) { 3873 return NVME_INVALID_FIELD | NVME_DNR; 3874 } 3875 3876 status = nvme_zrm_auto(n, ns, zone); 3877 if (status) { 3878 return status; 3879 } 3880 3881 zone->w_ptr += nlb; 3882 3883 nvme_advance_zone_wp(ns, zone, nlb); 3884 3885 return NVME_SUCCESS; 3886 } 3887 3888 static uint16_t nvme_zone_mgmt_send(NvmeCtrl *n, NvmeRequest *req) 3889 { 3890 NvmeZoneSendCmd *cmd = (NvmeZoneSendCmd *)&req->cmd; 3891 NvmeNamespace *ns = req->ns; 3892 NvmeZone *zone; 3893 NvmeZoneResetAIOCB *iocb; 3894 uint8_t *zd_ext; 3895 uint64_t slba = 0; 3896 uint32_t zone_idx = 0; 3897 uint16_t status; 3898 uint8_t action = cmd->zsa; 3899 bool all; 3900 enum NvmeZoneProcessingMask proc_mask = NVME_PROC_CURRENT_ZONE; 3901 3902 all = cmd->zsflags & NVME_ZSFLAG_SELECT_ALL; 3903 3904 req->status = NVME_SUCCESS; 3905 3906 if (!all) { 3907 status = nvme_get_mgmt_zone_slba_idx(ns, &req->cmd, &slba, &zone_idx); 3908 if (status) { 3909 return status; 3910 } 3911 } 3912 3913 zone = &ns->zone_array[zone_idx]; 3914 if (slba != zone->d.zslba && action != NVME_ZONE_ACTION_ZRWA_FLUSH) { 3915 trace_pci_nvme_err_unaligned_zone_cmd(action, slba, zone->d.zslba); 3916 return NVME_INVALID_FIELD | NVME_DNR; 3917 } 3918 3919 switch (action) { 3920 3921 case NVME_ZONE_ACTION_OPEN: 3922 if (all) { 3923 proc_mask = NVME_PROC_CLOSED_ZONES; 3924 } 3925 trace_pci_nvme_open_zone(slba, zone_idx, all); 3926 status = nvme_do_zone_op(ns, zone, proc_mask, nvme_open_zone, req); 3927 break; 3928 3929 case NVME_ZONE_ACTION_CLOSE: 3930 if (all) { 3931 proc_mask = NVME_PROC_OPENED_ZONES; 3932 } 3933 trace_pci_nvme_close_zone(slba, zone_idx, all); 3934 status = nvme_do_zone_op(ns, zone, proc_mask, nvme_close_zone, req); 3935 break; 3936 3937 case NVME_ZONE_ACTION_FINISH: 3938 if (all) { 3939 proc_mask = NVME_PROC_OPENED_ZONES | NVME_PROC_CLOSED_ZONES; 3940 } 3941 trace_pci_nvme_finish_zone(slba, zone_idx, all); 3942 status = nvme_do_zone_op(ns, zone, proc_mask, nvme_finish_zone, req); 3943 break; 3944 3945 case NVME_ZONE_ACTION_RESET: 3946 trace_pci_nvme_reset_zone(slba, zone_idx, all); 3947 3948 iocb = blk_aio_get(&nvme_zone_reset_aiocb_info, ns->blkconf.blk, 3949 nvme_misc_cb, req); 3950 3951 iocb->req = req; 3952 iocb->bh = qemu_bh_new(nvme_zone_reset_bh, iocb); 3953 iocb->ret = 0; 3954 iocb->all = all; 3955 iocb->idx = zone_idx; 3956 iocb->zone = NULL; 3957 3958 req->aiocb = &iocb->common; 3959 nvme_zone_reset_cb(iocb, 0); 3960 3961 return NVME_NO_COMPLETE; 3962 3963 case NVME_ZONE_ACTION_OFFLINE: 3964 if (all) { 3965 proc_mask = NVME_PROC_READ_ONLY_ZONES; 3966 } 3967 trace_pci_nvme_offline_zone(slba, zone_idx, all); 3968 status = nvme_do_zone_op(ns, zone, proc_mask, nvme_offline_zone, req); 3969 break; 3970 3971 case NVME_ZONE_ACTION_SET_ZD_EXT: 3972 trace_pci_nvme_set_descriptor_extension(slba, zone_idx); 3973 if (all || !ns->params.zd_extension_size) { 3974 return NVME_INVALID_FIELD | NVME_DNR; 3975 } 3976 zd_ext = nvme_get_zd_extension(ns, zone_idx); 3977 status = nvme_h2c(n, zd_ext, ns->params.zd_extension_size, req); 3978 if (status) { 3979 trace_pci_nvme_err_zd_extension_map_error(zone_idx); 3980 return status; 3981 } 3982 3983 status = nvme_set_zd_ext(ns, zone); 3984 if (status == NVME_SUCCESS) { 3985 trace_pci_nvme_zd_extension_set(zone_idx); 3986 return status; 3987 } 3988 break; 3989 3990 case NVME_ZONE_ACTION_ZRWA_FLUSH: 3991 if (all) { 3992 return NVME_INVALID_FIELD | NVME_DNR; 3993 } 3994 3995 return nvme_zone_mgmt_send_zrwa_flush(n, zone, slba, req); 3996 3997 default: 3998 trace_pci_nvme_err_invalid_mgmt_action(action); 3999 status = NVME_INVALID_FIELD; 4000 } 4001 4002 if (status == NVME_ZONE_INVAL_TRANSITION) { 4003 trace_pci_nvme_err_invalid_zone_state_transition(action, slba, 4004 zone->d.za); 4005 } 4006 if (status) { 4007 status |= NVME_DNR; 4008 } 4009 4010 return status; 4011 } 4012 4013 static bool nvme_zone_matches_filter(uint32_t zafs, NvmeZone *zl) 4014 { 4015 NvmeZoneState zs = nvme_get_zone_state(zl); 4016 4017 switch (zafs) { 4018 case NVME_ZONE_REPORT_ALL: 4019 return true; 4020 case NVME_ZONE_REPORT_EMPTY: 4021 return zs == NVME_ZONE_STATE_EMPTY; 4022 case NVME_ZONE_REPORT_IMPLICITLY_OPEN: 4023 return zs == NVME_ZONE_STATE_IMPLICITLY_OPEN; 4024 case NVME_ZONE_REPORT_EXPLICITLY_OPEN: 4025 return zs == NVME_ZONE_STATE_EXPLICITLY_OPEN; 4026 case NVME_ZONE_REPORT_CLOSED: 4027 return zs == NVME_ZONE_STATE_CLOSED; 4028 case NVME_ZONE_REPORT_FULL: 4029 return zs == NVME_ZONE_STATE_FULL; 4030 case NVME_ZONE_REPORT_READ_ONLY: 4031 return zs == NVME_ZONE_STATE_READ_ONLY; 4032 case NVME_ZONE_REPORT_OFFLINE: 4033 return zs == NVME_ZONE_STATE_OFFLINE; 4034 default: 4035 return false; 4036 } 4037 } 4038 4039 static uint16_t nvme_zone_mgmt_recv(NvmeCtrl *n, NvmeRequest *req) 4040 { 4041 NvmeCmd *cmd = (NvmeCmd *)&req->cmd; 4042 NvmeNamespace *ns = req->ns; 4043 /* cdw12 is zero-based number of dwords to return. Convert to bytes */ 4044 uint32_t data_size = (le32_to_cpu(cmd->cdw12) + 1) << 2; 4045 uint32_t dw13 = le32_to_cpu(cmd->cdw13); 4046 uint32_t zone_idx, zra, zrasf, partial; 4047 uint64_t max_zones, nr_zones = 0; 4048 uint16_t status; 4049 uint64_t slba; 4050 NvmeZoneDescr *z; 4051 NvmeZone *zone; 4052 NvmeZoneReportHeader *header; 4053 void *buf, *buf_p; 4054 size_t zone_entry_sz; 4055 int i; 4056 4057 req->status = NVME_SUCCESS; 4058 4059 status = nvme_get_mgmt_zone_slba_idx(ns, cmd, &slba, &zone_idx); 4060 if (status) { 4061 return status; 4062 } 4063 4064 zra = dw13 & 0xff; 4065 if (zra != NVME_ZONE_REPORT && zra != NVME_ZONE_REPORT_EXTENDED) { 4066 return NVME_INVALID_FIELD | NVME_DNR; 4067 } 4068 if (zra == NVME_ZONE_REPORT_EXTENDED && !ns->params.zd_extension_size) { 4069 return NVME_INVALID_FIELD | NVME_DNR; 4070 } 4071 4072 zrasf = (dw13 >> 8) & 0xff; 4073 if (zrasf > NVME_ZONE_REPORT_OFFLINE) { 4074 return NVME_INVALID_FIELD | NVME_DNR; 4075 } 4076 4077 if (data_size < sizeof(NvmeZoneReportHeader)) { 4078 return NVME_INVALID_FIELD | NVME_DNR; 4079 } 4080 4081 status = nvme_check_mdts(n, data_size); 4082 if (status) { 4083 return status; 4084 } 4085 4086 partial = (dw13 >> 16) & 0x01; 4087 4088 zone_entry_sz = sizeof(NvmeZoneDescr); 4089 if (zra == NVME_ZONE_REPORT_EXTENDED) { 4090 zone_entry_sz += ns->params.zd_extension_size; 4091 } 4092 4093 max_zones = (data_size - sizeof(NvmeZoneReportHeader)) / zone_entry_sz; 4094 buf = g_malloc0(data_size); 4095 4096 zone = &ns->zone_array[zone_idx]; 4097 for (i = zone_idx; i < ns->num_zones; i++) { 4098 if (partial && nr_zones >= max_zones) { 4099 break; 4100 } 4101 if (nvme_zone_matches_filter(zrasf, zone++)) { 4102 nr_zones++; 4103 } 4104 } 4105 header = (NvmeZoneReportHeader *)buf; 4106 header->nr_zones = cpu_to_le64(nr_zones); 4107 4108 buf_p = buf + sizeof(NvmeZoneReportHeader); 4109 for (; zone_idx < ns->num_zones && max_zones > 0; zone_idx++) { 4110 zone = &ns->zone_array[zone_idx]; 4111 if (nvme_zone_matches_filter(zrasf, zone)) { 4112 z = (NvmeZoneDescr *)buf_p; 4113 buf_p += sizeof(NvmeZoneDescr); 4114 4115 z->zt = zone->d.zt; 4116 z->zs = zone->d.zs; 4117 z->zcap = cpu_to_le64(zone->d.zcap); 4118 z->zslba = cpu_to_le64(zone->d.zslba); 4119 z->za = zone->d.za; 4120 4121 if (nvme_wp_is_valid(zone)) { 4122 z->wp = cpu_to_le64(zone->d.wp); 4123 } else { 4124 z->wp = cpu_to_le64(~0ULL); 4125 } 4126 4127 if (zra == NVME_ZONE_REPORT_EXTENDED) { 4128 if (zone->d.za & NVME_ZA_ZD_EXT_VALID) { 4129 memcpy(buf_p, nvme_get_zd_extension(ns, zone_idx), 4130 ns->params.zd_extension_size); 4131 } 4132 buf_p += ns->params.zd_extension_size; 4133 } 4134 4135 max_zones--; 4136 } 4137 } 4138 4139 status = nvme_c2h(n, (uint8_t *)buf, data_size, req); 4140 4141 g_free(buf); 4142 4143 return status; 4144 } 4145 4146 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req) 4147 { 4148 NvmeNamespace *ns; 4149 uint32_t nsid = le32_to_cpu(req->cmd.nsid); 4150 4151 trace_pci_nvme_io_cmd(nvme_cid(req), nsid, nvme_sqid(req), 4152 req->cmd.opcode, nvme_io_opc_str(req->cmd.opcode)); 4153 4154 if (!nvme_nsid_valid(n, nsid)) { 4155 return NVME_INVALID_NSID | NVME_DNR; 4156 } 4157 4158 /* 4159 * In the base NVM command set, Flush may apply to all namespaces 4160 * (indicated by NSID being set to FFFFFFFFh). But if that feature is used 4161 * along with TP 4056 (Namespace Types), it may be pretty screwed up. 4162 * 4163 * If NSID is indeed set to FFFFFFFFh, we simply cannot associate the 4164 * opcode with a specific command since we cannot determine a unique I/O 4165 * command set. Opcode 0h could have any other meaning than something 4166 * equivalent to flushing and say it DOES have completely different 4167 * semantics in some other command set - does an NSID of FFFFFFFFh then 4168 * mean "for all namespaces, apply whatever command set specific command 4169 * that uses the 0h opcode?" Or does it mean "for all namespaces, apply 4170 * whatever command that uses the 0h opcode if, and only if, it allows NSID 4171 * to be FFFFFFFFh"? 4172 * 4173 * Anyway (and luckily), for now, we do not care about this since the 4174 * device only supports namespace types that includes the NVM Flush command 4175 * (NVM and Zoned), so always do an NVM Flush. 4176 */ 4177 if (req->cmd.opcode == NVME_CMD_FLUSH) { 4178 return nvme_flush(n, req); 4179 } 4180 4181 ns = nvme_ns(n, nsid); 4182 if (unlikely(!ns)) { 4183 return NVME_INVALID_FIELD | NVME_DNR; 4184 } 4185 4186 if (!(ns->iocs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) { 4187 trace_pci_nvme_err_invalid_opc(req->cmd.opcode); 4188 return NVME_INVALID_OPCODE | NVME_DNR; 4189 } 4190 4191 if (ns->status) { 4192 return ns->status; 4193 } 4194 4195 if (NVME_CMD_FLAGS_FUSE(req->cmd.flags)) { 4196 return NVME_INVALID_FIELD; 4197 } 4198 4199 req->ns = ns; 4200 4201 switch (req->cmd.opcode) { 4202 case NVME_CMD_WRITE_ZEROES: 4203 return nvme_write_zeroes(n, req); 4204 case NVME_CMD_ZONE_APPEND: 4205 return nvme_zone_append(n, req); 4206 case NVME_CMD_WRITE: 4207 return nvme_write(n, req); 4208 case NVME_CMD_READ: 4209 return nvme_read(n, req); 4210 case NVME_CMD_COMPARE: 4211 return nvme_compare(n, req); 4212 case NVME_CMD_DSM: 4213 return nvme_dsm(n, req); 4214 case NVME_CMD_VERIFY: 4215 return nvme_verify(n, req); 4216 case NVME_CMD_COPY: 4217 return nvme_copy(n, req); 4218 case NVME_CMD_ZONE_MGMT_SEND: 4219 return nvme_zone_mgmt_send(n, req); 4220 case NVME_CMD_ZONE_MGMT_RECV: 4221 return nvme_zone_mgmt_recv(n, req); 4222 default: 4223 assert(false); 4224 } 4225 4226 return NVME_INVALID_OPCODE | NVME_DNR; 4227 } 4228 4229 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n) 4230 { 4231 n->sq[sq->sqid] = NULL; 4232 timer_free(sq->timer); 4233 g_free(sq->io_req); 4234 if (sq->sqid) { 4235 g_free(sq); 4236 } 4237 } 4238 4239 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeRequest *req) 4240 { 4241 NvmeDeleteQ *c = (NvmeDeleteQ *)&req->cmd; 4242 NvmeRequest *r, *next; 4243 NvmeSQueue *sq; 4244 NvmeCQueue *cq; 4245 uint16_t qid = le16_to_cpu(c->qid); 4246 4247 if (unlikely(!qid || nvme_check_sqid(n, qid))) { 4248 trace_pci_nvme_err_invalid_del_sq(qid); 4249 return NVME_INVALID_QID | NVME_DNR; 4250 } 4251 4252 trace_pci_nvme_del_sq(qid); 4253 4254 sq = n->sq[qid]; 4255 while (!QTAILQ_EMPTY(&sq->out_req_list)) { 4256 r = QTAILQ_FIRST(&sq->out_req_list); 4257 assert(r->aiocb); 4258 blk_aio_cancel(r->aiocb); 4259 } 4260 4261 assert(QTAILQ_EMPTY(&sq->out_req_list)); 4262 4263 if (!nvme_check_cqid(n, sq->cqid)) { 4264 cq = n->cq[sq->cqid]; 4265 QTAILQ_REMOVE(&cq->sq_list, sq, entry); 4266 4267 nvme_post_cqes(cq); 4268 QTAILQ_FOREACH_SAFE(r, &cq->req_list, entry, next) { 4269 if (r->sq == sq) { 4270 QTAILQ_REMOVE(&cq->req_list, r, entry); 4271 QTAILQ_INSERT_TAIL(&sq->req_list, r, entry); 4272 } 4273 } 4274 } 4275 4276 nvme_free_sq(sq, n); 4277 return NVME_SUCCESS; 4278 } 4279 4280 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr, 4281 uint16_t sqid, uint16_t cqid, uint16_t size) 4282 { 4283 int i; 4284 NvmeCQueue *cq; 4285 4286 sq->ctrl = n; 4287 sq->dma_addr = dma_addr; 4288 sq->sqid = sqid; 4289 sq->size = size; 4290 sq->cqid = cqid; 4291 sq->head = sq->tail = 0; 4292 sq->io_req = g_new0(NvmeRequest, sq->size); 4293 4294 QTAILQ_INIT(&sq->req_list); 4295 QTAILQ_INIT(&sq->out_req_list); 4296 for (i = 0; i < sq->size; i++) { 4297 sq->io_req[i].sq = sq; 4298 QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry); 4299 } 4300 sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq); 4301 4302 if (n->dbbuf_enabled) { 4303 sq->db_addr = n->dbbuf_dbs + (sqid << 3); 4304 sq->ei_addr = n->dbbuf_eis + (sqid << 3); 4305 } 4306 4307 assert(n->cq[cqid]); 4308 cq = n->cq[cqid]; 4309 QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry); 4310 n->sq[sqid] = sq; 4311 } 4312 4313 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req) 4314 { 4315 NvmeSQueue *sq; 4316 NvmeCreateSq *c = (NvmeCreateSq *)&req->cmd; 4317 4318 uint16_t cqid = le16_to_cpu(c->cqid); 4319 uint16_t sqid = le16_to_cpu(c->sqid); 4320 uint16_t qsize = le16_to_cpu(c->qsize); 4321 uint16_t qflags = le16_to_cpu(c->sq_flags); 4322 uint64_t prp1 = le64_to_cpu(c->prp1); 4323 4324 trace_pci_nvme_create_sq(prp1, sqid, cqid, qsize, qflags); 4325 4326 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) { 4327 trace_pci_nvme_err_invalid_create_sq_cqid(cqid); 4328 return NVME_INVALID_CQID | NVME_DNR; 4329 } 4330 if (unlikely(!sqid || sqid > n->conf_ioqpairs || n->sq[sqid] != NULL)) { 4331 trace_pci_nvme_err_invalid_create_sq_sqid(sqid); 4332 return NVME_INVALID_QID | NVME_DNR; 4333 } 4334 if (unlikely(!qsize || qsize > NVME_CAP_MQES(ldq_le_p(&n->bar.cap)))) { 4335 trace_pci_nvme_err_invalid_create_sq_size(qsize); 4336 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; 4337 } 4338 if (unlikely(prp1 & (n->page_size - 1))) { 4339 trace_pci_nvme_err_invalid_create_sq_addr(prp1); 4340 return NVME_INVALID_PRP_OFFSET | NVME_DNR; 4341 } 4342 if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) { 4343 trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags)); 4344 return NVME_INVALID_FIELD | NVME_DNR; 4345 } 4346 sq = g_malloc0(sizeof(*sq)); 4347 nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1); 4348 return NVME_SUCCESS; 4349 } 4350 4351 struct nvme_stats { 4352 uint64_t units_read; 4353 uint64_t units_written; 4354 uint64_t read_commands; 4355 uint64_t write_commands; 4356 }; 4357 4358 static void nvme_set_blk_stats(NvmeNamespace *ns, struct nvme_stats *stats) 4359 { 4360 BlockAcctStats *s = blk_get_stats(ns->blkconf.blk); 4361 4362 stats->units_read += s->nr_bytes[BLOCK_ACCT_READ] >> BDRV_SECTOR_BITS; 4363 stats->units_written += s->nr_bytes[BLOCK_ACCT_WRITE] >> BDRV_SECTOR_BITS; 4364 stats->read_commands += s->nr_ops[BLOCK_ACCT_READ]; 4365 stats->write_commands += s->nr_ops[BLOCK_ACCT_WRITE]; 4366 } 4367 4368 static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len, 4369 uint64_t off, NvmeRequest *req) 4370 { 4371 uint32_t nsid = le32_to_cpu(req->cmd.nsid); 4372 struct nvme_stats stats = { 0 }; 4373 NvmeSmartLog smart = { 0 }; 4374 uint32_t trans_len; 4375 NvmeNamespace *ns; 4376 time_t current_ms; 4377 4378 if (off >= sizeof(smart)) { 4379 return NVME_INVALID_FIELD | NVME_DNR; 4380 } 4381 4382 if (nsid != 0xffffffff) { 4383 ns = nvme_ns(n, nsid); 4384 if (!ns) { 4385 return NVME_INVALID_NSID | NVME_DNR; 4386 } 4387 nvme_set_blk_stats(ns, &stats); 4388 } else { 4389 int i; 4390 4391 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 4392 ns = nvme_ns(n, i); 4393 if (!ns) { 4394 continue; 4395 } 4396 nvme_set_blk_stats(ns, &stats); 4397 } 4398 } 4399 4400 trans_len = MIN(sizeof(smart) - off, buf_len); 4401 smart.critical_warning = n->smart_critical_warning; 4402 4403 smart.data_units_read[0] = cpu_to_le64(DIV_ROUND_UP(stats.units_read, 4404 1000)); 4405 smart.data_units_written[0] = cpu_to_le64(DIV_ROUND_UP(stats.units_written, 4406 1000)); 4407 smart.host_read_commands[0] = cpu_to_le64(stats.read_commands); 4408 smart.host_write_commands[0] = cpu_to_le64(stats.write_commands); 4409 4410 smart.temperature = cpu_to_le16(n->temperature); 4411 4412 if ((n->temperature >= n->features.temp_thresh_hi) || 4413 (n->temperature <= n->features.temp_thresh_low)) { 4414 smart.critical_warning |= NVME_SMART_TEMPERATURE; 4415 } 4416 4417 current_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 4418 smart.power_on_hours[0] = 4419 cpu_to_le64((((current_ms - n->starttime_ms) / 1000) / 60) / 60); 4420 4421 if (!rae) { 4422 nvme_clear_events(n, NVME_AER_TYPE_SMART); 4423 } 4424 4425 return nvme_c2h(n, (uint8_t *) &smart + off, trans_len, req); 4426 } 4427 4428 static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off, 4429 NvmeRequest *req) 4430 { 4431 uint32_t trans_len; 4432 NvmeFwSlotInfoLog fw_log = { 4433 .afi = 0x1, 4434 }; 4435 4436 if (off >= sizeof(fw_log)) { 4437 return NVME_INVALID_FIELD | NVME_DNR; 4438 } 4439 4440 strpadcpy((char *)&fw_log.frs1, sizeof(fw_log.frs1), "1.0", ' '); 4441 trans_len = MIN(sizeof(fw_log) - off, buf_len); 4442 4443 return nvme_c2h(n, (uint8_t *) &fw_log + off, trans_len, req); 4444 } 4445 4446 static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len, 4447 uint64_t off, NvmeRequest *req) 4448 { 4449 uint32_t trans_len; 4450 NvmeErrorLog errlog; 4451 4452 if (off >= sizeof(errlog)) { 4453 return NVME_INVALID_FIELD | NVME_DNR; 4454 } 4455 4456 if (!rae) { 4457 nvme_clear_events(n, NVME_AER_TYPE_ERROR); 4458 } 4459 4460 memset(&errlog, 0x0, sizeof(errlog)); 4461 trans_len = MIN(sizeof(errlog) - off, buf_len); 4462 4463 return nvme_c2h(n, (uint8_t *)&errlog, trans_len, req); 4464 } 4465 4466 static uint16_t nvme_changed_nslist(NvmeCtrl *n, uint8_t rae, uint32_t buf_len, 4467 uint64_t off, NvmeRequest *req) 4468 { 4469 uint32_t nslist[1024]; 4470 uint32_t trans_len; 4471 int i = 0; 4472 uint32_t nsid; 4473 4474 if (off >= sizeof(nslist)) { 4475 trace_pci_nvme_err_invalid_log_page_offset(off, sizeof(nslist)); 4476 return NVME_INVALID_FIELD | NVME_DNR; 4477 } 4478 4479 memset(nslist, 0x0, sizeof(nslist)); 4480 trans_len = MIN(sizeof(nslist) - off, buf_len); 4481 4482 while ((nsid = find_first_bit(n->changed_nsids, NVME_CHANGED_NSID_SIZE)) != 4483 NVME_CHANGED_NSID_SIZE) { 4484 /* 4485 * If more than 1024 namespaces, the first entry in the log page should 4486 * be set to FFFFFFFFh and the others to 0 as spec. 4487 */ 4488 if (i == ARRAY_SIZE(nslist)) { 4489 memset(nslist, 0x0, sizeof(nslist)); 4490 nslist[0] = 0xffffffff; 4491 break; 4492 } 4493 4494 nslist[i++] = nsid; 4495 clear_bit(nsid, n->changed_nsids); 4496 } 4497 4498 /* 4499 * Remove all the remaining list entries in case returns directly due to 4500 * more than 1024 namespaces. 4501 */ 4502 if (nslist[0] == 0xffffffff) { 4503 bitmap_zero(n->changed_nsids, NVME_CHANGED_NSID_SIZE); 4504 } 4505 4506 if (!rae) { 4507 nvme_clear_events(n, NVME_AER_TYPE_NOTICE); 4508 } 4509 4510 return nvme_c2h(n, ((uint8_t *)nslist) + off, trans_len, req); 4511 } 4512 4513 static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint8_t csi, uint32_t buf_len, 4514 uint64_t off, NvmeRequest *req) 4515 { 4516 NvmeEffectsLog log = {}; 4517 const uint32_t *src_iocs = NULL; 4518 uint32_t trans_len; 4519 4520 if (off >= sizeof(log)) { 4521 trace_pci_nvme_err_invalid_log_page_offset(off, sizeof(log)); 4522 return NVME_INVALID_FIELD | NVME_DNR; 4523 } 4524 4525 switch (NVME_CC_CSS(ldl_le_p(&n->bar.cc))) { 4526 case NVME_CC_CSS_NVM: 4527 src_iocs = nvme_cse_iocs_nvm; 4528 /* fall through */ 4529 case NVME_CC_CSS_ADMIN_ONLY: 4530 break; 4531 case NVME_CC_CSS_CSI: 4532 switch (csi) { 4533 case NVME_CSI_NVM: 4534 src_iocs = nvme_cse_iocs_nvm; 4535 break; 4536 case NVME_CSI_ZONED: 4537 src_iocs = nvme_cse_iocs_zoned; 4538 break; 4539 } 4540 } 4541 4542 memcpy(log.acs, nvme_cse_acs, sizeof(nvme_cse_acs)); 4543 4544 if (src_iocs) { 4545 memcpy(log.iocs, src_iocs, sizeof(log.iocs)); 4546 } 4547 4548 trans_len = MIN(sizeof(log) - off, buf_len); 4549 4550 return nvme_c2h(n, ((uint8_t *)&log) + off, trans_len, req); 4551 } 4552 4553 static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req) 4554 { 4555 NvmeCmd *cmd = &req->cmd; 4556 4557 uint32_t dw10 = le32_to_cpu(cmd->cdw10); 4558 uint32_t dw11 = le32_to_cpu(cmd->cdw11); 4559 uint32_t dw12 = le32_to_cpu(cmd->cdw12); 4560 uint32_t dw13 = le32_to_cpu(cmd->cdw13); 4561 uint8_t lid = dw10 & 0xff; 4562 uint8_t lsp = (dw10 >> 8) & 0xf; 4563 uint8_t rae = (dw10 >> 15) & 0x1; 4564 uint8_t csi = le32_to_cpu(cmd->cdw14) >> 24; 4565 uint32_t numdl, numdu; 4566 uint64_t off, lpol, lpou; 4567 size_t len; 4568 uint16_t status; 4569 4570 numdl = (dw10 >> 16); 4571 numdu = (dw11 & 0xffff); 4572 lpol = dw12; 4573 lpou = dw13; 4574 4575 len = (((numdu << 16) | numdl) + 1) << 2; 4576 off = (lpou << 32ULL) | lpol; 4577 4578 if (off & 0x3) { 4579 return NVME_INVALID_FIELD | NVME_DNR; 4580 } 4581 4582 trace_pci_nvme_get_log(nvme_cid(req), lid, lsp, rae, len, off); 4583 4584 status = nvme_check_mdts(n, len); 4585 if (status) { 4586 return status; 4587 } 4588 4589 switch (lid) { 4590 case NVME_LOG_ERROR_INFO: 4591 return nvme_error_info(n, rae, len, off, req); 4592 case NVME_LOG_SMART_INFO: 4593 return nvme_smart_info(n, rae, len, off, req); 4594 case NVME_LOG_FW_SLOT_INFO: 4595 return nvme_fw_log_info(n, len, off, req); 4596 case NVME_LOG_CHANGED_NSLIST: 4597 return nvme_changed_nslist(n, rae, len, off, req); 4598 case NVME_LOG_CMD_EFFECTS: 4599 return nvme_cmd_effects(n, csi, len, off, req); 4600 default: 4601 trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid); 4602 return NVME_INVALID_FIELD | NVME_DNR; 4603 } 4604 } 4605 4606 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n) 4607 { 4608 n->cq[cq->cqid] = NULL; 4609 timer_free(cq->timer); 4610 if (msix_enabled(&n->parent_obj)) { 4611 msix_vector_unuse(&n->parent_obj, cq->vector); 4612 } 4613 if (cq->cqid) { 4614 g_free(cq); 4615 } 4616 } 4617 4618 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeRequest *req) 4619 { 4620 NvmeDeleteQ *c = (NvmeDeleteQ *)&req->cmd; 4621 NvmeCQueue *cq; 4622 uint16_t qid = le16_to_cpu(c->qid); 4623 4624 if (unlikely(!qid || nvme_check_cqid(n, qid))) { 4625 trace_pci_nvme_err_invalid_del_cq_cqid(qid); 4626 return NVME_INVALID_CQID | NVME_DNR; 4627 } 4628 4629 cq = n->cq[qid]; 4630 if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) { 4631 trace_pci_nvme_err_invalid_del_cq_notempty(qid); 4632 return NVME_INVALID_QUEUE_DEL; 4633 } 4634 4635 if (cq->irq_enabled && cq->tail != cq->head) { 4636 n->cq_pending--; 4637 } 4638 4639 nvme_irq_deassert(n, cq); 4640 trace_pci_nvme_del_cq(qid); 4641 nvme_free_cq(cq, n); 4642 return NVME_SUCCESS; 4643 } 4644 4645 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr, 4646 uint16_t cqid, uint16_t vector, uint16_t size, 4647 uint16_t irq_enabled) 4648 { 4649 int ret; 4650 4651 if (msix_enabled(&n->parent_obj)) { 4652 ret = msix_vector_use(&n->parent_obj, vector); 4653 assert(ret == 0); 4654 } 4655 cq->ctrl = n; 4656 cq->cqid = cqid; 4657 cq->size = size; 4658 cq->dma_addr = dma_addr; 4659 cq->phase = 1; 4660 cq->irq_enabled = irq_enabled; 4661 cq->vector = vector; 4662 cq->head = cq->tail = 0; 4663 QTAILQ_INIT(&cq->req_list); 4664 QTAILQ_INIT(&cq->sq_list); 4665 if (n->dbbuf_enabled) { 4666 cq->db_addr = n->dbbuf_dbs + (cqid << 3) + (1 << 2); 4667 cq->ei_addr = n->dbbuf_eis + (cqid << 3) + (1 << 2); 4668 } 4669 n->cq[cqid] = cq; 4670 cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq); 4671 } 4672 4673 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req) 4674 { 4675 NvmeCQueue *cq; 4676 NvmeCreateCq *c = (NvmeCreateCq *)&req->cmd; 4677 uint16_t cqid = le16_to_cpu(c->cqid); 4678 uint16_t vector = le16_to_cpu(c->irq_vector); 4679 uint16_t qsize = le16_to_cpu(c->qsize); 4680 uint16_t qflags = le16_to_cpu(c->cq_flags); 4681 uint64_t prp1 = le64_to_cpu(c->prp1); 4682 4683 trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags, 4684 NVME_CQ_FLAGS_IEN(qflags) != 0); 4685 4686 if (unlikely(!cqid || cqid > n->conf_ioqpairs || n->cq[cqid] != NULL)) { 4687 trace_pci_nvme_err_invalid_create_cq_cqid(cqid); 4688 return NVME_INVALID_QID | NVME_DNR; 4689 } 4690 if (unlikely(!qsize || qsize > NVME_CAP_MQES(ldq_le_p(&n->bar.cap)))) { 4691 trace_pci_nvme_err_invalid_create_cq_size(qsize); 4692 return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; 4693 } 4694 if (unlikely(prp1 & (n->page_size - 1))) { 4695 trace_pci_nvme_err_invalid_create_cq_addr(prp1); 4696 return NVME_INVALID_PRP_OFFSET | NVME_DNR; 4697 } 4698 if (unlikely(!msix_enabled(&n->parent_obj) && vector)) { 4699 trace_pci_nvme_err_invalid_create_cq_vector(vector); 4700 return NVME_INVALID_IRQ_VECTOR | NVME_DNR; 4701 } 4702 if (unlikely(vector >= n->conf_msix_qsize)) { 4703 trace_pci_nvme_err_invalid_create_cq_vector(vector); 4704 return NVME_INVALID_IRQ_VECTOR | NVME_DNR; 4705 } 4706 if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) { 4707 trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags)); 4708 return NVME_INVALID_FIELD | NVME_DNR; 4709 } 4710 4711 cq = g_malloc0(sizeof(*cq)); 4712 nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1, 4713 NVME_CQ_FLAGS_IEN(qflags)); 4714 4715 /* 4716 * It is only required to set qs_created when creating a completion queue; 4717 * creating a submission queue without a matching completion queue will 4718 * fail. 4719 */ 4720 n->qs_created = true; 4721 return NVME_SUCCESS; 4722 } 4723 4724 static uint16_t nvme_rpt_empty_id_struct(NvmeCtrl *n, NvmeRequest *req) 4725 { 4726 uint8_t id[NVME_IDENTIFY_DATA_SIZE] = {}; 4727 4728 return nvme_c2h(n, id, sizeof(id), req); 4729 } 4730 4731 static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req) 4732 { 4733 trace_pci_nvme_identify_ctrl(); 4734 4735 return nvme_c2h(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), req); 4736 } 4737 4738 static uint16_t nvme_identify_ctrl_csi(NvmeCtrl *n, NvmeRequest *req) 4739 { 4740 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 4741 uint8_t id[NVME_IDENTIFY_DATA_SIZE] = {}; 4742 NvmeIdCtrlNvm *id_nvm = (NvmeIdCtrlNvm *)&id; 4743 4744 trace_pci_nvme_identify_ctrl_csi(c->csi); 4745 4746 switch (c->csi) { 4747 case NVME_CSI_NVM: 4748 id_nvm->vsl = n->params.vsl; 4749 id_nvm->dmrsl = cpu_to_le32(n->dmrsl); 4750 break; 4751 4752 case NVME_CSI_ZONED: 4753 ((NvmeIdCtrlZoned *)&id)->zasl = n->params.zasl; 4754 break; 4755 4756 default: 4757 return NVME_INVALID_FIELD | NVME_DNR; 4758 } 4759 4760 return nvme_c2h(n, id, sizeof(id), req); 4761 } 4762 4763 static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req, bool active) 4764 { 4765 NvmeNamespace *ns; 4766 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 4767 uint32_t nsid = le32_to_cpu(c->nsid); 4768 4769 trace_pci_nvme_identify_ns(nsid); 4770 4771 if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) { 4772 return NVME_INVALID_NSID | NVME_DNR; 4773 } 4774 4775 ns = nvme_ns(n, nsid); 4776 if (unlikely(!ns)) { 4777 if (!active) { 4778 ns = nvme_subsys_ns(n->subsys, nsid); 4779 if (!ns) { 4780 return nvme_rpt_empty_id_struct(n, req); 4781 } 4782 } else { 4783 return nvme_rpt_empty_id_struct(n, req); 4784 } 4785 } 4786 4787 if (active || ns->csi == NVME_CSI_NVM) { 4788 return nvme_c2h(n, (uint8_t *)&ns->id_ns, sizeof(NvmeIdNs), req); 4789 } 4790 4791 return NVME_INVALID_CMD_SET | NVME_DNR; 4792 } 4793 4794 static uint16_t nvme_identify_ctrl_list(NvmeCtrl *n, NvmeRequest *req, 4795 bool attached) 4796 { 4797 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 4798 uint32_t nsid = le32_to_cpu(c->nsid); 4799 uint16_t min_id = le16_to_cpu(c->ctrlid); 4800 uint16_t list[NVME_CONTROLLER_LIST_SIZE] = {}; 4801 uint16_t *ids = &list[1]; 4802 NvmeNamespace *ns; 4803 NvmeCtrl *ctrl; 4804 int cntlid, nr_ids = 0; 4805 4806 trace_pci_nvme_identify_ctrl_list(c->cns, min_id); 4807 4808 if (!n->subsys) { 4809 return NVME_INVALID_FIELD | NVME_DNR; 4810 } 4811 4812 if (attached) { 4813 if (nsid == NVME_NSID_BROADCAST) { 4814 return NVME_INVALID_FIELD | NVME_DNR; 4815 } 4816 4817 ns = nvme_subsys_ns(n->subsys, nsid); 4818 if (!ns) { 4819 return NVME_INVALID_FIELD | NVME_DNR; 4820 } 4821 } 4822 4823 for (cntlid = min_id; cntlid < ARRAY_SIZE(n->subsys->ctrls); cntlid++) { 4824 ctrl = nvme_subsys_ctrl(n->subsys, cntlid); 4825 if (!ctrl) { 4826 continue; 4827 } 4828 4829 if (attached && !nvme_ns(ctrl, nsid)) { 4830 continue; 4831 } 4832 4833 ids[nr_ids++] = cntlid; 4834 } 4835 4836 list[0] = nr_ids; 4837 4838 return nvme_c2h(n, (uint8_t *)list, sizeof(list), req); 4839 } 4840 4841 static uint16_t nvme_identify_pri_ctrl_cap(NvmeCtrl *n, NvmeRequest *req) 4842 { 4843 trace_pci_nvme_identify_pri_ctrl_cap(le16_to_cpu(n->pri_ctrl_cap.cntlid)); 4844 4845 return nvme_c2h(n, (uint8_t *)&n->pri_ctrl_cap, 4846 sizeof(NvmePriCtrlCap), req); 4847 } 4848 4849 static uint16_t nvme_identify_sec_ctrl_list(NvmeCtrl *n, NvmeRequest *req) 4850 { 4851 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 4852 uint16_t pri_ctrl_id = le16_to_cpu(n->pri_ctrl_cap.cntlid); 4853 uint16_t min_id = le16_to_cpu(c->ctrlid); 4854 uint8_t num_sec_ctrl = n->sec_ctrl_list.numcntl; 4855 NvmeSecCtrlList list = {0}; 4856 uint8_t i; 4857 4858 for (i = 0; i < num_sec_ctrl; i++) { 4859 if (n->sec_ctrl_list.sec[i].scid >= min_id) { 4860 list.numcntl = num_sec_ctrl - i; 4861 memcpy(&list.sec, n->sec_ctrl_list.sec + i, 4862 list.numcntl * sizeof(NvmeSecCtrlEntry)); 4863 break; 4864 } 4865 } 4866 4867 trace_pci_nvme_identify_sec_ctrl_list(pri_ctrl_id, list.numcntl); 4868 4869 return nvme_c2h(n, (uint8_t *)&list, sizeof(list), req); 4870 } 4871 4872 static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req, 4873 bool active) 4874 { 4875 NvmeNamespace *ns; 4876 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 4877 uint32_t nsid = le32_to_cpu(c->nsid); 4878 4879 trace_pci_nvme_identify_ns_csi(nsid, c->csi); 4880 4881 if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) { 4882 return NVME_INVALID_NSID | NVME_DNR; 4883 } 4884 4885 ns = nvme_ns(n, nsid); 4886 if (unlikely(!ns)) { 4887 if (!active) { 4888 ns = nvme_subsys_ns(n->subsys, nsid); 4889 if (!ns) { 4890 return nvme_rpt_empty_id_struct(n, req); 4891 } 4892 } else { 4893 return nvme_rpt_empty_id_struct(n, req); 4894 } 4895 } 4896 4897 if (c->csi == NVME_CSI_NVM) { 4898 return nvme_c2h(n, (uint8_t *)&ns->id_ns_nvm, sizeof(NvmeIdNsNvm), 4899 req); 4900 } else if (c->csi == NVME_CSI_ZONED && ns->csi == NVME_CSI_ZONED) { 4901 return nvme_c2h(n, (uint8_t *)ns->id_ns_zoned, sizeof(NvmeIdNsZoned), 4902 req); 4903 } 4904 4905 return NVME_INVALID_FIELD | NVME_DNR; 4906 } 4907 4908 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req, 4909 bool active) 4910 { 4911 NvmeNamespace *ns; 4912 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 4913 uint32_t min_nsid = le32_to_cpu(c->nsid); 4914 uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {}; 4915 static const int data_len = sizeof(list); 4916 uint32_t *list_ptr = (uint32_t *)list; 4917 int i, j = 0; 4918 4919 trace_pci_nvme_identify_nslist(min_nsid); 4920 4921 /* 4922 * Both FFFFFFFFh (NVME_NSID_BROADCAST) and FFFFFFFFEh are invalid values 4923 * since the Active Namespace ID List should return namespaces with ids 4924 * *higher* than the NSID specified in the command. This is also specified 4925 * in the spec (NVM Express v1.3d, Section 5.15.4). 4926 */ 4927 if (min_nsid >= NVME_NSID_BROADCAST - 1) { 4928 return NVME_INVALID_NSID | NVME_DNR; 4929 } 4930 4931 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 4932 ns = nvme_ns(n, i); 4933 if (!ns) { 4934 if (!active) { 4935 ns = nvme_subsys_ns(n->subsys, i); 4936 if (!ns) { 4937 continue; 4938 } 4939 } else { 4940 continue; 4941 } 4942 } 4943 if (ns->params.nsid <= min_nsid) { 4944 continue; 4945 } 4946 list_ptr[j++] = cpu_to_le32(ns->params.nsid); 4947 if (j == data_len / sizeof(uint32_t)) { 4948 break; 4949 } 4950 } 4951 4952 return nvme_c2h(n, list, data_len, req); 4953 } 4954 4955 static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n, NvmeRequest *req, 4956 bool active) 4957 { 4958 NvmeNamespace *ns; 4959 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 4960 uint32_t min_nsid = le32_to_cpu(c->nsid); 4961 uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {}; 4962 static const int data_len = sizeof(list); 4963 uint32_t *list_ptr = (uint32_t *)list; 4964 int i, j = 0; 4965 4966 trace_pci_nvme_identify_nslist_csi(min_nsid, c->csi); 4967 4968 /* 4969 * Same as in nvme_identify_nslist(), FFFFFFFFh/FFFFFFFFEh are invalid. 4970 */ 4971 if (min_nsid >= NVME_NSID_BROADCAST - 1) { 4972 return NVME_INVALID_NSID | NVME_DNR; 4973 } 4974 4975 if (c->csi != NVME_CSI_NVM && c->csi != NVME_CSI_ZONED) { 4976 return NVME_INVALID_FIELD | NVME_DNR; 4977 } 4978 4979 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 4980 ns = nvme_ns(n, i); 4981 if (!ns) { 4982 if (!active) { 4983 ns = nvme_subsys_ns(n->subsys, i); 4984 if (!ns) { 4985 continue; 4986 } 4987 } else { 4988 continue; 4989 } 4990 } 4991 if (ns->params.nsid <= min_nsid || c->csi != ns->csi) { 4992 continue; 4993 } 4994 list_ptr[j++] = cpu_to_le32(ns->params.nsid); 4995 if (j == data_len / sizeof(uint32_t)) { 4996 break; 4997 } 4998 } 4999 5000 return nvme_c2h(n, list, data_len, req); 5001 } 5002 5003 static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req) 5004 { 5005 NvmeNamespace *ns; 5006 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 5007 uint32_t nsid = le32_to_cpu(c->nsid); 5008 uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {}; 5009 uint8_t *pos = list; 5010 struct { 5011 NvmeIdNsDescr hdr; 5012 uint8_t v[NVME_NIDL_UUID]; 5013 } QEMU_PACKED uuid = {}; 5014 struct { 5015 NvmeIdNsDescr hdr; 5016 uint64_t v; 5017 } QEMU_PACKED eui64 = {}; 5018 struct { 5019 NvmeIdNsDescr hdr; 5020 uint8_t v; 5021 } QEMU_PACKED csi = {}; 5022 5023 trace_pci_nvme_identify_ns_descr_list(nsid); 5024 5025 if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) { 5026 return NVME_INVALID_NSID | NVME_DNR; 5027 } 5028 5029 ns = nvme_ns(n, nsid); 5030 if (unlikely(!ns)) { 5031 return NVME_INVALID_FIELD | NVME_DNR; 5032 } 5033 5034 if (!qemu_uuid_is_null(&ns->params.uuid)) { 5035 uuid.hdr.nidt = NVME_NIDT_UUID; 5036 uuid.hdr.nidl = NVME_NIDL_UUID; 5037 memcpy(uuid.v, ns->params.uuid.data, NVME_NIDL_UUID); 5038 memcpy(pos, &uuid, sizeof(uuid)); 5039 pos += sizeof(uuid); 5040 } 5041 5042 if (ns->params.eui64) { 5043 eui64.hdr.nidt = NVME_NIDT_EUI64; 5044 eui64.hdr.nidl = NVME_NIDL_EUI64; 5045 eui64.v = cpu_to_be64(ns->params.eui64); 5046 memcpy(pos, &eui64, sizeof(eui64)); 5047 pos += sizeof(eui64); 5048 } 5049 5050 csi.hdr.nidt = NVME_NIDT_CSI; 5051 csi.hdr.nidl = NVME_NIDL_CSI; 5052 csi.v = ns->csi; 5053 memcpy(pos, &csi, sizeof(csi)); 5054 pos += sizeof(csi); 5055 5056 return nvme_c2h(n, list, sizeof(list), req); 5057 } 5058 5059 static uint16_t nvme_identify_cmd_set(NvmeCtrl *n, NvmeRequest *req) 5060 { 5061 uint8_t list[NVME_IDENTIFY_DATA_SIZE] = {}; 5062 static const int data_len = sizeof(list); 5063 5064 trace_pci_nvme_identify_cmd_set(); 5065 5066 NVME_SET_CSI(*list, NVME_CSI_NVM); 5067 NVME_SET_CSI(*list, NVME_CSI_ZONED); 5068 5069 return nvme_c2h(n, list, data_len, req); 5070 } 5071 5072 static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req) 5073 { 5074 NvmeIdentify *c = (NvmeIdentify *)&req->cmd; 5075 5076 trace_pci_nvme_identify(nvme_cid(req), c->cns, le16_to_cpu(c->ctrlid), 5077 c->csi); 5078 5079 switch (c->cns) { 5080 case NVME_ID_CNS_NS: 5081 return nvme_identify_ns(n, req, true); 5082 case NVME_ID_CNS_NS_PRESENT: 5083 return nvme_identify_ns(n, req, false); 5084 case NVME_ID_CNS_NS_ATTACHED_CTRL_LIST: 5085 return nvme_identify_ctrl_list(n, req, true); 5086 case NVME_ID_CNS_CTRL_LIST: 5087 return nvme_identify_ctrl_list(n, req, false); 5088 case NVME_ID_CNS_PRIMARY_CTRL_CAP: 5089 return nvme_identify_pri_ctrl_cap(n, req); 5090 case NVME_ID_CNS_SECONDARY_CTRL_LIST: 5091 return nvme_identify_sec_ctrl_list(n, req); 5092 case NVME_ID_CNS_CS_NS: 5093 return nvme_identify_ns_csi(n, req, true); 5094 case NVME_ID_CNS_CS_NS_PRESENT: 5095 return nvme_identify_ns_csi(n, req, false); 5096 case NVME_ID_CNS_CTRL: 5097 return nvme_identify_ctrl(n, req); 5098 case NVME_ID_CNS_CS_CTRL: 5099 return nvme_identify_ctrl_csi(n, req); 5100 case NVME_ID_CNS_NS_ACTIVE_LIST: 5101 return nvme_identify_nslist(n, req, true); 5102 case NVME_ID_CNS_NS_PRESENT_LIST: 5103 return nvme_identify_nslist(n, req, false); 5104 case NVME_ID_CNS_CS_NS_ACTIVE_LIST: 5105 return nvme_identify_nslist_csi(n, req, true); 5106 case NVME_ID_CNS_CS_NS_PRESENT_LIST: 5107 return nvme_identify_nslist_csi(n, req, false); 5108 case NVME_ID_CNS_NS_DESCR_LIST: 5109 return nvme_identify_ns_descr_list(n, req); 5110 case NVME_ID_CNS_IO_COMMAND_SET: 5111 return nvme_identify_cmd_set(n, req); 5112 default: 5113 trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); 5114 return NVME_INVALID_FIELD | NVME_DNR; 5115 } 5116 } 5117 5118 static uint16_t nvme_abort(NvmeCtrl *n, NvmeRequest *req) 5119 { 5120 uint16_t sqid = le32_to_cpu(req->cmd.cdw10) & 0xffff; 5121 5122 req->cqe.result = 1; 5123 if (nvme_check_sqid(n, sqid)) { 5124 return NVME_INVALID_FIELD | NVME_DNR; 5125 } 5126 5127 return NVME_SUCCESS; 5128 } 5129 5130 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts) 5131 { 5132 trace_pci_nvme_setfeat_timestamp(ts); 5133 5134 n->host_timestamp = le64_to_cpu(ts); 5135 n->timestamp_set_qemu_clock_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 5136 } 5137 5138 static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n) 5139 { 5140 uint64_t current_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 5141 uint64_t elapsed_time = current_time - n->timestamp_set_qemu_clock_ms; 5142 5143 union nvme_timestamp { 5144 struct { 5145 uint64_t timestamp:48; 5146 uint64_t sync:1; 5147 uint64_t origin:3; 5148 uint64_t rsvd1:12; 5149 }; 5150 uint64_t all; 5151 }; 5152 5153 union nvme_timestamp ts; 5154 ts.all = 0; 5155 ts.timestamp = n->host_timestamp + elapsed_time; 5156 5157 /* If the host timestamp is non-zero, set the timestamp origin */ 5158 ts.origin = n->host_timestamp ? 0x01 : 0x00; 5159 5160 trace_pci_nvme_getfeat_timestamp(ts.all); 5161 5162 return cpu_to_le64(ts.all); 5163 } 5164 5165 static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeRequest *req) 5166 { 5167 uint64_t timestamp = nvme_get_timestamp(n); 5168 5169 return nvme_c2h(n, (uint8_t *)×tamp, sizeof(timestamp), req); 5170 } 5171 5172 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req) 5173 { 5174 NvmeCmd *cmd = &req->cmd; 5175 uint32_t dw10 = le32_to_cpu(cmd->cdw10); 5176 uint32_t dw11 = le32_to_cpu(cmd->cdw11); 5177 uint32_t nsid = le32_to_cpu(cmd->nsid); 5178 uint32_t result; 5179 uint8_t fid = NVME_GETSETFEAT_FID(dw10); 5180 NvmeGetFeatureSelect sel = NVME_GETFEAT_SELECT(dw10); 5181 uint16_t iv; 5182 NvmeNamespace *ns; 5183 int i; 5184 5185 static const uint32_t nvme_feature_default[NVME_FID_MAX] = { 5186 [NVME_ARBITRATION] = NVME_ARB_AB_NOLIMIT, 5187 }; 5188 5189 trace_pci_nvme_getfeat(nvme_cid(req), nsid, fid, sel, dw11); 5190 5191 if (!nvme_feature_support[fid]) { 5192 return NVME_INVALID_FIELD | NVME_DNR; 5193 } 5194 5195 if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) { 5196 if (!nvme_nsid_valid(n, nsid) || nsid == NVME_NSID_BROADCAST) { 5197 /* 5198 * The Reservation Notification Mask and Reservation Persistence 5199 * features require a status code of Invalid Field in Command when 5200 * NSID is FFFFFFFFh. Since the device does not support those 5201 * features we can always return Invalid Namespace or Format as we 5202 * should do for all other features. 5203 */ 5204 return NVME_INVALID_NSID | NVME_DNR; 5205 } 5206 5207 if (!nvme_ns(n, nsid)) { 5208 return NVME_INVALID_FIELD | NVME_DNR; 5209 } 5210 } 5211 5212 switch (sel) { 5213 case NVME_GETFEAT_SELECT_CURRENT: 5214 break; 5215 case NVME_GETFEAT_SELECT_SAVED: 5216 /* no features are saveable by the controller; fallthrough */ 5217 case NVME_GETFEAT_SELECT_DEFAULT: 5218 goto defaults; 5219 case NVME_GETFEAT_SELECT_CAP: 5220 result = nvme_feature_cap[fid]; 5221 goto out; 5222 } 5223 5224 switch (fid) { 5225 case NVME_TEMPERATURE_THRESHOLD: 5226 result = 0; 5227 5228 /* 5229 * The controller only implements the Composite Temperature sensor, so 5230 * return 0 for all other sensors. 5231 */ 5232 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) { 5233 goto out; 5234 } 5235 5236 switch (NVME_TEMP_THSEL(dw11)) { 5237 case NVME_TEMP_THSEL_OVER: 5238 result = n->features.temp_thresh_hi; 5239 goto out; 5240 case NVME_TEMP_THSEL_UNDER: 5241 result = n->features.temp_thresh_low; 5242 goto out; 5243 } 5244 5245 return NVME_INVALID_FIELD | NVME_DNR; 5246 case NVME_ERROR_RECOVERY: 5247 if (!nvme_nsid_valid(n, nsid)) { 5248 return NVME_INVALID_NSID | NVME_DNR; 5249 } 5250 5251 ns = nvme_ns(n, nsid); 5252 if (unlikely(!ns)) { 5253 return NVME_INVALID_FIELD | NVME_DNR; 5254 } 5255 5256 result = ns->features.err_rec; 5257 goto out; 5258 case NVME_VOLATILE_WRITE_CACHE: 5259 result = 0; 5260 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 5261 ns = nvme_ns(n, i); 5262 if (!ns) { 5263 continue; 5264 } 5265 5266 result = blk_enable_write_cache(ns->blkconf.blk); 5267 if (result) { 5268 break; 5269 } 5270 } 5271 trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); 5272 goto out; 5273 case NVME_ASYNCHRONOUS_EVENT_CONF: 5274 result = n->features.async_config; 5275 goto out; 5276 case NVME_TIMESTAMP: 5277 return nvme_get_feature_timestamp(n, req); 5278 case NVME_HOST_BEHAVIOR_SUPPORT: 5279 return nvme_c2h(n, (uint8_t *)&n->features.hbs, 5280 sizeof(n->features.hbs), req); 5281 default: 5282 break; 5283 } 5284 5285 defaults: 5286 switch (fid) { 5287 case NVME_TEMPERATURE_THRESHOLD: 5288 result = 0; 5289 5290 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) { 5291 break; 5292 } 5293 5294 if (NVME_TEMP_THSEL(dw11) == NVME_TEMP_THSEL_OVER) { 5295 result = NVME_TEMPERATURE_WARNING; 5296 } 5297 5298 break; 5299 case NVME_NUMBER_OF_QUEUES: 5300 result = (n->conf_ioqpairs - 1) | ((n->conf_ioqpairs - 1) << 16); 5301 trace_pci_nvme_getfeat_numq(result); 5302 break; 5303 case NVME_INTERRUPT_VECTOR_CONF: 5304 iv = dw11 & 0xffff; 5305 if (iv >= n->conf_ioqpairs + 1) { 5306 return NVME_INVALID_FIELD | NVME_DNR; 5307 } 5308 5309 result = iv; 5310 if (iv == n->admin_cq.vector) { 5311 result |= NVME_INTVC_NOCOALESCING; 5312 } 5313 break; 5314 default: 5315 result = nvme_feature_default[fid]; 5316 break; 5317 } 5318 5319 out: 5320 req->cqe.result = cpu_to_le32(result); 5321 return NVME_SUCCESS; 5322 } 5323 5324 static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeRequest *req) 5325 { 5326 uint16_t ret; 5327 uint64_t timestamp; 5328 5329 ret = nvme_h2c(n, (uint8_t *)×tamp, sizeof(timestamp), req); 5330 if (ret) { 5331 return ret; 5332 } 5333 5334 nvme_set_timestamp(n, timestamp); 5335 5336 return NVME_SUCCESS; 5337 } 5338 5339 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req) 5340 { 5341 NvmeNamespace *ns = NULL; 5342 5343 NvmeCmd *cmd = &req->cmd; 5344 uint32_t dw10 = le32_to_cpu(cmd->cdw10); 5345 uint32_t dw11 = le32_to_cpu(cmd->cdw11); 5346 uint32_t nsid = le32_to_cpu(cmd->nsid); 5347 uint8_t fid = NVME_GETSETFEAT_FID(dw10); 5348 uint8_t save = NVME_SETFEAT_SAVE(dw10); 5349 uint16_t status; 5350 int i; 5351 5352 trace_pci_nvme_setfeat(nvme_cid(req), nsid, fid, save, dw11); 5353 5354 if (save && !(nvme_feature_cap[fid] & NVME_FEAT_CAP_SAVE)) { 5355 return NVME_FID_NOT_SAVEABLE | NVME_DNR; 5356 } 5357 5358 if (!nvme_feature_support[fid]) { 5359 return NVME_INVALID_FIELD | NVME_DNR; 5360 } 5361 5362 if (nvme_feature_cap[fid] & NVME_FEAT_CAP_NS) { 5363 if (nsid != NVME_NSID_BROADCAST) { 5364 if (!nvme_nsid_valid(n, nsid)) { 5365 return NVME_INVALID_NSID | NVME_DNR; 5366 } 5367 5368 ns = nvme_ns(n, nsid); 5369 if (unlikely(!ns)) { 5370 return NVME_INVALID_FIELD | NVME_DNR; 5371 } 5372 } 5373 } else if (nsid && nsid != NVME_NSID_BROADCAST) { 5374 if (!nvme_nsid_valid(n, nsid)) { 5375 return NVME_INVALID_NSID | NVME_DNR; 5376 } 5377 5378 return NVME_FEAT_NOT_NS_SPEC | NVME_DNR; 5379 } 5380 5381 if (!(nvme_feature_cap[fid] & NVME_FEAT_CAP_CHANGE)) { 5382 return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR; 5383 } 5384 5385 switch (fid) { 5386 case NVME_TEMPERATURE_THRESHOLD: 5387 if (NVME_TEMP_TMPSEL(dw11) != NVME_TEMP_TMPSEL_COMPOSITE) { 5388 break; 5389 } 5390 5391 switch (NVME_TEMP_THSEL(dw11)) { 5392 case NVME_TEMP_THSEL_OVER: 5393 n->features.temp_thresh_hi = NVME_TEMP_TMPTH(dw11); 5394 break; 5395 case NVME_TEMP_THSEL_UNDER: 5396 n->features.temp_thresh_low = NVME_TEMP_TMPTH(dw11); 5397 break; 5398 default: 5399 return NVME_INVALID_FIELD | NVME_DNR; 5400 } 5401 5402 if ((n->temperature >= n->features.temp_thresh_hi) || 5403 (n->temperature <= n->features.temp_thresh_low)) { 5404 nvme_smart_event(n, NVME_SMART_TEMPERATURE); 5405 } 5406 5407 break; 5408 case NVME_ERROR_RECOVERY: 5409 if (nsid == NVME_NSID_BROADCAST) { 5410 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 5411 ns = nvme_ns(n, i); 5412 5413 if (!ns) { 5414 continue; 5415 } 5416 5417 if (NVME_ID_NS_NSFEAT_DULBE(ns->id_ns.nsfeat)) { 5418 ns->features.err_rec = dw11; 5419 } 5420 } 5421 5422 break; 5423 } 5424 5425 assert(ns); 5426 if (NVME_ID_NS_NSFEAT_DULBE(ns->id_ns.nsfeat)) { 5427 ns->features.err_rec = dw11; 5428 } 5429 break; 5430 case NVME_VOLATILE_WRITE_CACHE: 5431 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 5432 ns = nvme_ns(n, i); 5433 if (!ns) { 5434 continue; 5435 } 5436 5437 if (!(dw11 & 0x1) && blk_enable_write_cache(ns->blkconf.blk)) { 5438 blk_flush(ns->blkconf.blk); 5439 } 5440 5441 blk_set_enable_write_cache(ns->blkconf.blk, dw11 & 1); 5442 } 5443 5444 break; 5445 5446 case NVME_NUMBER_OF_QUEUES: 5447 if (n->qs_created) { 5448 return NVME_CMD_SEQ_ERROR | NVME_DNR; 5449 } 5450 5451 /* 5452 * NVMe v1.3, Section 5.21.1.7: FFFFh is not an allowed value for NCQR 5453 * and NSQR. 5454 */ 5455 if ((dw11 & 0xffff) == 0xffff || ((dw11 >> 16) & 0xffff) == 0xffff) { 5456 return NVME_INVALID_FIELD | NVME_DNR; 5457 } 5458 5459 trace_pci_nvme_setfeat_numq((dw11 & 0xffff) + 1, 5460 ((dw11 >> 16) & 0xffff) + 1, 5461 n->conf_ioqpairs, 5462 n->conf_ioqpairs); 5463 req->cqe.result = cpu_to_le32((n->conf_ioqpairs - 1) | 5464 ((n->conf_ioqpairs - 1) << 16)); 5465 break; 5466 case NVME_ASYNCHRONOUS_EVENT_CONF: 5467 n->features.async_config = dw11; 5468 break; 5469 case NVME_TIMESTAMP: 5470 return nvme_set_feature_timestamp(n, req); 5471 case NVME_HOST_BEHAVIOR_SUPPORT: 5472 status = nvme_h2c(n, (uint8_t *)&n->features.hbs, 5473 sizeof(n->features.hbs), req); 5474 if (status) { 5475 return status; 5476 } 5477 5478 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 5479 ns = nvme_ns(n, i); 5480 5481 if (!ns) { 5482 continue; 5483 } 5484 5485 ns->id_ns.nlbaf = ns->nlbaf - 1; 5486 if (!n->features.hbs.lbafee) { 5487 ns->id_ns.nlbaf = MIN(ns->id_ns.nlbaf, 15); 5488 } 5489 } 5490 5491 return status; 5492 case NVME_COMMAND_SET_PROFILE: 5493 if (dw11 & 0x1ff) { 5494 trace_pci_nvme_err_invalid_iocsci(dw11 & 0x1ff); 5495 return NVME_CMD_SET_CMB_REJECTED | NVME_DNR; 5496 } 5497 break; 5498 default: 5499 return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR; 5500 } 5501 return NVME_SUCCESS; 5502 } 5503 5504 static uint16_t nvme_aer(NvmeCtrl *n, NvmeRequest *req) 5505 { 5506 trace_pci_nvme_aer(nvme_cid(req)); 5507 5508 if (n->outstanding_aers > n->params.aerl) { 5509 trace_pci_nvme_aer_aerl_exceeded(); 5510 return NVME_AER_LIMIT_EXCEEDED; 5511 } 5512 5513 n->aer_reqs[n->outstanding_aers] = req; 5514 n->outstanding_aers++; 5515 5516 if (!QTAILQ_EMPTY(&n->aer_queue)) { 5517 nvme_process_aers(n); 5518 } 5519 5520 return NVME_NO_COMPLETE; 5521 } 5522 5523 static void nvme_update_dmrsl(NvmeCtrl *n) 5524 { 5525 int nsid; 5526 5527 for (nsid = 1; nsid <= NVME_MAX_NAMESPACES; nsid++) { 5528 NvmeNamespace *ns = nvme_ns(n, nsid); 5529 if (!ns) { 5530 continue; 5531 } 5532 5533 n->dmrsl = MIN_NON_ZERO(n->dmrsl, 5534 BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1)); 5535 } 5536 } 5537 5538 static void nvme_select_iocs_ns(NvmeCtrl *n, NvmeNamespace *ns) 5539 { 5540 uint32_t cc = ldl_le_p(&n->bar.cc); 5541 5542 ns->iocs = nvme_cse_iocs_none; 5543 switch (ns->csi) { 5544 case NVME_CSI_NVM: 5545 if (NVME_CC_CSS(cc) != NVME_CC_CSS_ADMIN_ONLY) { 5546 ns->iocs = nvme_cse_iocs_nvm; 5547 } 5548 break; 5549 case NVME_CSI_ZONED: 5550 if (NVME_CC_CSS(cc) == NVME_CC_CSS_CSI) { 5551 ns->iocs = nvme_cse_iocs_zoned; 5552 } else if (NVME_CC_CSS(cc) == NVME_CC_CSS_NVM) { 5553 ns->iocs = nvme_cse_iocs_nvm; 5554 } 5555 break; 5556 } 5557 } 5558 5559 static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req) 5560 { 5561 NvmeNamespace *ns; 5562 NvmeCtrl *ctrl; 5563 uint16_t list[NVME_CONTROLLER_LIST_SIZE] = {}; 5564 uint32_t nsid = le32_to_cpu(req->cmd.nsid); 5565 uint32_t dw10 = le32_to_cpu(req->cmd.cdw10); 5566 uint8_t sel = dw10 & 0xf; 5567 uint16_t *nr_ids = &list[0]; 5568 uint16_t *ids = &list[1]; 5569 uint16_t ret; 5570 int i; 5571 5572 trace_pci_nvme_ns_attachment(nvme_cid(req), dw10 & 0xf); 5573 5574 if (!nvme_nsid_valid(n, nsid)) { 5575 return NVME_INVALID_NSID | NVME_DNR; 5576 } 5577 5578 ns = nvme_subsys_ns(n->subsys, nsid); 5579 if (!ns) { 5580 return NVME_INVALID_FIELD | NVME_DNR; 5581 } 5582 5583 ret = nvme_h2c(n, (uint8_t *)list, 4096, req); 5584 if (ret) { 5585 return ret; 5586 } 5587 5588 if (!*nr_ids) { 5589 return NVME_NS_CTRL_LIST_INVALID | NVME_DNR; 5590 } 5591 5592 *nr_ids = MIN(*nr_ids, NVME_CONTROLLER_LIST_SIZE - 1); 5593 for (i = 0; i < *nr_ids; i++) { 5594 ctrl = nvme_subsys_ctrl(n->subsys, ids[i]); 5595 if (!ctrl) { 5596 return NVME_NS_CTRL_LIST_INVALID | NVME_DNR; 5597 } 5598 5599 switch (sel) { 5600 case NVME_NS_ATTACHMENT_ATTACH: 5601 if (nvme_ns(ctrl, nsid)) { 5602 return NVME_NS_ALREADY_ATTACHED | NVME_DNR; 5603 } 5604 5605 if (ns->attached && !ns->params.shared) { 5606 return NVME_NS_PRIVATE | NVME_DNR; 5607 } 5608 5609 nvme_attach_ns(ctrl, ns); 5610 nvme_select_iocs_ns(ctrl, ns); 5611 5612 break; 5613 5614 case NVME_NS_ATTACHMENT_DETACH: 5615 if (!nvme_ns(ctrl, nsid)) { 5616 return NVME_NS_NOT_ATTACHED | NVME_DNR; 5617 } 5618 5619 ctrl->namespaces[nsid] = NULL; 5620 ns->attached--; 5621 5622 nvme_update_dmrsl(ctrl); 5623 5624 break; 5625 5626 default: 5627 return NVME_INVALID_FIELD | NVME_DNR; 5628 } 5629 5630 /* 5631 * Add namespace id to the changed namespace id list for event clearing 5632 * via Get Log Page command. 5633 */ 5634 if (!test_and_set_bit(nsid, ctrl->changed_nsids)) { 5635 nvme_enqueue_event(ctrl, NVME_AER_TYPE_NOTICE, 5636 NVME_AER_INFO_NOTICE_NS_ATTR_CHANGED, 5637 NVME_LOG_CHANGED_NSLIST); 5638 } 5639 } 5640 5641 return NVME_SUCCESS; 5642 } 5643 5644 typedef struct NvmeFormatAIOCB { 5645 BlockAIOCB common; 5646 BlockAIOCB *aiocb; 5647 QEMUBH *bh; 5648 NvmeRequest *req; 5649 int ret; 5650 5651 NvmeNamespace *ns; 5652 uint32_t nsid; 5653 bool broadcast; 5654 int64_t offset; 5655 5656 uint8_t lbaf; 5657 uint8_t mset; 5658 uint8_t pi; 5659 uint8_t pil; 5660 } NvmeFormatAIOCB; 5661 5662 static void nvme_format_bh(void *opaque); 5663 5664 static void nvme_format_cancel(BlockAIOCB *aiocb) 5665 { 5666 NvmeFormatAIOCB *iocb = container_of(aiocb, NvmeFormatAIOCB, common); 5667 5668 if (iocb->aiocb) { 5669 blk_aio_cancel_async(iocb->aiocb); 5670 } 5671 } 5672 5673 static const AIOCBInfo nvme_format_aiocb_info = { 5674 .aiocb_size = sizeof(NvmeFormatAIOCB), 5675 .cancel_async = nvme_format_cancel, 5676 .get_aio_context = nvme_get_aio_context, 5677 }; 5678 5679 static void nvme_format_set(NvmeNamespace *ns, uint8_t lbaf, uint8_t mset, 5680 uint8_t pi, uint8_t pil) 5681 { 5682 uint8_t lbafl = lbaf & 0xf; 5683 uint8_t lbafu = lbaf >> 4; 5684 5685 trace_pci_nvme_format_set(ns->params.nsid, lbaf, mset, pi, pil); 5686 5687 ns->id_ns.dps = (pil << 3) | pi; 5688 ns->id_ns.flbas = (lbafu << 5) | (mset << 4) | lbafl; 5689 5690 nvme_ns_init_format(ns); 5691 } 5692 5693 static void nvme_format_ns_cb(void *opaque, int ret) 5694 { 5695 NvmeFormatAIOCB *iocb = opaque; 5696 NvmeNamespace *ns = iocb->ns; 5697 int bytes; 5698 5699 if (ret < 0) { 5700 iocb->ret = ret; 5701 goto done; 5702 } 5703 5704 assert(ns); 5705 5706 if (iocb->offset < ns->size) { 5707 bytes = MIN(BDRV_REQUEST_MAX_BYTES, ns->size - iocb->offset); 5708 5709 iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, iocb->offset, 5710 bytes, BDRV_REQ_MAY_UNMAP, 5711 nvme_format_ns_cb, iocb); 5712 5713 iocb->offset += bytes; 5714 return; 5715 } 5716 5717 nvme_format_set(ns, iocb->lbaf, iocb->mset, iocb->pi, iocb->pil); 5718 ns->status = 0x0; 5719 iocb->ns = NULL; 5720 iocb->offset = 0; 5721 5722 done: 5723 iocb->aiocb = NULL; 5724 qemu_bh_schedule(iocb->bh); 5725 } 5726 5727 static uint16_t nvme_format_check(NvmeNamespace *ns, uint8_t lbaf, uint8_t pi) 5728 { 5729 if (ns->params.zoned) { 5730 return NVME_INVALID_FORMAT | NVME_DNR; 5731 } 5732 5733 if (lbaf > ns->id_ns.nlbaf) { 5734 return NVME_INVALID_FORMAT | NVME_DNR; 5735 } 5736 5737 if (pi && (ns->id_ns.lbaf[lbaf].ms < nvme_pi_tuple_size(ns))) { 5738 return NVME_INVALID_FORMAT | NVME_DNR; 5739 } 5740 5741 if (pi && pi > NVME_ID_NS_DPS_TYPE_3) { 5742 return NVME_INVALID_FIELD | NVME_DNR; 5743 } 5744 5745 return NVME_SUCCESS; 5746 } 5747 5748 static void nvme_format_bh(void *opaque) 5749 { 5750 NvmeFormatAIOCB *iocb = opaque; 5751 NvmeRequest *req = iocb->req; 5752 NvmeCtrl *n = nvme_ctrl(req); 5753 uint32_t dw10 = le32_to_cpu(req->cmd.cdw10); 5754 uint8_t lbaf = dw10 & 0xf; 5755 uint8_t pi = (dw10 >> 5) & 0x7; 5756 uint16_t status; 5757 int i; 5758 5759 if (iocb->ret < 0) { 5760 goto done; 5761 } 5762 5763 if (iocb->broadcast) { 5764 for (i = iocb->nsid + 1; i <= NVME_MAX_NAMESPACES; i++) { 5765 iocb->ns = nvme_ns(n, i); 5766 if (iocb->ns) { 5767 iocb->nsid = i; 5768 break; 5769 } 5770 } 5771 } 5772 5773 if (!iocb->ns) { 5774 goto done; 5775 } 5776 5777 status = nvme_format_check(iocb->ns, lbaf, pi); 5778 if (status) { 5779 req->status = status; 5780 goto done; 5781 } 5782 5783 iocb->ns->status = NVME_FORMAT_IN_PROGRESS; 5784 nvme_format_ns_cb(iocb, 0); 5785 return; 5786 5787 done: 5788 qemu_bh_delete(iocb->bh); 5789 iocb->bh = NULL; 5790 5791 iocb->common.cb(iocb->common.opaque, iocb->ret); 5792 5793 qemu_aio_unref(iocb); 5794 } 5795 5796 static uint16_t nvme_format(NvmeCtrl *n, NvmeRequest *req) 5797 { 5798 NvmeFormatAIOCB *iocb; 5799 uint32_t nsid = le32_to_cpu(req->cmd.nsid); 5800 uint32_t dw10 = le32_to_cpu(req->cmd.cdw10); 5801 uint8_t lbaf = dw10 & 0xf; 5802 uint8_t mset = (dw10 >> 4) & 0x1; 5803 uint8_t pi = (dw10 >> 5) & 0x7; 5804 uint8_t pil = (dw10 >> 8) & 0x1; 5805 uint8_t lbafu = (dw10 >> 12) & 0x3; 5806 uint16_t status; 5807 5808 iocb = qemu_aio_get(&nvme_format_aiocb_info, NULL, nvme_misc_cb, req); 5809 5810 iocb->req = req; 5811 iocb->bh = qemu_bh_new(nvme_format_bh, iocb); 5812 iocb->ret = 0; 5813 iocb->ns = NULL; 5814 iocb->nsid = 0; 5815 iocb->lbaf = lbaf; 5816 iocb->mset = mset; 5817 iocb->pi = pi; 5818 iocb->pil = pil; 5819 iocb->broadcast = (nsid == NVME_NSID_BROADCAST); 5820 iocb->offset = 0; 5821 5822 if (n->features.hbs.lbafee) { 5823 iocb->lbaf |= lbafu << 4; 5824 } 5825 5826 if (!iocb->broadcast) { 5827 if (!nvme_nsid_valid(n, nsid)) { 5828 status = NVME_INVALID_NSID | NVME_DNR; 5829 goto out; 5830 } 5831 5832 iocb->ns = nvme_ns(n, nsid); 5833 if (!iocb->ns) { 5834 status = NVME_INVALID_FIELD | NVME_DNR; 5835 goto out; 5836 } 5837 } 5838 5839 req->aiocb = &iocb->common; 5840 qemu_bh_schedule(iocb->bh); 5841 5842 return NVME_NO_COMPLETE; 5843 5844 out: 5845 qemu_bh_delete(iocb->bh); 5846 iocb->bh = NULL; 5847 qemu_aio_unref(iocb); 5848 return status; 5849 } 5850 5851 static void nvme_get_virt_res_num(NvmeCtrl *n, uint8_t rt, int *num_total, 5852 int *num_prim, int *num_sec) 5853 { 5854 *num_total = le32_to_cpu(rt ? 5855 n->pri_ctrl_cap.vifrt : n->pri_ctrl_cap.vqfrt); 5856 *num_prim = le16_to_cpu(rt ? 5857 n->pri_ctrl_cap.virfap : n->pri_ctrl_cap.vqrfap); 5858 *num_sec = le16_to_cpu(rt ? n->pri_ctrl_cap.virfa : n->pri_ctrl_cap.vqrfa); 5859 } 5860 5861 static uint16_t nvme_assign_virt_res_to_prim(NvmeCtrl *n, NvmeRequest *req, 5862 uint16_t cntlid, uint8_t rt, 5863 int nr) 5864 { 5865 int num_total, num_prim, num_sec; 5866 5867 if (cntlid != n->cntlid) { 5868 return NVME_INVALID_CTRL_ID | NVME_DNR; 5869 } 5870 5871 nvme_get_virt_res_num(n, rt, &num_total, &num_prim, &num_sec); 5872 5873 if (nr > num_total) { 5874 return NVME_INVALID_NUM_RESOURCES | NVME_DNR; 5875 } 5876 5877 if (nr > num_total - num_sec) { 5878 return NVME_INVALID_RESOURCE_ID | NVME_DNR; 5879 } 5880 5881 if (rt) { 5882 n->next_pri_ctrl_cap.virfap = cpu_to_le16(nr); 5883 } else { 5884 n->next_pri_ctrl_cap.vqrfap = cpu_to_le16(nr); 5885 } 5886 5887 req->cqe.result = cpu_to_le32(nr); 5888 return req->status; 5889 } 5890 5891 static void nvme_update_virt_res(NvmeCtrl *n, NvmeSecCtrlEntry *sctrl, 5892 uint8_t rt, int nr) 5893 { 5894 int prev_nr, prev_total; 5895 5896 if (rt) { 5897 prev_nr = le16_to_cpu(sctrl->nvi); 5898 prev_total = le32_to_cpu(n->pri_ctrl_cap.virfa); 5899 sctrl->nvi = cpu_to_le16(nr); 5900 n->pri_ctrl_cap.virfa = cpu_to_le32(prev_total + nr - prev_nr); 5901 } else { 5902 prev_nr = le16_to_cpu(sctrl->nvq); 5903 prev_total = le32_to_cpu(n->pri_ctrl_cap.vqrfa); 5904 sctrl->nvq = cpu_to_le16(nr); 5905 n->pri_ctrl_cap.vqrfa = cpu_to_le32(prev_total + nr - prev_nr); 5906 } 5907 } 5908 5909 static uint16_t nvme_assign_virt_res_to_sec(NvmeCtrl *n, NvmeRequest *req, 5910 uint16_t cntlid, uint8_t rt, int nr) 5911 { 5912 int num_total, num_prim, num_sec, num_free, diff, limit; 5913 NvmeSecCtrlEntry *sctrl; 5914 5915 sctrl = nvme_sctrl_for_cntlid(n, cntlid); 5916 if (!sctrl) { 5917 return NVME_INVALID_CTRL_ID | NVME_DNR; 5918 } 5919 5920 if (sctrl->scs) { 5921 return NVME_INVALID_SEC_CTRL_STATE | NVME_DNR; 5922 } 5923 5924 limit = le16_to_cpu(rt ? n->pri_ctrl_cap.vifrsm : n->pri_ctrl_cap.vqfrsm); 5925 if (nr > limit) { 5926 return NVME_INVALID_NUM_RESOURCES | NVME_DNR; 5927 } 5928 5929 nvme_get_virt_res_num(n, rt, &num_total, &num_prim, &num_sec); 5930 num_free = num_total - num_prim - num_sec; 5931 diff = nr - le16_to_cpu(rt ? sctrl->nvi : sctrl->nvq); 5932 5933 if (diff > num_free) { 5934 return NVME_INVALID_RESOURCE_ID | NVME_DNR; 5935 } 5936 5937 nvme_update_virt_res(n, sctrl, rt, nr); 5938 req->cqe.result = cpu_to_le32(nr); 5939 5940 return req->status; 5941 } 5942 5943 static uint16_t nvme_virt_set_state(NvmeCtrl *n, uint16_t cntlid, bool online) 5944 { 5945 NvmeCtrl *sn = NULL; 5946 NvmeSecCtrlEntry *sctrl; 5947 int vf_index; 5948 5949 sctrl = nvme_sctrl_for_cntlid(n, cntlid); 5950 if (!sctrl) { 5951 return NVME_INVALID_CTRL_ID | NVME_DNR; 5952 } 5953 5954 if (!pci_is_vf(&n->parent_obj)) { 5955 vf_index = le16_to_cpu(sctrl->vfn) - 1; 5956 sn = NVME(pcie_sriov_get_vf_at_index(&n->parent_obj, vf_index)); 5957 } 5958 5959 if (online) { 5960 if (!sctrl->nvi || (le16_to_cpu(sctrl->nvq) < 2) || !sn) { 5961 return NVME_INVALID_SEC_CTRL_STATE | NVME_DNR; 5962 } 5963 5964 if (!sctrl->scs) { 5965 sctrl->scs = 0x1; 5966 nvme_ctrl_reset(sn, NVME_RESET_FUNCTION); 5967 } 5968 } else { 5969 nvme_update_virt_res(n, sctrl, NVME_VIRT_RES_INTERRUPT, 0); 5970 nvme_update_virt_res(n, sctrl, NVME_VIRT_RES_QUEUE, 0); 5971 5972 if (sctrl->scs) { 5973 sctrl->scs = 0x0; 5974 if (sn) { 5975 nvme_ctrl_reset(sn, NVME_RESET_FUNCTION); 5976 } 5977 } 5978 } 5979 5980 return NVME_SUCCESS; 5981 } 5982 5983 static uint16_t nvme_virt_mngmt(NvmeCtrl *n, NvmeRequest *req) 5984 { 5985 uint32_t dw10 = le32_to_cpu(req->cmd.cdw10); 5986 uint32_t dw11 = le32_to_cpu(req->cmd.cdw11); 5987 uint8_t act = dw10 & 0xf; 5988 uint8_t rt = (dw10 >> 8) & 0x7; 5989 uint16_t cntlid = (dw10 >> 16) & 0xffff; 5990 int nr = dw11 & 0xffff; 5991 5992 trace_pci_nvme_virt_mngmt(nvme_cid(req), act, cntlid, rt ? "VI" : "VQ", nr); 5993 5994 if (rt != NVME_VIRT_RES_QUEUE && rt != NVME_VIRT_RES_INTERRUPT) { 5995 return NVME_INVALID_RESOURCE_ID | NVME_DNR; 5996 } 5997 5998 switch (act) { 5999 case NVME_VIRT_MNGMT_ACTION_SEC_ASSIGN: 6000 return nvme_assign_virt_res_to_sec(n, req, cntlid, rt, nr); 6001 case NVME_VIRT_MNGMT_ACTION_PRM_ALLOC: 6002 return nvme_assign_virt_res_to_prim(n, req, cntlid, rt, nr); 6003 case NVME_VIRT_MNGMT_ACTION_SEC_ONLINE: 6004 return nvme_virt_set_state(n, cntlid, true); 6005 case NVME_VIRT_MNGMT_ACTION_SEC_OFFLINE: 6006 return nvme_virt_set_state(n, cntlid, false); 6007 default: 6008 return NVME_INVALID_FIELD | NVME_DNR; 6009 } 6010 } 6011 6012 static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) 6013 { 6014 uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1); 6015 uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2); 6016 int i; 6017 6018 /* Address should be page aligned */ 6019 if (dbs_addr & (n->page_size - 1) || eis_addr & (n->page_size - 1)) { 6020 return NVME_INVALID_FIELD | NVME_DNR; 6021 } 6022 6023 /* Save shadow buffer base addr for use during queue creation */ 6024 n->dbbuf_dbs = dbs_addr; 6025 n->dbbuf_eis = eis_addr; 6026 n->dbbuf_enabled = true; 6027 6028 for (i = 0; i < n->params.max_ioqpairs + 1; i++) { 6029 NvmeSQueue *sq = n->sq[i]; 6030 NvmeCQueue *cq = n->cq[i]; 6031 6032 if (sq) { 6033 /* 6034 * CAP.DSTRD is 0, so offset of ith sq db_addr is (i<<3) 6035 * nvme_process_db() uses this hard-coded way to calculate 6036 * doorbell offsets. Be consistent with that here. 6037 */ 6038 sq->db_addr = dbs_addr + (i << 3); 6039 sq->ei_addr = eis_addr + (i << 3); 6040 pci_dma_write(&n->parent_obj, sq->db_addr, &sq->tail, 6041 sizeof(sq->tail)); 6042 } 6043 6044 if (cq) { 6045 /* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2) */ 6046 cq->db_addr = dbs_addr + (i << 3) + (1 << 2); 6047 cq->ei_addr = eis_addr + (i << 3) + (1 << 2); 6048 pci_dma_write(&n->parent_obj, cq->db_addr, &cq->head, 6049 sizeof(cq->head)); 6050 } 6051 } 6052 6053 trace_pci_nvme_dbbuf_config(dbs_addr, eis_addr); 6054 6055 return NVME_SUCCESS; 6056 } 6057 6058 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req) 6059 { 6060 trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcode, 6061 nvme_adm_opc_str(req->cmd.opcode)); 6062 6063 if (!(nvme_cse_acs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) { 6064 trace_pci_nvme_err_invalid_admin_opc(req->cmd.opcode); 6065 return NVME_INVALID_OPCODE | NVME_DNR; 6066 } 6067 6068 /* SGLs shall not be used for Admin commands in NVMe over PCIe */ 6069 if (NVME_CMD_FLAGS_PSDT(req->cmd.flags) != NVME_PSDT_PRP) { 6070 return NVME_INVALID_FIELD | NVME_DNR; 6071 } 6072 6073 if (NVME_CMD_FLAGS_FUSE(req->cmd.flags)) { 6074 return NVME_INVALID_FIELD; 6075 } 6076 6077 switch (req->cmd.opcode) { 6078 case NVME_ADM_CMD_DELETE_SQ: 6079 return nvme_del_sq(n, req); 6080 case NVME_ADM_CMD_CREATE_SQ: 6081 return nvme_create_sq(n, req); 6082 case NVME_ADM_CMD_GET_LOG_PAGE: 6083 return nvme_get_log(n, req); 6084 case NVME_ADM_CMD_DELETE_CQ: 6085 return nvme_del_cq(n, req); 6086 case NVME_ADM_CMD_CREATE_CQ: 6087 return nvme_create_cq(n, req); 6088 case NVME_ADM_CMD_IDENTIFY: 6089 return nvme_identify(n, req); 6090 case NVME_ADM_CMD_ABORT: 6091 return nvme_abort(n, req); 6092 case NVME_ADM_CMD_SET_FEATURES: 6093 return nvme_set_feature(n, req); 6094 case NVME_ADM_CMD_GET_FEATURES: 6095 return nvme_get_feature(n, req); 6096 case NVME_ADM_CMD_ASYNC_EV_REQ: 6097 return nvme_aer(n, req); 6098 case NVME_ADM_CMD_NS_ATTACHMENT: 6099 return nvme_ns_attachment(n, req); 6100 case NVME_ADM_CMD_VIRT_MNGMT: 6101 return nvme_virt_mngmt(n, req); 6102 case NVME_ADM_CMD_DBBUF_CONFIG: 6103 return nvme_dbbuf_config(n, req); 6104 case NVME_ADM_CMD_FORMAT_NVM: 6105 return nvme_format(n, req); 6106 default: 6107 assert(false); 6108 } 6109 6110 return NVME_INVALID_OPCODE | NVME_DNR; 6111 } 6112 6113 static void nvme_update_sq_eventidx(const NvmeSQueue *sq) 6114 { 6115 pci_dma_write(&sq->ctrl->parent_obj, sq->ei_addr, &sq->tail, 6116 sizeof(sq->tail)); 6117 trace_pci_nvme_eventidx_sq(sq->sqid, sq->tail); 6118 } 6119 6120 static void nvme_update_sq_tail(NvmeSQueue *sq) 6121 { 6122 pci_dma_read(&sq->ctrl->parent_obj, sq->db_addr, &sq->tail, 6123 sizeof(sq->tail)); 6124 trace_pci_nvme_shadow_doorbell_sq(sq->sqid, sq->tail); 6125 } 6126 6127 static void nvme_process_sq(void *opaque) 6128 { 6129 NvmeSQueue *sq = opaque; 6130 NvmeCtrl *n = sq->ctrl; 6131 NvmeCQueue *cq = n->cq[sq->cqid]; 6132 6133 uint16_t status; 6134 hwaddr addr; 6135 NvmeCmd cmd; 6136 NvmeRequest *req; 6137 6138 if (n->dbbuf_enabled) { 6139 nvme_update_sq_tail(sq); 6140 } 6141 6142 while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) { 6143 addr = sq->dma_addr + sq->head * n->sqe_size; 6144 if (nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd))) { 6145 trace_pci_nvme_err_addr_read(addr); 6146 trace_pci_nvme_err_cfs(); 6147 stl_le_p(&n->bar.csts, NVME_CSTS_FAILED); 6148 break; 6149 } 6150 nvme_inc_sq_head(sq); 6151 6152 req = QTAILQ_FIRST(&sq->req_list); 6153 QTAILQ_REMOVE(&sq->req_list, req, entry); 6154 QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry); 6155 nvme_req_clear(req); 6156 req->cqe.cid = cmd.cid; 6157 memcpy(&req->cmd, &cmd, sizeof(NvmeCmd)); 6158 6159 status = sq->sqid ? nvme_io_cmd(n, req) : 6160 nvme_admin_cmd(n, req); 6161 if (status != NVME_NO_COMPLETE) { 6162 req->status = status; 6163 nvme_enqueue_req_completion(cq, req); 6164 } 6165 6166 if (n->dbbuf_enabled) { 6167 nvme_update_sq_eventidx(sq); 6168 nvme_update_sq_tail(sq); 6169 } 6170 } 6171 } 6172 6173 static void nvme_update_msixcap_ts(PCIDevice *pci_dev, uint32_t table_size) 6174 { 6175 uint8_t *config; 6176 6177 if (!msix_present(pci_dev)) { 6178 return; 6179 } 6180 6181 assert(table_size > 0 && table_size <= pci_dev->msix_entries_nr); 6182 6183 config = pci_dev->config + pci_dev->msix_cap; 6184 pci_set_word_by_mask(config + PCI_MSIX_FLAGS, PCI_MSIX_FLAGS_QSIZE, 6185 table_size - 1); 6186 } 6187 6188 static void nvme_activate_virt_res(NvmeCtrl *n) 6189 { 6190 PCIDevice *pci_dev = &n->parent_obj; 6191 NvmePriCtrlCap *cap = &n->pri_ctrl_cap; 6192 NvmeSecCtrlEntry *sctrl; 6193 6194 /* -1 to account for the admin queue */ 6195 if (pci_is_vf(pci_dev)) { 6196 sctrl = nvme_sctrl(n); 6197 cap->vqprt = sctrl->nvq; 6198 cap->viprt = sctrl->nvi; 6199 n->conf_ioqpairs = sctrl->nvq ? le16_to_cpu(sctrl->nvq) - 1 : 0; 6200 n->conf_msix_qsize = sctrl->nvi ? le16_to_cpu(sctrl->nvi) : 1; 6201 } else { 6202 cap->vqrfap = n->next_pri_ctrl_cap.vqrfap; 6203 cap->virfap = n->next_pri_ctrl_cap.virfap; 6204 n->conf_ioqpairs = le16_to_cpu(cap->vqprt) + 6205 le16_to_cpu(cap->vqrfap) - 1; 6206 n->conf_msix_qsize = le16_to_cpu(cap->viprt) + 6207 le16_to_cpu(cap->virfap); 6208 } 6209 } 6210 6211 static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) 6212 { 6213 PCIDevice *pci_dev = &n->parent_obj; 6214 NvmeSecCtrlEntry *sctrl; 6215 NvmeNamespace *ns; 6216 int i; 6217 6218 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 6219 ns = nvme_ns(n, i); 6220 if (!ns) { 6221 continue; 6222 } 6223 6224 nvme_ns_drain(ns); 6225 } 6226 6227 for (i = 0; i < n->params.max_ioqpairs + 1; i++) { 6228 if (n->sq[i] != NULL) { 6229 nvme_free_sq(n->sq[i], n); 6230 } 6231 } 6232 for (i = 0; i < n->params.max_ioqpairs + 1; i++) { 6233 if (n->cq[i] != NULL) { 6234 nvme_free_cq(n->cq[i], n); 6235 } 6236 } 6237 6238 while (!QTAILQ_EMPTY(&n->aer_queue)) { 6239 NvmeAsyncEvent *event = QTAILQ_FIRST(&n->aer_queue); 6240 QTAILQ_REMOVE(&n->aer_queue, event, entry); 6241 g_free(event); 6242 } 6243 6244 if (n->params.sriov_max_vfs) { 6245 if (!pci_is_vf(pci_dev)) { 6246 for (i = 0; i < n->sec_ctrl_list.numcntl; i++) { 6247 sctrl = &n->sec_ctrl_list.sec[i]; 6248 nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); 6249 } 6250 6251 if (rst != NVME_RESET_CONTROLLER) { 6252 pcie_sriov_pf_disable_vfs(pci_dev); 6253 } 6254 } 6255 6256 if (rst != NVME_RESET_CONTROLLER) { 6257 nvme_activate_virt_res(n); 6258 } 6259 } 6260 6261 n->aer_queued = 0; 6262 n->aer_mask = 0; 6263 n->outstanding_aers = 0; 6264 n->qs_created = false; 6265 6266 nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize); 6267 6268 if (pci_is_vf(pci_dev)) { 6269 sctrl = nvme_sctrl(n); 6270 6271 stl_le_p(&n->bar.csts, sctrl->scs ? 0 : NVME_CSTS_FAILED); 6272 } else { 6273 stl_le_p(&n->bar.csts, 0); 6274 } 6275 6276 stl_le_p(&n->bar.intms, 0); 6277 stl_le_p(&n->bar.intmc, 0); 6278 stl_le_p(&n->bar.cc, 0); 6279 6280 n->dbbuf_dbs = 0; 6281 n->dbbuf_eis = 0; 6282 n->dbbuf_enabled = false; 6283 } 6284 6285 static void nvme_ctrl_shutdown(NvmeCtrl *n) 6286 { 6287 NvmeNamespace *ns; 6288 int i; 6289 6290 if (n->pmr.dev) { 6291 memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size); 6292 } 6293 6294 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 6295 ns = nvme_ns(n, i); 6296 if (!ns) { 6297 continue; 6298 } 6299 6300 nvme_ns_shutdown(ns); 6301 } 6302 } 6303 6304 static void nvme_select_iocs(NvmeCtrl *n) 6305 { 6306 NvmeNamespace *ns; 6307 int i; 6308 6309 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 6310 ns = nvme_ns(n, i); 6311 if (!ns) { 6312 continue; 6313 } 6314 6315 nvme_select_iocs_ns(n, ns); 6316 } 6317 } 6318 6319 static int nvme_start_ctrl(NvmeCtrl *n) 6320 { 6321 uint64_t cap = ldq_le_p(&n->bar.cap); 6322 uint32_t cc = ldl_le_p(&n->bar.cc); 6323 uint32_t aqa = ldl_le_p(&n->bar.aqa); 6324 uint64_t asq = ldq_le_p(&n->bar.asq); 6325 uint64_t acq = ldq_le_p(&n->bar.acq); 6326 uint32_t page_bits = NVME_CC_MPS(cc) + 12; 6327 uint32_t page_size = 1 << page_bits; 6328 NvmeSecCtrlEntry *sctrl = nvme_sctrl(n); 6329 6330 if (pci_is_vf(&n->parent_obj) && !sctrl->scs) { 6331 trace_pci_nvme_err_startfail_virt_state(le16_to_cpu(sctrl->nvi), 6332 le16_to_cpu(sctrl->nvq), 6333 sctrl->scs ? "ONLINE" : 6334 "OFFLINE"); 6335 return -1; 6336 } 6337 if (unlikely(n->cq[0])) { 6338 trace_pci_nvme_err_startfail_cq(); 6339 return -1; 6340 } 6341 if (unlikely(n->sq[0])) { 6342 trace_pci_nvme_err_startfail_sq(); 6343 return -1; 6344 } 6345 if (unlikely(asq & (page_size - 1))) { 6346 trace_pci_nvme_err_startfail_asq_misaligned(asq); 6347 return -1; 6348 } 6349 if (unlikely(acq & (page_size - 1))) { 6350 trace_pci_nvme_err_startfail_acq_misaligned(acq); 6351 return -1; 6352 } 6353 if (unlikely(!(NVME_CAP_CSS(cap) & (1 << NVME_CC_CSS(cc))))) { 6354 trace_pci_nvme_err_startfail_css(NVME_CC_CSS(cc)); 6355 return -1; 6356 } 6357 if (unlikely(NVME_CC_MPS(cc) < NVME_CAP_MPSMIN(cap))) { 6358 trace_pci_nvme_err_startfail_page_too_small( 6359 NVME_CC_MPS(cc), 6360 NVME_CAP_MPSMIN(cap)); 6361 return -1; 6362 } 6363 if (unlikely(NVME_CC_MPS(cc) > 6364 NVME_CAP_MPSMAX(cap))) { 6365 trace_pci_nvme_err_startfail_page_too_large( 6366 NVME_CC_MPS(cc), 6367 NVME_CAP_MPSMAX(cap)); 6368 return -1; 6369 } 6370 if (unlikely(NVME_CC_IOCQES(cc) < 6371 NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) { 6372 trace_pci_nvme_err_startfail_cqent_too_small( 6373 NVME_CC_IOCQES(cc), 6374 NVME_CTRL_CQES_MIN(cap)); 6375 return -1; 6376 } 6377 if (unlikely(NVME_CC_IOCQES(cc) > 6378 NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) { 6379 trace_pci_nvme_err_startfail_cqent_too_large( 6380 NVME_CC_IOCQES(cc), 6381 NVME_CTRL_CQES_MAX(cap)); 6382 return -1; 6383 } 6384 if (unlikely(NVME_CC_IOSQES(cc) < 6385 NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) { 6386 trace_pci_nvme_err_startfail_sqent_too_small( 6387 NVME_CC_IOSQES(cc), 6388 NVME_CTRL_SQES_MIN(cap)); 6389 return -1; 6390 } 6391 if (unlikely(NVME_CC_IOSQES(cc) > 6392 NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) { 6393 trace_pci_nvme_err_startfail_sqent_too_large( 6394 NVME_CC_IOSQES(cc), 6395 NVME_CTRL_SQES_MAX(cap)); 6396 return -1; 6397 } 6398 if (unlikely(!NVME_AQA_ASQS(aqa))) { 6399 trace_pci_nvme_err_startfail_asqent_sz_zero(); 6400 return -1; 6401 } 6402 if (unlikely(!NVME_AQA_ACQS(aqa))) { 6403 trace_pci_nvme_err_startfail_acqent_sz_zero(); 6404 return -1; 6405 } 6406 6407 n->page_bits = page_bits; 6408 n->page_size = page_size; 6409 n->max_prp_ents = n->page_size / sizeof(uint64_t); 6410 n->cqe_size = 1 << NVME_CC_IOCQES(cc); 6411 n->sqe_size = 1 << NVME_CC_IOSQES(cc); 6412 nvme_init_cq(&n->admin_cq, n, acq, 0, 0, NVME_AQA_ACQS(aqa) + 1, 1); 6413 nvme_init_sq(&n->admin_sq, n, asq, 0, 0, NVME_AQA_ASQS(aqa) + 1); 6414 6415 nvme_set_timestamp(n, 0ULL); 6416 6417 nvme_select_iocs(n); 6418 6419 return 0; 6420 } 6421 6422 static void nvme_cmb_enable_regs(NvmeCtrl *n) 6423 { 6424 uint32_t cmbloc = ldl_le_p(&n->bar.cmbloc); 6425 uint32_t cmbsz = ldl_le_p(&n->bar.cmbsz); 6426 6427 NVME_CMBLOC_SET_CDPCILS(cmbloc, 1); 6428 NVME_CMBLOC_SET_CDPMLS(cmbloc, 1); 6429 NVME_CMBLOC_SET_BIR(cmbloc, NVME_CMB_BIR); 6430 stl_le_p(&n->bar.cmbloc, cmbloc); 6431 6432 NVME_CMBSZ_SET_SQS(cmbsz, 1); 6433 NVME_CMBSZ_SET_CQS(cmbsz, 0); 6434 NVME_CMBSZ_SET_LISTS(cmbsz, 1); 6435 NVME_CMBSZ_SET_RDS(cmbsz, 1); 6436 NVME_CMBSZ_SET_WDS(cmbsz, 1); 6437 NVME_CMBSZ_SET_SZU(cmbsz, 2); /* MBs */ 6438 NVME_CMBSZ_SET_SZ(cmbsz, n->params.cmb_size_mb); 6439 stl_le_p(&n->bar.cmbsz, cmbsz); 6440 } 6441 6442 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, 6443 unsigned size) 6444 { 6445 uint64_t cap = ldq_le_p(&n->bar.cap); 6446 uint32_t cc = ldl_le_p(&n->bar.cc); 6447 uint32_t intms = ldl_le_p(&n->bar.intms); 6448 uint32_t csts = ldl_le_p(&n->bar.csts); 6449 uint32_t pmrsts = ldl_le_p(&n->bar.pmrsts); 6450 6451 if (unlikely(offset & (sizeof(uint32_t) - 1))) { 6452 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32, 6453 "MMIO write not 32-bit aligned," 6454 " offset=0x%"PRIx64"", offset); 6455 /* should be ignored, fall through for now */ 6456 } 6457 6458 if (unlikely(size < sizeof(uint32_t))) { 6459 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall, 6460 "MMIO write smaller than 32-bits," 6461 " offset=0x%"PRIx64", size=%u", 6462 offset, size); 6463 /* should be ignored, fall through for now */ 6464 } 6465 6466 switch (offset) { 6467 case NVME_REG_INTMS: 6468 if (unlikely(msix_enabled(&(n->parent_obj)))) { 6469 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, 6470 "undefined access to interrupt mask set" 6471 " when MSI-X is enabled"); 6472 /* should be ignored, fall through for now */ 6473 } 6474 intms |= data; 6475 stl_le_p(&n->bar.intms, intms); 6476 n->bar.intmc = n->bar.intms; 6477 trace_pci_nvme_mmio_intm_set(data & 0xffffffff, intms); 6478 nvme_irq_check(n); 6479 break; 6480 case NVME_REG_INTMC: 6481 if (unlikely(msix_enabled(&(n->parent_obj)))) { 6482 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, 6483 "undefined access to interrupt mask clr" 6484 " when MSI-X is enabled"); 6485 /* should be ignored, fall through for now */ 6486 } 6487 intms &= ~data; 6488 stl_le_p(&n->bar.intms, intms); 6489 n->bar.intmc = n->bar.intms; 6490 trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, intms); 6491 nvme_irq_check(n); 6492 break; 6493 case NVME_REG_CC: 6494 stl_le_p(&n->bar.cc, data); 6495 6496 trace_pci_nvme_mmio_cfg(data & 0xffffffff); 6497 6498 if (NVME_CC_SHN(data) && !(NVME_CC_SHN(cc))) { 6499 trace_pci_nvme_mmio_shutdown_set(); 6500 nvme_ctrl_shutdown(n); 6501 csts &= ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT); 6502 csts |= NVME_CSTS_SHST_COMPLETE; 6503 } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) { 6504 trace_pci_nvme_mmio_shutdown_cleared(); 6505 csts &= ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT); 6506 } 6507 6508 if (NVME_CC_EN(data) && !NVME_CC_EN(cc)) { 6509 if (unlikely(nvme_start_ctrl(n))) { 6510 trace_pci_nvme_err_startfail(); 6511 csts = NVME_CSTS_FAILED; 6512 } else { 6513 trace_pci_nvme_mmio_start_success(); 6514 csts = NVME_CSTS_READY; 6515 } 6516 } else if (!NVME_CC_EN(data) && NVME_CC_EN(cc)) { 6517 trace_pci_nvme_mmio_stopped(); 6518 nvme_ctrl_reset(n, NVME_RESET_CONTROLLER); 6519 6520 break; 6521 } 6522 6523 stl_le_p(&n->bar.csts, csts); 6524 6525 break; 6526 case NVME_REG_CSTS: 6527 if (data & (1 << 4)) { 6528 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported, 6529 "attempted to W1C CSTS.NSSRO" 6530 " but CAP.NSSRS is zero (not supported)"); 6531 } else if (data != 0) { 6532 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts, 6533 "attempted to set a read only bit" 6534 " of controller status"); 6535 } 6536 break; 6537 case NVME_REG_NSSR: 6538 if (data == 0x4e564d65) { 6539 trace_pci_nvme_ub_mmiowr_ssreset_unsupported(); 6540 } else { 6541 /* The spec says that writes of other values have no effect */ 6542 return; 6543 } 6544 break; 6545 case NVME_REG_AQA: 6546 stl_le_p(&n->bar.aqa, data); 6547 trace_pci_nvme_mmio_aqattr(data & 0xffffffff); 6548 break; 6549 case NVME_REG_ASQ: 6550 stn_le_p(&n->bar.asq, size, data); 6551 trace_pci_nvme_mmio_asqaddr(data); 6552 break; 6553 case NVME_REG_ASQ + 4: 6554 stl_le_p((uint8_t *)&n->bar.asq + 4, data); 6555 trace_pci_nvme_mmio_asqaddr_hi(data, ldq_le_p(&n->bar.asq)); 6556 break; 6557 case NVME_REG_ACQ: 6558 trace_pci_nvme_mmio_acqaddr(data); 6559 stn_le_p(&n->bar.acq, size, data); 6560 break; 6561 case NVME_REG_ACQ + 4: 6562 stl_le_p((uint8_t *)&n->bar.acq + 4, data); 6563 trace_pci_nvme_mmio_acqaddr_hi(data, ldq_le_p(&n->bar.acq)); 6564 break; 6565 case NVME_REG_CMBLOC: 6566 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved, 6567 "invalid write to reserved CMBLOC" 6568 " when CMBSZ is zero, ignored"); 6569 return; 6570 case NVME_REG_CMBSZ: 6571 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly, 6572 "invalid write to read only CMBSZ, ignored"); 6573 return; 6574 case NVME_REG_CMBMSC: 6575 if (!NVME_CAP_CMBS(cap)) { 6576 return; 6577 } 6578 6579 stn_le_p(&n->bar.cmbmsc, size, data); 6580 n->cmb.cmse = false; 6581 6582 if (NVME_CMBMSC_CRE(data)) { 6583 nvme_cmb_enable_regs(n); 6584 6585 if (NVME_CMBMSC_CMSE(data)) { 6586 uint64_t cmbmsc = ldq_le_p(&n->bar.cmbmsc); 6587 hwaddr cba = NVME_CMBMSC_CBA(cmbmsc) << CMBMSC_CBA_SHIFT; 6588 if (cba + int128_get64(n->cmb.mem.size) < cba) { 6589 uint32_t cmbsts = ldl_le_p(&n->bar.cmbsts); 6590 NVME_CMBSTS_SET_CBAI(cmbsts, 1); 6591 stl_le_p(&n->bar.cmbsts, cmbsts); 6592 return; 6593 } 6594 6595 n->cmb.cba = cba; 6596 n->cmb.cmse = true; 6597 } 6598 } else { 6599 n->bar.cmbsz = 0; 6600 n->bar.cmbloc = 0; 6601 } 6602 6603 return; 6604 case NVME_REG_CMBMSC + 4: 6605 stl_le_p((uint8_t *)&n->bar.cmbmsc + 4, data); 6606 return; 6607 6608 case NVME_REG_PMRCAP: 6609 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly, 6610 "invalid write to PMRCAP register, ignored"); 6611 return; 6612 case NVME_REG_PMRCTL: 6613 if (!NVME_CAP_PMRS(cap)) { 6614 return; 6615 } 6616 6617 stl_le_p(&n->bar.pmrctl, data); 6618 if (NVME_PMRCTL_EN(data)) { 6619 memory_region_set_enabled(&n->pmr.dev->mr, true); 6620 pmrsts = 0; 6621 } else { 6622 memory_region_set_enabled(&n->pmr.dev->mr, false); 6623 NVME_PMRSTS_SET_NRDY(pmrsts, 1); 6624 n->pmr.cmse = false; 6625 } 6626 stl_le_p(&n->bar.pmrsts, pmrsts); 6627 return; 6628 case NVME_REG_PMRSTS: 6629 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly, 6630 "invalid write to PMRSTS register, ignored"); 6631 return; 6632 case NVME_REG_PMREBS: 6633 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly, 6634 "invalid write to PMREBS register, ignored"); 6635 return; 6636 case NVME_REG_PMRSWTP: 6637 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly, 6638 "invalid write to PMRSWTP register, ignored"); 6639 return; 6640 case NVME_REG_PMRMSCL: 6641 if (!NVME_CAP_PMRS(cap)) { 6642 return; 6643 } 6644 6645 stl_le_p(&n->bar.pmrmscl, data); 6646 n->pmr.cmse = false; 6647 6648 if (NVME_PMRMSCL_CMSE(data)) { 6649 uint64_t pmrmscu = ldl_le_p(&n->bar.pmrmscu); 6650 hwaddr cba = pmrmscu << 32 | 6651 (NVME_PMRMSCL_CBA(data) << PMRMSCL_CBA_SHIFT); 6652 if (cba + int128_get64(n->pmr.dev->mr.size) < cba) { 6653 NVME_PMRSTS_SET_CBAI(pmrsts, 1); 6654 stl_le_p(&n->bar.pmrsts, pmrsts); 6655 return; 6656 } 6657 6658 n->pmr.cmse = true; 6659 n->pmr.cba = cba; 6660 } 6661 6662 return; 6663 case NVME_REG_PMRMSCU: 6664 if (!NVME_CAP_PMRS(cap)) { 6665 return; 6666 } 6667 6668 stl_le_p(&n->bar.pmrmscu, data); 6669 return; 6670 default: 6671 NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, 6672 "invalid MMIO write," 6673 " offset=0x%"PRIx64", data=%"PRIx64"", 6674 offset, data); 6675 break; 6676 } 6677 } 6678 6679 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size) 6680 { 6681 NvmeCtrl *n = (NvmeCtrl *)opaque; 6682 uint8_t *ptr = (uint8_t *)&n->bar; 6683 6684 trace_pci_nvme_mmio_read(addr, size); 6685 6686 if (unlikely(addr & (sizeof(uint32_t) - 1))) { 6687 NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32, 6688 "MMIO read not 32-bit aligned," 6689 " offset=0x%"PRIx64"", addr); 6690 /* should RAZ, fall through for now */ 6691 } else if (unlikely(size < sizeof(uint32_t))) { 6692 NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall, 6693 "MMIO read smaller than 32-bits," 6694 " offset=0x%"PRIx64"", addr); 6695 /* should RAZ, fall through for now */ 6696 } 6697 6698 if (addr > sizeof(n->bar) - size) { 6699 NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs, 6700 "MMIO read beyond last register," 6701 " offset=0x%"PRIx64", returning 0", addr); 6702 6703 return 0; 6704 } 6705 6706 if (pci_is_vf(&n->parent_obj) && !nvme_sctrl(n)->scs && 6707 addr != NVME_REG_CSTS) { 6708 trace_pci_nvme_err_ignored_mmio_vf_offline(addr, size); 6709 return 0; 6710 } 6711 6712 /* 6713 * When PMRWBM bit 1 is set then read from 6714 * from PMRSTS should ensure prior writes 6715 * made it to persistent media 6716 */ 6717 if (addr == NVME_REG_PMRSTS && 6718 (NVME_PMRCAP_PMRWBM(ldl_le_p(&n->bar.pmrcap)) & 0x02)) { 6719 memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size); 6720 } 6721 6722 return ldn_le_p(ptr + addr, size); 6723 } 6724 6725 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) 6726 { 6727 uint32_t qid; 6728 6729 if (unlikely(addr & ((1 << 2) - 1))) { 6730 NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned, 6731 "doorbell write not 32-bit aligned," 6732 " offset=0x%"PRIx64", ignoring", addr); 6733 return; 6734 } 6735 6736 if (((addr - 0x1000) >> 2) & 1) { 6737 /* Completion queue doorbell write */ 6738 6739 uint16_t new_head = val & 0xffff; 6740 int start_sqs; 6741 NvmeCQueue *cq; 6742 6743 qid = (addr - (0x1000 + (1 << 2))) >> 3; 6744 if (unlikely(nvme_check_cqid(n, qid))) { 6745 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq, 6746 "completion queue doorbell write" 6747 " for nonexistent queue," 6748 " sqid=%"PRIu32", ignoring", qid); 6749 6750 /* 6751 * NVM Express v1.3d, Section 4.1 state: "If host software writes 6752 * an invalid value to the Submission Queue Tail Doorbell or 6753 * Completion Queue Head Doorbell regiter and an Asynchronous Event 6754 * Request command is outstanding, then an asynchronous event is 6755 * posted to the Admin Completion Queue with a status code of 6756 * Invalid Doorbell Write Value." 6757 * 6758 * Also note that the spec includes the "Invalid Doorbell Register" 6759 * status code, but nowhere does it specify when to use it. 6760 * However, it seems reasonable to use it here in a similar 6761 * fashion. 6762 */ 6763 if (n->outstanding_aers) { 6764 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR, 6765 NVME_AER_INFO_ERR_INVALID_DB_REGISTER, 6766 NVME_LOG_ERROR_INFO); 6767 } 6768 6769 return; 6770 } 6771 6772 cq = n->cq[qid]; 6773 if (unlikely(new_head >= cq->size)) { 6774 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead, 6775 "completion queue doorbell write value" 6776 " beyond queue size, sqid=%"PRIu32"," 6777 " new_head=%"PRIu16", ignoring", 6778 qid, new_head); 6779 6780 if (n->outstanding_aers) { 6781 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR, 6782 NVME_AER_INFO_ERR_INVALID_DB_VALUE, 6783 NVME_LOG_ERROR_INFO); 6784 } 6785 6786 return; 6787 } 6788 6789 trace_pci_nvme_mmio_doorbell_cq(cq->cqid, new_head); 6790 6791 start_sqs = nvme_cq_full(cq) ? 1 : 0; 6792 cq->head = new_head; 6793 if (!qid && n->dbbuf_enabled) { 6794 pci_dma_write(&n->parent_obj, cq->db_addr, &cq->head, 6795 sizeof(cq->head)); 6796 } 6797 if (start_sqs) { 6798 NvmeSQueue *sq; 6799 QTAILQ_FOREACH(sq, &cq->sq_list, entry) { 6800 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); 6801 } 6802 timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); 6803 } 6804 6805 if (cq->tail == cq->head) { 6806 if (cq->irq_enabled) { 6807 n->cq_pending--; 6808 } 6809 6810 nvme_irq_deassert(n, cq); 6811 } 6812 } else { 6813 /* Submission queue doorbell write */ 6814 6815 uint16_t new_tail = val & 0xffff; 6816 NvmeSQueue *sq; 6817 6818 qid = (addr - 0x1000) >> 3; 6819 if (unlikely(nvme_check_sqid(n, qid))) { 6820 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq, 6821 "submission queue doorbell write" 6822 " for nonexistent queue," 6823 " sqid=%"PRIu32", ignoring", qid); 6824 6825 if (n->outstanding_aers) { 6826 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR, 6827 NVME_AER_INFO_ERR_INVALID_DB_REGISTER, 6828 NVME_LOG_ERROR_INFO); 6829 } 6830 6831 return; 6832 } 6833 6834 sq = n->sq[qid]; 6835 if (unlikely(new_tail >= sq->size)) { 6836 NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail, 6837 "submission queue doorbell write value" 6838 " beyond queue size, sqid=%"PRIu32"," 6839 " new_tail=%"PRIu16", ignoring", 6840 qid, new_tail); 6841 6842 if (n->outstanding_aers) { 6843 nvme_enqueue_event(n, NVME_AER_TYPE_ERROR, 6844 NVME_AER_INFO_ERR_INVALID_DB_VALUE, 6845 NVME_LOG_ERROR_INFO); 6846 } 6847 6848 return; 6849 } 6850 6851 trace_pci_nvme_mmio_doorbell_sq(sq->sqid, new_tail); 6852 6853 sq->tail = new_tail; 6854 if (!qid && n->dbbuf_enabled) { 6855 /* 6856 * The spec states "the host shall also update the controller's 6857 * corresponding doorbell property to match the value of that entry 6858 * in the Shadow Doorbell buffer." 6859 * 6860 * Since this context is currently a VM trap, we can safely enforce 6861 * the requirement from the device side in case the host is 6862 * misbehaving. 6863 * 6864 * Note, we shouldn't have to do this, but various drivers 6865 * including ones that run on Linux, are not updating Admin Queues, 6866 * so we can't trust reading it for an appropriate sq tail. 6867 */ 6868 pci_dma_write(&n->parent_obj, sq->db_addr, &sq->tail, 6869 sizeof(sq->tail)); 6870 } 6871 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500); 6872 } 6873 } 6874 6875 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data, 6876 unsigned size) 6877 { 6878 NvmeCtrl *n = (NvmeCtrl *)opaque; 6879 6880 trace_pci_nvme_mmio_write(addr, data, size); 6881 6882 if (pci_is_vf(&n->parent_obj) && !nvme_sctrl(n)->scs && 6883 addr != NVME_REG_CSTS) { 6884 trace_pci_nvme_err_ignored_mmio_vf_offline(addr, size); 6885 return; 6886 } 6887 6888 if (addr < sizeof(n->bar)) { 6889 nvme_write_bar(n, addr, data, size); 6890 } else { 6891 nvme_process_db(n, addr, data); 6892 } 6893 } 6894 6895 static const MemoryRegionOps nvme_mmio_ops = { 6896 .read = nvme_mmio_read, 6897 .write = nvme_mmio_write, 6898 .endianness = DEVICE_LITTLE_ENDIAN, 6899 .impl = { 6900 .min_access_size = 2, 6901 .max_access_size = 8, 6902 }, 6903 }; 6904 6905 static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data, 6906 unsigned size) 6907 { 6908 NvmeCtrl *n = (NvmeCtrl *)opaque; 6909 stn_le_p(&n->cmb.buf[addr], size, data); 6910 } 6911 6912 static uint64_t nvme_cmb_read(void *opaque, hwaddr addr, unsigned size) 6913 { 6914 NvmeCtrl *n = (NvmeCtrl *)opaque; 6915 return ldn_le_p(&n->cmb.buf[addr], size); 6916 } 6917 6918 static const MemoryRegionOps nvme_cmb_ops = { 6919 .read = nvme_cmb_read, 6920 .write = nvme_cmb_write, 6921 .endianness = DEVICE_LITTLE_ENDIAN, 6922 .impl = { 6923 .min_access_size = 1, 6924 .max_access_size = 8, 6925 }, 6926 }; 6927 6928 static void nvme_check_constraints(NvmeCtrl *n, Error **errp) 6929 { 6930 NvmeParams *params = &n->params; 6931 6932 if (params->num_queues) { 6933 warn_report("num_queues is deprecated; please use max_ioqpairs " 6934 "instead"); 6935 6936 params->max_ioqpairs = params->num_queues - 1; 6937 } 6938 6939 if (n->namespace.blkconf.blk && n->subsys) { 6940 error_setg(errp, "subsystem support is unavailable with legacy " 6941 "namespace ('drive' property)"); 6942 return; 6943 } 6944 6945 if (params->max_ioqpairs < 1 || 6946 params->max_ioqpairs > NVME_MAX_IOQPAIRS) { 6947 error_setg(errp, "max_ioqpairs must be between 1 and %d", 6948 NVME_MAX_IOQPAIRS); 6949 return; 6950 } 6951 6952 if (params->msix_qsize < 1 || 6953 params->msix_qsize > PCI_MSIX_FLAGS_QSIZE + 1) { 6954 error_setg(errp, "msix_qsize must be between 1 and %d", 6955 PCI_MSIX_FLAGS_QSIZE + 1); 6956 return; 6957 } 6958 6959 if (!params->serial) { 6960 error_setg(errp, "serial property not set"); 6961 return; 6962 } 6963 6964 if (n->pmr.dev) { 6965 if (host_memory_backend_is_mapped(n->pmr.dev)) { 6966 error_setg(errp, "can't use already busy memdev: %s", 6967 object_get_canonical_path_component(OBJECT(n->pmr.dev))); 6968 return; 6969 } 6970 6971 if (!is_power_of_2(n->pmr.dev->size)) { 6972 error_setg(errp, "pmr backend size needs to be power of 2 in size"); 6973 return; 6974 } 6975 6976 host_memory_backend_set_mapped(n->pmr.dev, true); 6977 } 6978 6979 if (n->params.zasl > n->params.mdts) { 6980 error_setg(errp, "zoned.zasl (Zone Append Size Limit) must be less " 6981 "than or equal to mdts (Maximum Data Transfer Size)"); 6982 return; 6983 } 6984 6985 if (!n->params.vsl) { 6986 error_setg(errp, "vsl must be non-zero"); 6987 return; 6988 } 6989 6990 if (params->sriov_max_vfs) { 6991 if (!n->subsys) { 6992 error_setg(errp, "subsystem is required for the use of SR-IOV"); 6993 return; 6994 } 6995 6996 if (params->sriov_max_vfs > NVME_MAX_VFS) { 6997 error_setg(errp, "sriov_max_vfs must be between 0 and %d", 6998 NVME_MAX_VFS); 6999 return; 7000 } 7001 7002 if (params->cmb_size_mb) { 7003 error_setg(errp, "CMB is not supported with SR-IOV"); 7004 return; 7005 } 7006 7007 if (n->pmr.dev) { 7008 error_setg(errp, "PMR is not supported with SR-IOV"); 7009 return; 7010 } 7011 7012 if (!params->sriov_vq_flexible || !params->sriov_vi_flexible) { 7013 error_setg(errp, "both sriov_vq_flexible and sriov_vi_flexible" 7014 " must be set for the use of SR-IOV"); 7015 return; 7016 } 7017 7018 if (params->sriov_vq_flexible < params->sriov_max_vfs * 2) { 7019 error_setg(errp, "sriov_vq_flexible must be greater than or equal" 7020 " to %d (sriov_max_vfs * 2)", params->sriov_max_vfs * 2); 7021 return; 7022 } 7023 7024 if (params->max_ioqpairs < params->sriov_vq_flexible + 2) { 7025 error_setg(errp, "(max_ioqpairs - sriov_vq_flexible) must be" 7026 " greater than or equal to 2"); 7027 return; 7028 } 7029 7030 if (params->sriov_vi_flexible < params->sriov_max_vfs) { 7031 error_setg(errp, "sriov_vi_flexible must be greater than or equal" 7032 " to %d (sriov_max_vfs)", params->sriov_max_vfs); 7033 return; 7034 } 7035 7036 if (params->msix_qsize < params->sriov_vi_flexible + 1) { 7037 error_setg(errp, "(msix_qsize - sriov_vi_flexible) must be" 7038 " greater than or equal to 1"); 7039 return; 7040 } 7041 7042 if (params->sriov_max_vi_per_vf && 7043 (params->sriov_max_vi_per_vf - 1) % NVME_VF_RES_GRANULARITY) { 7044 error_setg(errp, "sriov_max_vi_per_vf must meet:" 7045 " (sriov_max_vi_per_vf - 1) %% %d == 0 and" 7046 " sriov_max_vi_per_vf >= 1", NVME_VF_RES_GRANULARITY); 7047 return; 7048 } 7049 7050 if (params->sriov_max_vq_per_vf && 7051 (params->sriov_max_vq_per_vf < 2 || 7052 (params->sriov_max_vq_per_vf - 1) % NVME_VF_RES_GRANULARITY)) { 7053 error_setg(errp, "sriov_max_vq_per_vf must meet:" 7054 " (sriov_max_vq_per_vf - 1) %% %d == 0 and" 7055 " sriov_max_vq_per_vf >= 2", NVME_VF_RES_GRANULARITY); 7056 return; 7057 } 7058 } 7059 } 7060 7061 static void nvme_init_state(NvmeCtrl *n) 7062 { 7063 NvmePriCtrlCap *cap = &n->pri_ctrl_cap; 7064 NvmeSecCtrlList *list = &n->sec_ctrl_list; 7065 NvmeSecCtrlEntry *sctrl; 7066 uint8_t max_vfs; 7067 int i; 7068 7069 if (pci_is_vf(&n->parent_obj)) { 7070 sctrl = nvme_sctrl(n); 7071 max_vfs = 0; 7072 n->conf_ioqpairs = sctrl->nvq ? le16_to_cpu(sctrl->nvq) - 1 : 0; 7073 n->conf_msix_qsize = sctrl->nvi ? le16_to_cpu(sctrl->nvi) : 1; 7074 } else { 7075 max_vfs = n->params.sriov_max_vfs; 7076 n->conf_ioqpairs = n->params.max_ioqpairs; 7077 n->conf_msix_qsize = n->params.msix_qsize; 7078 } 7079 7080 n->sq = g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); 7081 n->cq = g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); 7082 n->temperature = NVME_TEMPERATURE; 7083 n->features.temp_thresh_hi = NVME_TEMPERATURE_WARNING; 7084 n->starttime_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); 7085 n->aer_reqs = g_new0(NvmeRequest *, n->params.aerl + 1); 7086 QTAILQ_INIT(&n->aer_queue); 7087 7088 list->numcntl = cpu_to_le16(max_vfs); 7089 for (i = 0; i < max_vfs; i++) { 7090 sctrl = &list->sec[i]; 7091 sctrl->pcid = cpu_to_le16(n->cntlid); 7092 sctrl->vfn = cpu_to_le16(i + 1); 7093 } 7094 7095 cap->cntlid = cpu_to_le16(n->cntlid); 7096 cap->crt = NVME_CRT_VQ | NVME_CRT_VI; 7097 7098 if (pci_is_vf(&n->parent_obj)) { 7099 cap->vqprt = cpu_to_le16(1 + n->conf_ioqpairs); 7100 } else { 7101 cap->vqprt = cpu_to_le16(1 + n->params.max_ioqpairs - 7102 n->params.sriov_vq_flexible); 7103 cap->vqfrt = cpu_to_le32(n->params.sriov_vq_flexible); 7104 cap->vqrfap = cap->vqfrt; 7105 cap->vqgran = cpu_to_le16(NVME_VF_RES_GRANULARITY); 7106 cap->vqfrsm = n->params.sriov_max_vq_per_vf ? 7107 cpu_to_le16(n->params.sriov_max_vq_per_vf) : 7108 cap->vqfrt / MAX(max_vfs, 1); 7109 } 7110 7111 if (pci_is_vf(&n->parent_obj)) { 7112 cap->viprt = cpu_to_le16(n->conf_msix_qsize); 7113 } else { 7114 cap->viprt = cpu_to_le16(n->params.msix_qsize - 7115 n->params.sriov_vi_flexible); 7116 cap->vifrt = cpu_to_le32(n->params.sriov_vi_flexible); 7117 cap->virfap = cap->vifrt; 7118 cap->vigran = cpu_to_le16(NVME_VF_RES_GRANULARITY); 7119 cap->vifrsm = n->params.sriov_max_vi_per_vf ? 7120 cpu_to_le16(n->params.sriov_max_vi_per_vf) : 7121 cap->vifrt / MAX(max_vfs, 1); 7122 } 7123 } 7124 7125 static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) 7126 { 7127 uint64_t cmb_size = n->params.cmb_size_mb * MiB; 7128 uint64_t cap = ldq_le_p(&n->bar.cap); 7129 7130 n->cmb.buf = g_malloc0(cmb_size); 7131 memory_region_init_io(&n->cmb.mem, OBJECT(n), &nvme_cmb_ops, n, 7132 "nvme-cmb", cmb_size); 7133 pci_register_bar(pci_dev, NVME_CMB_BIR, 7134 PCI_BASE_ADDRESS_SPACE_MEMORY | 7135 PCI_BASE_ADDRESS_MEM_TYPE_64 | 7136 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->cmb.mem); 7137 7138 NVME_CAP_SET_CMBS(cap, 1); 7139 stq_le_p(&n->bar.cap, cap); 7140 7141 if (n->params.legacy_cmb) { 7142 nvme_cmb_enable_regs(n); 7143 n->cmb.cmse = true; 7144 } 7145 } 7146 7147 static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev) 7148 { 7149 uint32_t pmrcap = ldl_le_p(&n->bar.pmrcap); 7150 7151 NVME_PMRCAP_SET_RDS(pmrcap, 1); 7152 NVME_PMRCAP_SET_WDS(pmrcap, 1); 7153 NVME_PMRCAP_SET_BIR(pmrcap, NVME_PMR_BIR); 7154 /* Turn on bit 1 support */ 7155 NVME_PMRCAP_SET_PMRWBM(pmrcap, 0x02); 7156 NVME_PMRCAP_SET_CMSS(pmrcap, 1); 7157 stl_le_p(&n->bar.pmrcap, pmrcap); 7158 7159 pci_register_bar(pci_dev, NVME_PMR_BIR, 7160 PCI_BASE_ADDRESS_SPACE_MEMORY | 7161 PCI_BASE_ADDRESS_MEM_TYPE_64 | 7162 PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmr.dev->mr); 7163 7164 memory_region_set_enabled(&n->pmr.dev->mr, false); 7165 } 7166 7167 static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs, 7168 unsigned *msix_table_offset, 7169 unsigned *msix_pba_offset) 7170 { 7171 uint64_t bar_size, msix_table_size, msix_pba_size; 7172 7173 bar_size = sizeof(NvmeBar) + 2 * total_queues * NVME_DB_SIZE; 7174 bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB); 7175 7176 if (msix_table_offset) { 7177 *msix_table_offset = bar_size; 7178 } 7179 7180 msix_table_size = PCI_MSIX_ENTRY_SIZE * total_irqs; 7181 bar_size += msix_table_size; 7182 bar_size = QEMU_ALIGN_UP(bar_size, 4 * KiB); 7183 7184 if (msix_pba_offset) { 7185 *msix_pba_offset = bar_size; 7186 } 7187 7188 msix_pba_size = QEMU_ALIGN_UP(total_irqs, 64) / 8; 7189 bar_size += msix_pba_size; 7190 7191 bar_size = pow2ceil(bar_size); 7192 return bar_size; 7193 } 7194 7195 static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset) 7196 { 7197 uint16_t vf_dev_id = n->params.use_intel_id ? 7198 PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME; 7199 NvmePriCtrlCap *cap = &n->pri_ctrl_cap; 7200 uint64_t bar_size = nvme_bar_size(le16_to_cpu(cap->vqfrsm), 7201 le16_to_cpu(cap->vifrsm), 7202 NULL, NULL); 7203 7204 pcie_sriov_pf_init(pci_dev, offset, "nvme", vf_dev_id, 7205 n->params.sriov_max_vfs, n->params.sriov_max_vfs, 7206 NVME_VF_OFFSET, NVME_VF_STRIDE); 7207 7208 pcie_sriov_pf_init_vf_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | 7209 PCI_BASE_ADDRESS_MEM_TYPE_64, bar_size); 7210 } 7211 7212 static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset) 7213 { 7214 Error *err = NULL; 7215 int ret; 7216 7217 ret = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, 7218 PCI_PM_SIZEOF, &err); 7219 if (err) { 7220 error_report_err(err); 7221 return ret; 7222 } 7223 7224 pci_set_word(pci_dev->config + offset + PCI_PM_PMC, 7225 PCI_PM_CAP_VER_1_2); 7226 pci_set_word(pci_dev->config + offset + PCI_PM_CTRL, 7227 PCI_PM_CTRL_NO_SOFT_RESET); 7228 pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, 7229 PCI_PM_CTRL_STATE_MASK); 7230 7231 return 0; 7232 } 7233 7234 static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp) 7235 { 7236 uint8_t *pci_conf = pci_dev->config; 7237 uint64_t bar_size; 7238 unsigned msix_table_offset, msix_pba_offset; 7239 int ret; 7240 7241 Error *err = NULL; 7242 7243 pci_conf[PCI_INTERRUPT_PIN] = 1; 7244 pci_config_set_prog_interface(pci_conf, 0x2); 7245 7246 if (n->params.use_intel_id) { 7247 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); 7248 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_NVME); 7249 } else { 7250 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT); 7251 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REDHAT_NVME); 7252 } 7253 7254 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); 7255 nvme_add_pm_capability(pci_dev, 0x60); 7256 pcie_endpoint_cap_init(pci_dev, 0x80); 7257 pcie_cap_flr_init(pci_dev); 7258 if (n->params.sriov_max_vfs) { 7259 pcie_ari_init(pci_dev, 0x100, 1); 7260 } 7261 7262 /* add one to max_ioqpairs to account for the admin queue pair */ 7263 bar_size = nvme_bar_size(n->params.max_ioqpairs + 1, n->params.msix_qsize, 7264 &msix_table_offset, &msix_pba_offset); 7265 7266 memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); 7267 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", 7268 msix_table_offset); 7269 memory_region_add_subregion(&n->bar0, 0, &n->iomem); 7270 7271 if (pci_is_vf(pci_dev)) { 7272 pcie_sriov_vf_register_bar(pci_dev, 0, &n->bar0); 7273 } else { 7274 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | 7275 PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0); 7276 } 7277 ret = msix_init(pci_dev, n->params.msix_qsize, 7278 &n->bar0, 0, msix_table_offset, 7279 &n->bar0, 0, msix_pba_offset, 0, &err); 7280 if (ret < 0) { 7281 if (ret == -ENOTSUP) { 7282 warn_report_err(err); 7283 } else { 7284 error_propagate(errp, err); 7285 return ret; 7286 } 7287 } 7288 7289 nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize); 7290 7291 if (n->params.cmb_size_mb) { 7292 nvme_init_cmb(n, pci_dev); 7293 } 7294 7295 if (n->pmr.dev) { 7296 nvme_init_pmr(n, pci_dev); 7297 } 7298 7299 if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) { 7300 nvme_init_sriov(n, pci_dev, 0x120); 7301 } 7302 7303 return 0; 7304 } 7305 7306 static void nvme_init_subnqn(NvmeCtrl *n) 7307 { 7308 NvmeSubsystem *subsys = n->subsys; 7309 NvmeIdCtrl *id = &n->id_ctrl; 7310 7311 if (!subsys) { 7312 snprintf((char *)id->subnqn, sizeof(id->subnqn), 7313 "nqn.2019-08.org.qemu:%s", n->params.serial); 7314 } else { 7315 pstrcpy((char *)id->subnqn, sizeof(id->subnqn), (char*)subsys->subnqn); 7316 } 7317 } 7318 7319 static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) 7320 { 7321 NvmeIdCtrl *id = &n->id_ctrl; 7322 uint8_t *pci_conf = pci_dev->config; 7323 uint64_t cap = ldq_le_p(&n->bar.cap); 7324 NvmeSecCtrlEntry *sctrl = nvme_sctrl(n); 7325 7326 id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); 7327 id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID)); 7328 strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); 7329 strpadcpy((char *)id->fr, sizeof(id->fr), QEMU_VERSION, ' '); 7330 strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' '); 7331 7332 id->cntlid = cpu_to_le16(n->cntlid); 7333 7334 id->oaes = cpu_to_le32(NVME_OAES_NS_ATTR); 7335 id->ctratt |= cpu_to_le32(NVME_CTRATT_ELBAS); 7336 7337 id->rab = 6; 7338 7339 if (n->params.use_intel_id) { 7340 id->ieee[0] = 0xb3; 7341 id->ieee[1] = 0x02; 7342 id->ieee[2] = 0x00; 7343 } else { 7344 id->ieee[0] = 0x00; 7345 id->ieee[1] = 0x54; 7346 id->ieee[2] = 0x52; 7347 } 7348 7349 id->mdts = n->params.mdts; 7350 id->ver = cpu_to_le32(NVME_SPEC_VER); 7351 id->oacs = 7352 cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT | NVME_OACS_DBBUF); 7353 id->cntrltype = 0x1; 7354 7355 /* 7356 * Because the controller always completes the Abort command immediately, 7357 * there can never be more than one concurrently executing Abort command, 7358 * so this value is never used for anything. Note that there can easily be 7359 * many Abort commands in the queues, but they are not considered 7360 * "executing" until processed by nvme_abort. 7361 * 7362 * The specification recommends a value of 3 for Abort Command Limit (four 7363 * concurrently outstanding Abort commands), so lets use that though it is 7364 * inconsequential. 7365 */ 7366 id->acl = 3; 7367 id->aerl = n->params.aerl; 7368 id->frmw = (NVME_NUM_FW_SLOTS << 1) | NVME_FRMW_SLOT1_RO; 7369 id->lpa = NVME_LPA_NS_SMART | NVME_LPA_CSE | NVME_LPA_EXTENDED; 7370 7371 /* recommended default value (~70 C) */ 7372 id->wctemp = cpu_to_le16(NVME_TEMPERATURE_WARNING); 7373 id->cctemp = cpu_to_le16(NVME_TEMPERATURE_CRITICAL); 7374 7375 id->sqes = (0x6 << 4) | 0x6; 7376 id->cqes = (0x4 << 4) | 0x4; 7377 id->nn = cpu_to_le32(NVME_MAX_NAMESPACES); 7378 id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP | 7379 NVME_ONCS_FEATURES | NVME_ONCS_DSM | 7380 NVME_ONCS_COMPARE | NVME_ONCS_COPY); 7381 7382 /* 7383 * NOTE: If this device ever supports a command set that does NOT use 0x0 7384 * as a Flush-equivalent operation, support for the broadcast NSID in Flush 7385 * should probably be removed. 7386 * 7387 * See comment in nvme_io_cmd. 7388 */ 7389 id->vwc = NVME_VWC_NSID_BROADCAST_SUPPORT | NVME_VWC_PRESENT; 7390 7391 id->ocfs = cpu_to_le16(NVME_OCFS_COPY_FORMAT_0 | NVME_OCFS_COPY_FORMAT_1); 7392 id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN); 7393 7394 nvme_init_subnqn(n); 7395 7396 id->psd[0].mp = cpu_to_le16(0x9c4); 7397 id->psd[0].enlat = cpu_to_le32(0x10); 7398 id->psd[0].exlat = cpu_to_le32(0x4); 7399 7400 if (n->subsys) { 7401 id->cmic |= NVME_CMIC_MULTI_CTRL; 7402 } 7403 7404 NVME_CAP_SET_MQES(cap, 0x7ff); 7405 NVME_CAP_SET_CQR(cap, 1); 7406 NVME_CAP_SET_TO(cap, 0xf); 7407 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_NVM); 7408 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_CSI_SUPP); 7409 NVME_CAP_SET_CSS(cap, NVME_CAP_CSS_ADMIN_ONLY); 7410 NVME_CAP_SET_MPSMAX(cap, 4); 7411 NVME_CAP_SET_CMBS(cap, n->params.cmb_size_mb ? 1 : 0); 7412 NVME_CAP_SET_PMRS(cap, n->pmr.dev ? 1 : 0); 7413 stq_le_p(&n->bar.cap, cap); 7414 7415 stl_le_p(&n->bar.vs, NVME_SPEC_VER); 7416 n->bar.intmc = n->bar.intms = 0; 7417 7418 if (pci_is_vf(&n->parent_obj) && !sctrl->scs) { 7419 stl_le_p(&n->bar.csts, NVME_CSTS_FAILED); 7420 } 7421 } 7422 7423 static int nvme_init_subsys(NvmeCtrl *n, Error **errp) 7424 { 7425 int cntlid; 7426 7427 if (!n->subsys) { 7428 return 0; 7429 } 7430 7431 cntlid = nvme_subsys_register_ctrl(n, errp); 7432 if (cntlid < 0) { 7433 return -1; 7434 } 7435 7436 n->cntlid = cntlid; 7437 7438 return 0; 7439 } 7440 7441 void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns) 7442 { 7443 uint32_t nsid = ns->params.nsid; 7444 assert(nsid && nsid <= NVME_MAX_NAMESPACES); 7445 7446 n->namespaces[nsid] = ns; 7447 ns->attached++; 7448 7449 n->dmrsl = MIN_NON_ZERO(n->dmrsl, 7450 BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1)); 7451 } 7452 7453 static void nvme_realize(PCIDevice *pci_dev, Error **errp) 7454 { 7455 NvmeCtrl *n = NVME(pci_dev); 7456 NvmeNamespace *ns; 7457 Error *local_err = NULL; 7458 NvmeCtrl *pn = NVME(pcie_sriov_get_pf(pci_dev)); 7459 7460 if (pci_is_vf(pci_dev)) { 7461 /* 7462 * VFs derive settings from the parent. PF's lifespan exceeds 7463 * that of VF's, so it's safe to share params.serial. 7464 */ 7465 memcpy(&n->params, &pn->params, sizeof(NvmeParams)); 7466 n->subsys = pn->subsys; 7467 } 7468 7469 nvme_check_constraints(n, &local_err); 7470 if (local_err) { 7471 error_propagate(errp, local_err); 7472 return; 7473 } 7474 7475 qbus_init(&n->bus, sizeof(NvmeBus), TYPE_NVME_BUS, 7476 &pci_dev->qdev, n->parent_obj.qdev.id); 7477 7478 if (nvme_init_subsys(n, errp)) { 7479 error_propagate(errp, local_err); 7480 return; 7481 } 7482 nvme_init_state(n); 7483 if (nvme_init_pci(n, pci_dev, errp)) { 7484 return; 7485 } 7486 nvme_init_ctrl(n, pci_dev); 7487 7488 /* setup a namespace if the controller drive property was given */ 7489 if (n->namespace.blkconf.blk) { 7490 ns = &n->namespace; 7491 ns->params.nsid = 1; 7492 7493 if (nvme_ns_setup(ns, errp)) { 7494 return; 7495 } 7496 7497 nvme_attach_ns(n, ns); 7498 } 7499 } 7500 7501 static void nvme_exit(PCIDevice *pci_dev) 7502 { 7503 NvmeCtrl *n = NVME(pci_dev); 7504 NvmeNamespace *ns; 7505 int i; 7506 7507 nvme_ctrl_reset(n, NVME_RESET_FUNCTION); 7508 7509 if (n->subsys) { 7510 for (i = 1; i <= NVME_MAX_NAMESPACES; i++) { 7511 ns = nvme_ns(n, i); 7512 if (ns) { 7513 ns->attached--; 7514 } 7515 } 7516 7517 nvme_subsys_unregister_ctrl(n->subsys, n); 7518 } 7519 7520 g_free(n->cq); 7521 g_free(n->sq); 7522 g_free(n->aer_reqs); 7523 7524 if (n->params.cmb_size_mb) { 7525 g_free(n->cmb.buf); 7526 } 7527 7528 if (n->pmr.dev) { 7529 host_memory_backend_set_mapped(n->pmr.dev, false); 7530 } 7531 7532 if (!pci_is_vf(pci_dev) && n->params.sriov_max_vfs) { 7533 pcie_sriov_pf_exit(pci_dev); 7534 } 7535 7536 msix_uninit(pci_dev, &n->bar0, &n->bar0); 7537 memory_region_del_subregion(&n->bar0, &n->iomem); 7538 } 7539 7540 static Property nvme_props[] = { 7541 DEFINE_BLOCK_PROPERTIES(NvmeCtrl, namespace.blkconf), 7542 DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmr.dev, TYPE_MEMORY_BACKEND, 7543 HostMemoryBackend *), 7544 DEFINE_PROP_LINK("subsys", NvmeCtrl, subsys, TYPE_NVME_SUBSYS, 7545 NvmeSubsystem *), 7546 DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial), 7547 DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0), 7548 DEFINE_PROP_UINT32("num_queues", NvmeCtrl, params.num_queues, 0), 7549 DEFINE_PROP_UINT32("max_ioqpairs", NvmeCtrl, params.max_ioqpairs, 64), 7550 DEFINE_PROP_UINT16("msix_qsize", NvmeCtrl, params.msix_qsize, 65), 7551 DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3), 7552 DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64), 7553 DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7), 7554 DEFINE_PROP_UINT8("vsl", NvmeCtrl, params.vsl, 7), 7555 DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false), 7556 DEFINE_PROP_BOOL("legacy-cmb", NvmeCtrl, params.legacy_cmb, false), 7557 DEFINE_PROP_UINT8("zoned.zasl", NvmeCtrl, params.zasl, 0), 7558 DEFINE_PROP_BOOL("zoned.auto_transition", NvmeCtrl, 7559 params.auto_transition_zones, true), 7560 DEFINE_PROP_UINT8("sriov_max_vfs", NvmeCtrl, params.sriov_max_vfs, 0), 7561 DEFINE_PROP_UINT16("sriov_vq_flexible", NvmeCtrl, 7562 params.sriov_vq_flexible, 0), 7563 DEFINE_PROP_UINT16("sriov_vi_flexible", NvmeCtrl, 7564 params.sriov_vi_flexible, 0), 7565 DEFINE_PROP_UINT8("sriov_max_vi_per_vf", NvmeCtrl, 7566 params.sriov_max_vi_per_vf, 0), 7567 DEFINE_PROP_UINT8("sriov_max_vq_per_vf", NvmeCtrl, 7568 params.sriov_max_vq_per_vf, 0), 7569 DEFINE_PROP_END_OF_LIST(), 7570 }; 7571 7572 static void nvme_get_smart_warning(Object *obj, Visitor *v, const char *name, 7573 void *opaque, Error **errp) 7574 { 7575 NvmeCtrl *n = NVME(obj); 7576 uint8_t value = n->smart_critical_warning; 7577 7578 visit_type_uint8(v, name, &value, errp); 7579 } 7580 7581 static void nvme_set_smart_warning(Object *obj, Visitor *v, const char *name, 7582 void *opaque, Error **errp) 7583 { 7584 NvmeCtrl *n = NVME(obj); 7585 uint8_t value, old_value, cap = 0, index, event; 7586 7587 if (!visit_type_uint8(v, name, &value, errp)) { 7588 return; 7589 } 7590 7591 cap = NVME_SMART_SPARE | NVME_SMART_TEMPERATURE | NVME_SMART_RELIABILITY 7592 | NVME_SMART_MEDIA_READ_ONLY | NVME_SMART_FAILED_VOLATILE_MEDIA; 7593 if (NVME_CAP_PMRS(ldq_le_p(&n->bar.cap))) { 7594 cap |= NVME_SMART_PMR_UNRELIABLE; 7595 } 7596 7597 if ((value & cap) != value) { 7598 error_setg(errp, "unsupported smart critical warning bits: 0x%x", 7599 value & ~cap); 7600 return; 7601 } 7602 7603 old_value = n->smart_critical_warning; 7604 n->smart_critical_warning = value; 7605 7606 /* only inject new bits of smart critical warning */ 7607 for (index = 0; index < NVME_SMART_WARN_MAX; index++) { 7608 event = 1 << index; 7609 if (value & ~old_value & event) 7610 nvme_smart_event(n, event); 7611 } 7612 } 7613 7614 static void nvme_pci_reset(DeviceState *qdev) 7615 { 7616 PCIDevice *pci_dev = PCI_DEVICE(qdev); 7617 NvmeCtrl *n = NVME(pci_dev); 7618 7619 trace_pci_nvme_pci_reset(); 7620 nvme_ctrl_reset(n, NVME_RESET_FUNCTION); 7621 } 7622 7623 static void nvme_sriov_pre_write_ctrl(PCIDevice *dev, uint32_t address, 7624 uint32_t val, int len) 7625 { 7626 NvmeCtrl *n = NVME(dev); 7627 NvmeSecCtrlEntry *sctrl; 7628 uint16_t sriov_cap = dev->exp.sriov_cap; 7629 uint32_t off = address - sriov_cap; 7630 int i, num_vfs; 7631 7632 if (!sriov_cap) { 7633 return; 7634 } 7635 7636 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 7637 if (!(val & PCI_SRIOV_CTRL_VFE)) { 7638 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 7639 for (i = 0; i < num_vfs; i++) { 7640 sctrl = &n->sec_ctrl_list.sec[i]; 7641 nvme_virt_set_state(n, le16_to_cpu(sctrl->scid), false); 7642 } 7643 } 7644 } 7645 } 7646 7647 static void nvme_pci_write_config(PCIDevice *dev, uint32_t address, 7648 uint32_t val, int len) 7649 { 7650 nvme_sriov_pre_write_ctrl(dev, address, val, len); 7651 pci_default_write_config(dev, address, val, len); 7652 pcie_cap_flr_write_config(dev, address, val, len); 7653 } 7654 7655 static const VMStateDescription nvme_vmstate = { 7656 .name = "nvme", 7657 .unmigratable = 1, 7658 }; 7659 7660 static void nvme_class_init(ObjectClass *oc, void *data) 7661 { 7662 DeviceClass *dc = DEVICE_CLASS(oc); 7663 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); 7664 7665 pc->realize = nvme_realize; 7666 pc->config_write = nvme_pci_write_config; 7667 pc->exit = nvme_exit; 7668 pc->class_id = PCI_CLASS_STORAGE_EXPRESS; 7669 pc->revision = 2; 7670 7671 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 7672 dc->desc = "Non-Volatile Memory Express"; 7673 device_class_set_props(dc, nvme_props); 7674 dc->vmsd = &nvme_vmstate; 7675 dc->reset = nvme_pci_reset; 7676 } 7677 7678 static void nvme_instance_init(Object *obj) 7679 { 7680 NvmeCtrl *n = NVME(obj); 7681 7682 device_add_bootindex_property(obj, &n->namespace.blkconf.bootindex, 7683 "bootindex", "/namespace@1,0", 7684 DEVICE(obj)); 7685 7686 object_property_add(obj, "smart_critical_warning", "uint8", 7687 nvme_get_smart_warning, 7688 nvme_set_smart_warning, NULL, NULL); 7689 } 7690 7691 static const TypeInfo nvme_info = { 7692 .name = TYPE_NVME, 7693 .parent = TYPE_PCI_DEVICE, 7694 .instance_size = sizeof(NvmeCtrl), 7695 .instance_init = nvme_instance_init, 7696 .class_init = nvme_class_init, 7697 .interfaces = (InterfaceInfo[]) { 7698 { INTERFACE_PCIE_DEVICE }, 7699 { } 7700 }, 7701 }; 7702 7703 static const TypeInfo nvme_bus_info = { 7704 .name = TYPE_NVME_BUS, 7705 .parent = TYPE_BUS, 7706 .instance_size = sizeof(NvmeBus), 7707 }; 7708 7709 static void nvme_register_types(void) 7710 { 7711 type_register_static(&nvme_info); 7712 type_register_static(&nvme_bus_info); 7713 } 7714 7715 type_init(nvme_register_types) 7716