1 /* 2 * QEMU model of the Xilinx Ethernet Lite MAC. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias. 5 * 6 * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite 7 * LogiCORE IP XPS Ethernet Lite Media Access Controller 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/module.h" 30 #include "qom/object.h" 31 #include "exec/tswap.h" 32 #include "hw/sysbus.h" 33 #include "hw/irq.h" 34 #include "hw/qdev-properties.h" 35 #include "net/net.h" 36 #include "trace.h" 37 38 #define R_TX_BUF0 0 39 #define BUFSZ_MAX 0x07e4 40 #define R_TX_LEN0 (0x07f4 / 4) 41 #define R_TX_GIE0 (0x07f8 / 4) 42 #define R_TX_CTRL0 (0x07fc / 4) 43 #define R_TX_BUF1 (0x0800 / 4) 44 #define R_TX_LEN1 (0x0ff4 / 4) 45 #define R_TX_CTRL1 (0x0ffc / 4) 46 47 #define R_RX_BUF0 (0x1000 / 4) 48 #define R_RX_CTRL0 (0x17fc / 4) 49 #define R_RX_BUF1 (0x1800 / 4) 50 #define R_RX_CTRL1 (0x1ffc / 4) 51 #define R_MAX (0x2000 / 4) 52 53 #define GIE_GIE 0x80000000 54 55 #define CTRL_I 0x8 56 #define CTRL_P 0x2 57 #define CTRL_S 0x1 58 59 #define TYPE_XILINX_ETHLITE "xlnx.xps-ethernetlite" 60 OBJECT_DECLARE_SIMPLE_TYPE(XlnxXpsEthLite, XILINX_ETHLITE) 61 62 struct XlnxXpsEthLite 63 { 64 SysBusDevice parent_obj; 65 66 MemoryRegion mmio; 67 qemu_irq irq; 68 NICState *nic; 69 NICConf conf; 70 71 uint32_t c_tx_pingpong; 72 uint32_t c_rx_pingpong; 73 unsigned int port_index; /* dual port RAM index */ 74 75 uint32_t regs[R_MAX]; 76 }; 77 78 static inline void eth_pulse_irq(XlnxXpsEthLite *s) 79 { 80 /* Only the first gie reg is active. */ 81 if (s->regs[R_TX_GIE0] & GIE_GIE) { 82 qemu_irq_pulse(s->irq); 83 } 84 } 85 86 static uint64_t 87 eth_read(void *opaque, hwaddr addr, unsigned int size) 88 { 89 XlnxXpsEthLite *s = opaque; 90 uint32_t r = 0; 91 92 addr >>= 2; 93 94 switch (addr) 95 { 96 case R_TX_GIE0: 97 case R_TX_LEN0: 98 case R_TX_LEN1: 99 case R_TX_CTRL1: 100 case R_TX_CTRL0: 101 case R_RX_CTRL1: 102 case R_RX_CTRL0: 103 r = s->regs[addr]; 104 break; 105 106 default: 107 r = tswap32(s->regs[addr]); 108 break; 109 } 110 return r; 111 } 112 113 static void 114 eth_write(void *opaque, hwaddr addr, 115 uint64_t val64, unsigned int size) 116 { 117 XlnxXpsEthLite *s = opaque; 118 unsigned int base = 0; 119 uint32_t value = val64; 120 121 addr >>= 2; 122 switch (addr) 123 { 124 case R_TX_CTRL0: 125 case R_TX_CTRL1: 126 if (addr == R_TX_CTRL1) 127 base = 0x800 / 4; 128 129 if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { 130 qemu_send_packet(qemu_get_queue(s->nic), 131 (void *) &s->regs[base], 132 s->regs[base + R_TX_LEN0]); 133 if (s->regs[base + R_TX_CTRL0] & CTRL_I) 134 eth_pulse_irq(s); 135 } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { 136 memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6); 137 if (s->regs[base + R_TX_CTRL0] & CTRL_I) 138 eth_pulse_irq(s); 139 } 140 141 /* We are fast and get ready pretty much immediately so 142 we actually never flip the S nor P bits to one. */ 143 s->regs[addr] = value & ~(CTRL_P | CTRL_S); 144 break; 145 146 /* Keep these native. */ 147 case R_RX_CTRL0: 148 case R_RX_CTRL1: 149 if (!(value & CTRL_S)) { 150 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 151 } 152 /* fall through */ 153 case R_TX_LEN0: 154 case R_TX_LEN1: 155 case R_TX_GIE0: 156 s->regs[addr] = value; 157 break; 158 159 default: 160 s->regs[addr] = tswap32(value); 161 break; 162 } 163 } 164 165 static const MemoryRegionOps eth_ops = { 166 .read = eth_read, 167 .write = eth_write, 168 .endianness = DEVICE_NATIVE_ENDIAN, 169 .valid = { 170 .min_access_size = 4, 171 .max_access_size = 4 172 } 173 }; 174 175 static bool eth_can_rx(NetClientState *nc) 176 { 177 XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); 178 unsigned int rxbase = s->port_index * (0x800 / 4); 179 180 return !(s->regs[rxbase + R_RX_CTRL0] & CTRL_S); 181 } 182 183 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size) 184 { 185 XlnxXpsEthLite *s = qemu_get_nic_opaque(nc); 186 unsigned int rxbase = s->port_index * (0x800 / 4); 187 188 /* DA filter. */ 189 if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6)) 190 return size; 191 192 if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) { 193 trace_ethlite_pkt_lost(s->regs[R_RX_CTRL0]); 194 return -1; 195 } 196 197 if (size >= BUFSZ_MAX) { 198 trace_ethlite_pkt_size_too_big(size); 199 return -1; 200 } 201 memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size); 202 203 s->regs[rxbase + R_RX_CTRL0] |= CTRL_S; 204 if (s->regs[R_RX_CTRL0] & CTRL_I) { 205 eth_pulse_irq(s); 206 } 207 208 /* If c_rx_pingpong was set flip buffers. */ 209 s->port_index ^= s->c_rx_pingpong; 210 return size; 211 } 212 213 static void xilinx_ethlite_reset(DeviceState *dev) 214 { 215 XlnxXpsEthLite *s = XILINX_ETHLITE(dev); 216 217 s->port_index = 0; 218 } 219 220 static NetClientInfo net_xilinx_ethlite_info = { 221 .type = NET_CLIENT_DRIVER_NIC, 222 .size = sizeof(NICState), 223 .can_receive = eth_can_rx, 224 .receive = eth_rx, 225 }; 226 227 static void xilinx_ethlite_realize(DeviceState *dev, Error **errp) 228 { 229 XlnxXpsEthLite *s = XILINX_ETHLITE(dev); 230 231 qemu_macaddr_default_if_unset(&s->conf.macaddr); 232 s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, 233 object_get_typename(OBJECT(dev)), dev->id, 234 &dev->mem_reentrancy_guard, s); 235 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 236 } 237 238 static void xilinx_ethlite_init(Object *obj) 239 { 240 XlnxXpsEthLite *s = XILINX_ETHLITE(obj); 241 242 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 243 244 memory_region_init_io(&s->mmio, obj, ð_ops, s, 245 "xlnx.xps-ethernetlite", R_MAX * 4); 246 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 247 } 248 249 static const Property xilinx_ethlite_properties[] = { 250 DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1), 251 DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1), 252 DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf), 253 }; 254 255 static void xilinx_ethlite_class_init(ObjectClass *klass, void *data) 256 { 257 DeviceClass *dc = DEVICE_CLASS(klass); 258 259 dc->realize = xilinx_ethlite_realize; 260 device_class_set_legacy_reset(dc, xilinx_ethlite_reset); 261 device_class_set_props(dc, xilinx_ethlite_properties); 262 } 263 264 static const TypeInfo xilinx_ethlite_types[] = { 265 { 266 .name = TYPE_XILINX_ETHLITE, 267 .parent = TYPE_SYS_BUS_DEVICE, 268 .instance_size = sizeof(XlnxXpsEthLite), 269 .instance_init = xilinx_ethlite_init, 270 .class_init = xilinx_ethlite_class_init, 271 }, 272 }; 273 274 DEFINE_TYPES(xilinx_ethlite_types) 275