1 /** 2 * QEMU RTL8139 emulation 3 * 4 * Copyright (c) 2006 Igor Kovalenko 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 24 * Modifications: 25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) 26 * 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver 28 * HW revision ID changes for FreeBSD driver 29 * 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver 31 * Corrected packet transfer reassembly routine for 8139C+ mode 32 * Rearranged debugging print statements 33 * Implemented PCI timer interrupt (disabled by default) 34 * Implemented Tally Counters, increased VM load/save version 35 * Implemented IP/TCP/UDP checksum task offloading 36 * 37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading 38 * Fixed MTU=1500 for produced ethernet frames 39 * 40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing 41 * segmentation offloading 42 * Removed slirp.h dependency 43 * Added rx/tx buffer reset when enabling rx/tx operation 44 * 45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only 46 * when strictly needed (required for for 47 * Darwin) 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading 49 */ 50 51 /* For crc32 */ 52 #include <zlib.h> 53 54 #include "hw.h" 55 #include "pci.h" 56 #include "dma.h" 57 #include "qemu-timer.h" 58 #include "net.h" 59 #include "loader.h" 60 #include "sysemu.h" 61 #include "iov.h" 62 63 /* debug RTL8139 card */ 64 //#define DEBUG_RTL8139 1 65 66 #define PCI_FREQUENCY 33000000L 67 68 /* debug RTL8139 card C+ mode only */ 69 //#define DEBUG_RTL8139CP 1 70 71 #define SET_MASKED(input, mask, curr) \ 72 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) 73 74 /* arg % size for size which is a power of 2 */ 75 #define MOD2(input, size) \ 76 ( ( input ) & ( size - 1 ) ) 77 78 #define ETHER_ADDR_LEN 6 79 #define ETHER_TYPE_LEN 2 80 #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN) 81 #define ETH_P_IP 0x0800 /* Internet Protocol packet */ 82 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 83 #define ETH_MTU 1500 84 85 #define VLAN_TCI_LEN 2 86 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) 87 88 #if defined (DEBUG_RTL8139) 89 # define DPRINTF(fmt, ...) \ 90 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) 91 #else 92 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...) 93 { 94 return 0; 95 } 96 #endif 97 98 /* Symbolic offsets to registers. */ 99 enum RTL8139_registers { 100 MAC0 = 0, /* Ethernet hardware address. */ 101 MAR0 = 8, /* Multicast filter. */ 102 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ 103 /* Dump Tally Conter control register(64bit). C+ mode only */ 104 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 105 RxBuf = 0x30, 106 ChipCmd = 0x37, 107 RxBufPtr = 0x38, 108 RxBufAddr = 0x3A, 109 IntrMask = 0x3C, 110 IntrStatus = 0x3E, 111 TxConfig = 0x40, 112 RxConfig = 0x44, 113 Timer = 0x48, /* A general-purpose counter. */ 114 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 115 Cfg9346 = 0x50, 116 Config0 = 0x51, 117 Config1 = 0x52, 118 FlashReg = 0x54, 119 MediaStatus = 0x58, 120 Config3 = 0x59, 121 Config4 = 0x5A, /* absent on RTL-8139A */ 122 HltClk = 0x5B, 123 MultiIntr = 0x5C, 124 PCIRevisionID = 0x5E, 125 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ 126 BasicModeCtrl = 0x62, 127 BasicModeStatus = 0x64, 128 NWayAdvert = 0x66, 129 NWayLPAR = 0x68, 130 NWayExpansion = 0x6A, 131 /* Undocumented registers, but required for proper operation. */ 132 FIFOTMS = 0x70, /* FIFO Control and test. */ 133 CSCR = 0x74, /* Chip Status and Configuration Register. */ 134 PARA78 = 0x78, 135 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 136 Config5 = 0xD8, /* absent on RTL-8139A */ 137 /* C+ mode */ 138 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ 139 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ 140 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ 141 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ 142 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ 143 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ 144 TxThresh = 0xEC, /* Early Tx threshold */ 145 }; 146 147 enum ClearBitMasks { 148 MultiIntrClear = 0xF000, 149 ChipCmdClear = 0xE2, 150 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 151 }; 152 153 enum ChipCmdBits { 154 CmdReset = 0x10, 155 CmdRxEnb = 0x08, 156 CmdTxEnb = 0x04, 157 RxBufEmpty = 0x01, 158 }; 159 160 /* C+ mode */ 161 enum CplusCmdBits { 162 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ 163 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ 164 CPlusRxEnb = 0x0002, 165 CPlusTxEnb = 0x0001, 166 }; 167 168 /* Interrupt register bits, using my own meaningful names. */ 169 enum IntrStatusBits { 170 PCIErr = 0x8000, 171 PCSTimeout = 0x4000, 172 RxFIFOOver = 0x40, 173 RxUnderrun = 0x20, 174 RxOverflow = 0x10, 175 TxErr = 0x08, 176 TxOK = 0x04, 177 RxErr = 0x02, 178 RxOK = 0x01, 179 180 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 181 }; 182 183 enum TxStatusBits { 184 TxHostOwns = 0x2000, 185 TxUnderrun = 0x4000, 186 TxStatOK = 0x8000, 187 TxOutOfWindow = 0x20000000, 188 TxAborted = 0x40000000, 189 TxCarrierLost = 0x80000000, 190 }; 191 enum RxStatusBits { 192 RxMulticast = 0x8000, 193 RxPhysical = 0x4000, 194 RxBroadcast = 0x2000, 195 RxBadSymbol = 0x0020, 196 RxRunt = 0x0010, 197 RxTooLong = 0x0008, 198 RxCRCErr = 0x0004, 199 RxBadAlign = 0x0002, 200 RxStatusOK = 0x0001, 201 }; 202 203 /* Bits in RxConfig. */ 204 enum rx_mode_bits { 205 AcceptErr = 0x20, 206 AcceptRunt = 0x10, 207 AcceptBroadcast = 0x08, 208 AcceptMulticast = 0x04, 209 AcceptMyPhys = 0x02, 210 AcceptAllPhys = 0x01, 211 }; 212 213 /* Bits in TxConfig. */ 214 enum tx_config_bits { 215 216 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 217 TxIFGShift = 24, 218 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 219 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 220 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 221 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 222 223 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 224 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ 225 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 226 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ 227 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ 228 229 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 230 }; 231 232 233 /* Transmit Status of All Descriptors (TSAD) Register */ 234 enum TSAD_bits { 235 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 236 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 237 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 238 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 239 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 240 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 241 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 242 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 243 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 244 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 245 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 246 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 247 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 248 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 249 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 250 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 251 }; 252 253 254 /* Bits in Config1 */ 255 enum Config1Bits { 256 Cfg1_PM_Enable = 0x01, 257 Cfg1_VPD_Enable = 0x02, 258 Cfg1_PIO = 0x04, 259 Cfg1_MMIO = 0x08, 260 LWAKE = 0x10, /* not on 8139, 8139A */ 261 Cfg1_Driver_Load = 0x20, 262 Cfg1_LED0 = 0x40, 263 Cfg1_LED1 = 0x80, 264 SLEEP = (1 << 1), /* only on 8139, 8139A */ 265 PWRDN = (1 << 0), /* only on 8139, 8139A */ 266 }; 267 268 /* Bits in Config3 */ 269 enum Config3Bits { 270 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 271 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 272 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 273 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 274 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 275 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 276 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 277 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 278 }; 279 280 /* Bits in Config4 */ 281 enum Config4Bits { 282 LWPTN = (1 << 2), /* not on 8139, 8139A */ 283 }; 284 285 /* Bits in Config5 */ 286 enum Config5Bits { 287 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 288 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 289 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 290 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ 291 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 292 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 293 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 294 }; 295 296 enum RxConfigBits { 297 /* rx fifo threshold */ 298 RxCfgFIFOShift = 13, 299 RxCfgFIFONone = (7 << RxCfgFIFOShift), 300 301 /* Max DMA burst */ 302 RxCfgDMAShift = 8, 303 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 304 305 /* rx ring buffer length */ 306 RxCfgRcv8K = 0, 307 RxCfgRcv16K = (1 << 11), 308 RxCfgRcv32K = (1 << 12), 309 RxCfgRcv64K = (1 << 11) | (1 << 12), 310 311 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 312 RxNoWrap = (1 << 7), 313 }; 314 315 /* Twister tuning parameters from RealTek. 316 Completely undocumented, but required to tune bad links on some boards. */ 317 /* 318 enum CSCRBits { 319 CSCR_LinkOKBit = 0x0400, 320 CSCR_LinkChangeBit = 0x0800, 321 CSCR_LinkStatusBits = 0x0f000, 322 CSCR_LinkDownOffCmd = 0x003c0, 323 CSCR_LinkDownCmd = 0x0f3c0, 324 */ 325 enum CSCRBits { 326 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ 327 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ 328 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ 329 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ 330 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ 331 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ 332 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ 333 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ 334 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ 335 }; 336 337 enum Cfg9346Bits { 338 Cfg9346_Lock = 0x00, 339 Cfg9346_Unlock = 0xC0, 340 }; 341 342 typedef enum { 343 CH_8139 = 0, 344 CH_8139_K, 345 CH_8139A, 346 CH_8139A_G, 347 CH_8139B, 348 CH_8130, 349 CH_8139C, 350 CH_8100, 351 CH_8100B_8139D, 352 CH_8101, 353 } chip_t; 354 355 enum chip_flags { 356 HasHltClk = (1 << 0), 357 HasLWake = (1 << 1), 358 }; 359 360 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 361 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 362 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 363 364 #define RTL8139_PCI_REVID_8139 0x10 365 #define RTL8139_PCI_REVID_8139CPLUS 0x20 366 367 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS 368 369 /* Size is 64 * 16bit words */ 370 #define EEPROM_9346_ADDR_BITS 6 371 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) 372 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) 373 374 enum Chip9346Operation 375 { 376 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ 377 Chip9346_op_read = 0x80, /* 10 AAAAAA */ 378 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ 379 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ 380 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ 381 Chip9346_op_write_all = 0x10, /* 00 01zzzz */ 382 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ 383 }; 384 385 enum Chip9346Mode 386 { 387 Chip9346_none = 0, 388 Chip9346_enter_command_mode, 389 Chip9346_read_command, 390 Chip9346_data_read, /* from output register */ 391 Chip9346_data_write, /* to input register, then to contents at specified address */ 392 Chip9346_data_write_all, /* to input register, then filling contents */ 393 }; 394 395 typedef struct EEprom9346 396 { 397 uint16_t contents[EEPROM_9346_SIZE]; 398 int mode; 399 uint32_t tick; 400 uint8_t address; 401 uint16_t input; 402 uint16_t output; 403 404 uint8_t eecs; 405 uint8_t eesk; 406 uint8_t eedi; 407 uint8_t eedo; 408 } EEprom9346; 409 410 typedef struct RTL8139TallyCounters 411 { 412 /* Tally counters */ 413 uint64_t TxOk; 414 uint64_t RxOk; 415 uint64_t TxERR; 416 uint32_t RxERR; 417 uint16_t MissPkt; 418 uint16_t FAE; 419 uint32_t Tx1Col; 420 uint32_t TxMCol; 421 uint64_t RxOkPhy; 422 uint64_t RxOkBrd; 423 uint32_t RxOkMul; 424 uint16_t TxAbt; 425 uint16_t TxUndrn; 426 } RTL8139TallyCounters; 427 428 /* Clears all tally counters */ 429 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); 430 431 typedef struct RTL8139State { 432 PCIDevice dev; 433 uint8_t phys[8]; /* mac address */ 434 uint8_t mult[8]; /* multicast mask array */ 435 436 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ 437 uint32_t TxAddr[4]; /* TxAddr0 */ 438 uint32_t RxBuf; /* Receive buffer */ 439 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ 440 uint32_t RxBufPtr; 441 uint32_t RxBufAddr; 442 443 uint16_t IntrStatus; 444 uint16_t IntrMask; 445 446 uint32_t TxConfig; 447 uint32_t RxConfig; 448 uint32_t RxMissed; 449 450 uint16_t CSCR; 451 452 uint8_t Cfg9346; 453 uint8_t Config0; 454 uint8_t Config1; 455 uint8_t Config3; 456 uint8_t Config4; 457 uint8_t Config5; 458 459 uint8_t clock_enabled; 460 uint8_t bChipCmdState; 461 462 uint16_t MultiIntr; 463 464 uint16_t BasicModeCtrl; 465 uint16_t BasicModeStatus; 466 uint16_t NWayAdvert; 467 uint16_t NWayLPAR; 468 uint16_t NWayExpansion; 469 470 uint16_t CpCmd; 471 uint8_t TxThresh; 472 473 NICState *nic; 474 NICConf conf; 475 476 /* C ring mode */ 477 uint32_t currTxDesc; 478 479 /* C+ mode */ 480 uint32_t cplus_enabled; 481 482 uint32_t currCPlusRxDesc; 483 uint32_t currCPlusTxDesc; 484 485 uint32_t RxRingAddrLO; 486 uint32_t RxRingAddrHI; 487 488 EEprom9346 eeprom; 489 490 uint32_t TCTR; 491 uint32_t TimerInt; 492 int64_t TCTR_base; 493 494 /* Tally counters */ 495 RTL8139TallyCounters tally_counters; 496 497 /* Non-persistent data */ 498 uint8_t *cplus_txbuffer; 499 int cplus_txbuffer_len; 500 int cplus_txbuffer_offset; 501 502 /* PCI interrupt timer */ 503 QEMUTimer *timer; 504 int64_t TimerExpire; 505 506 MemoryRegion bar_io; 507 MemoryRegion bar_mem; 508 509 /* Support migration to/from old versions */ 510 int rtl8139_mmio_io_addr_dummy; 511 } RTL8139State; 512 513 /* Writes tally counters to memory via DMA */ 514 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); 515 516 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time); 517 518 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) 519 { 520 DPRINTF("eeprom command 0x%02x\n", command); 521 522 switch (command & Chip9346_op_mask) 523 { 524 case Chip9346_op_read: 525 { 526 eeprom->address = command & EEPROM_9346_ADDR_MASK; 527 eeprom->output = eeprom->contents[eeprom->address]; 528 eeprom->eedo = 0; 529 eeprom->tick = 0; 530 eeprom->mode = Chip9346_data_read; 531 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", 532 eeprom->address, eeprom->output); 533 } 534 break; 535 536 case Chip9346_op_write: 537 { 538 eeprom->address = command & EEPROM_9346_ADDR_MASK; 539 eeprom->input = 0; 540 eeprom->tick = 0; 541 eeprom->mode = Chip9346_none; /* Chip9346_data_write */ 542 DPRINTF("eeprom begin write to address 0x%02x\n", 543 eeprom->address); 544 } 545 break; 546 default: 547 eeprom->mode = Chip9346_none; 548 switch (command & Chip9346_op_ext_mask) 549 { 550 case Chip9346_op_write_enable: 551 DPRINTF("eeprom write enabled\n"); 552 break; 553 case Chip9346_op_write_all: 554 DPRINTF("eeprom begin write all\n"); 555 break; 556 case Chip9346_op_write_disable: 557 DPRINTF("eeprom write disabled\n"); 558 break; 559 } 560 break; 561 } 562 } 563 564 static void prom9346_shift_clock(EEprom9346 *eeprom) 565 { 566 int bit = eeprom->eedi?1:0; 567 568 ++ eeprom->tick; 569 570 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, 571 eeprom->eedo); 572 573 switch (eeprom->mode) 574 { 575 case Chip9346_enter_command_mode: 576 if (bit) 577 { 578 eeprom->mode = Chip9346_read_command; 579 eeprom->tick = 0; 580 eeprom->input = 0; 581 DPRINTF("eeprom: +++ synchronized, begin command read\n"); 582 } 583 break; 584 585 case Chip9346_read_command: 586 eeprom->input = (eeprom->input << 1) | (bit & 1); 587 if (eeprom->tick == 8) 588 { 589 prom9346_decode_command(eeprom, eeprom->input & 0xff); 590 } 591 break; 592 593 case Chip9346_data_read: 594 eeprom->eedo = (eeprom->output & 0x8000)?1:0; 595 eeprom->output <<= 1; 596 if (eeprom->tick == 16) 597 { 598 #if 1 599 // the FreeBSD drivers (rl and re) don't explicitly toggle 600 // CS between reads (or does setting Cfg9346 to 0 count too?), 601 // so we need to enter wait-for-command state here 602 eeprom->mode = Chip9346_enter_command_mode; 603 eeprom->input = 0; 604 eeprom->tick = 0; 605 606 DPRINTF("eeprom: +++ end of read, awaiting next command\n"); 607 #else 608 // original behaviour 609 ++eeprom->address; 610 eeprom->address &= EEPROM_9346_ADDR_MASK; 611 eeprom->output = eeprom->contents[eeprom->address]; 612 eeprom->tick = 0; 613 614 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", 615 eeprom->address, eeprom->output); 616 #endif 617 } 618 break; 619 620 case Chip9346_data_write: 621 eeprom->input = (eeprom->input << 1) | (bit & 1); 622 if (eeprom->tick == 16) 623 { 624 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", 625 eeprom->address, eeprom->input); 626 627 eeprom->contents[eeprom->address] = eeprom->input; 628 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ 629 eeprom->tick = 0; 630 eeprom->input = 0; 631 } 632 break; 633 634 case Chip9346_data_write_all: 635 eeprom->input = (eeprom->input << 1) | (bit & 1); 636 if (eeprom->tick == 16) 637 { 638 int i; 639 for (i = 0; i < EEPROM_9346_SIZE; i++) 640 { 641 eeprom->contents[i] = eeprom->input; 642 } 643 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); 644 645 eeprom->mode = Chip9346_enter_command_mode; 646 eeprom->tick = 0; 647 eeprom->input = 0; 648 } 649 break; 650 651 default: 652 break; 653 } 654 } 655 656 static int prom9346_get_wire(RTL8139State *s) 657 { 658 EEprom9346 *eeprom = &s->eeprom; 659 if (!eeprom->eecs) 660 return 0; 661 662 return eeprom->eedo; 663 } 664 665 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ 666 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) 667 { 668 EEprom9346 *eeprom = &s->eeprom; 669 uint8_t old_eecs = eeprom->eecs; 670 uint8_t old_eesk = eeprom->eesk; 671 672 eeprom->eecs = eecs; 673 eeprom->eesk = eesk; 674 eeprom->eedi = eedi; 675 676 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, 677 eeprom->eesk, eeprom->eedi, eeprom->eedo); 678 679 if (!old_eecs && eecs) 680 { 681 /* Synchronize start */ 682 eeprom->tick = 0; 683 eeprom->input = 0; 684 eeprom->output = 0; 685 eeprom->mode = Chip9346_enter_command_mode; 686 687 DPRINTF("=== eeprom: begin access, enter command mode\n"); 688 } 689 690 if (!eecs) 691 { 692 DPRINTF("=== eeprom: end access\n"); 693 return; 694 } 695 696 if (!old_eesk && eesk) 697 { 698 /* SK front rules */ 699 prom9346_shift_clock(eeprom); 700 } 701 } 702 703 static void rtl8139_update_irq(RTL8139State *s) 704 { 705 int isr; 706 isr = (s->IntrStatus & s->IntrMask) & 0xffff; 707 708 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, 709 s->IntrMask); 710 711 qemu_set_irq(s->dev.irq[0], (isr != 0)); 712 } 713 714 #define POLYNOMIAL 0x04c11db6 715 716 /* From FreeBSD */ 717 /* XXX: optimize */ 718 static int compute_mcast_idx(const uint8_t *ep) 719 { 720 uint32_t crc; 721 int carry, i, j; 722 uint8_t b; 723 724 crc = 0xffffffff; 725 for (i = 0; i < 6; i++) { 726 b = *ep++; 727 for (j = 0; j < 8; j++) { 728 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 729 crc <<= 1; 730 b >>= 1; 731 if (carry) 732 crc = ((crc ^ POLYNOMIAL) | carry); 733 } 734 } 735 return (crc >> 26); 736 } 737 738 static int rtl8139_RxWrap(RTL8139State *s) 739 { 740 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ 741 return (s->RxConfig & (1 << 7)); 742 } 743 744 static int rtl8139_receiver_enabled(RTL8139State *s) 745 { 746 return s->bChipCmdState & CmdRxEnb; 747 } 748 749 static int rtl8139_transmitter_enabled(RTL8139State *s) 750 { 751 return s->bChipCmdState & CmdTxEnb; 752 } 753 754 static int rtl8139_cp_receiver_enabled(RTL8139State *s) 755 { 756 return s->CpCmd & CPlusRxEnb; 757 } 758 759 static int rtl8139_cp_transmitter_enabled(RTL8139State *s) 760 { 761 return s->CpCmd & CPlusTxEnb; 762 } 763 764 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) 765 { 766 if (s->RxBufAddr + size > s->RxBufferSize) 767 { 768 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); 769 770 /* write packet data */ 771 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) 772 { 773 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); 774 775 if (size > wrapped) 776 { 777 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, 778 buf, size-wrapped); 779 } 780 781 /* reset buffer pointer */ 782 s->RxBufAddr = 0; 783 784 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, 785 buf + (size-wrapped), wrapped); 786 787 s->RxBufAddr = wrapped; 788 789 return; 790 } 791 } 792 793 /* non-wrapping path or overwrapping enabled */ 794 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size); 795 796 s->RxBufAddr += size; 797 } 798 799 #define MIN_BUF_SIZE 60 800 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) 801 { 802 #if TARGET_PHYS_ADDR_BITS > 32 803 return low | ((target_phys_addr_t)high << 32); 804 #else 805 return low; 806 #endif 807 } 808 809 static int rtl8139_can_receive(VLANClientState *nc) 810 { 811 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; 812 int avail; 813 814 /* Receive (drop) packets if card is disabled. */ 815 if (!s->clock_enabled) 816 return 1; 817 if (!rtl8139_receiver_enabled(s)) 818 return 1; 819 820 if (rtl8139_cp_receiver_enabled(s)) { 821 /* ??? Flow control not implemented in c+ mode. 822 This is a hack to work around slirp deficiencies anyway. */ 823 return 1; 824 } else { 825 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, 826 s->RxBufferSize); 827 return (avail == 0 || avail >= 1514); 828 } 829 } 830 831 static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) 832 { 833 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; 834 /* size is the length of the buffer passed to the driver */ 835 int size = size_; 836 const uint8_t *dot1q_buf = NULL; 837 838 uint32_t packet_header = 0; 839 840 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; 841 static const uint8_t broadcast_macaddr[6] = 842 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 843 844 DPRINTF(">>> received len=%d\n", size); 845 846 /* test if board clock is stopped */ 847 if (!s->clock_enabled) 848 { 849 DPRINTF("stopped ==========================\n"); 850 return -1; 851 } 852 853 /* first check if receiver is enabled */ 854 855 if (!rtl8139_receiver_enabled(s)) 856 { 857 DPRINTF("receiver disabled ================\n"); 858 return -1; 859 } 860 861 /* XXX: check this */ 862 if (s->RxConfig & AcceptAllPhys) { 863 /* promiscuous: receive all */ 864 DPRINTF(">>> packet received in promiscuous mode\n"); 865 866 } else { 867 if (!memcmp(buf, broadcast_macaddr, 6)) { 868 /* broadcast address */ 869 if (!(s->RxConfig & AcceptBroadcast)) 870 { 871 DPRINTF(">>> broadcast packet rejected\n"); 872 873 /* update tally counter */ 874 ++s->tally_counters.RxERR; 875 876 return size; 877 } 878 879 packet_header |= RxBroadcast; 880 881 DPRINTF(">>> broadcast packet received\n"); 882 883 /* update tally counter */ 884 ++s->tally_counters.RxOkBrd; 885 886 } else if (buf[0] & 0x01) { 887 /* multicast */ 888 if (!(s->RxConfig & AcceptMulticast)) 889 { 890 DPRINTF(">>> multicast packet rejected\n"); 891 892 /* update tally counter */ 893 ++s->tally_counters.RxERR; 894 895 return size; 896 } 897 898 int mcast_idx = compute_mcast_idx(buf); 899 900 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 901 { 902 DPRINTF(">>> multicast address mismatch\n"); 903 904 /* update tally counter */ 905 ++s->tally_counters.RxERR; 906 907 return size; 908 } 909 910 packet_header |= RxMulticast; 911 912 DPRINTF(">>> multicast packet received\n"); 913 914 /* update tally counter */ 915 ++s->tally_counters.RxOkMul; 916 917 } else if (s->phys[0] == buf[0] && 918 s->phys[1] == buf[1] && 919 s->phys[2] == buf[2] && 920 s->phys[3] == buf[3] && 921 s->phys[4] == buf[4] && 922 s->phys[5] == buf[5]) { 923 /* match */ 924 if (!(s->RxConfig & AcceptMyPhys)) 925 { 926 DPRINTF(">>> rejecting physical address matching packet\n"); 927 928 /* update tally counter */ 929 ++s->tally_counters.RxERR; 930 931 return size; 932 } 933 934 packet_header |= RxPhysical; 935 936 DPRINTF(">>> physical address matching packet received\n"); 937 938 /* update tally counter */ 939 ++s->tally_counters.RxOkPhy; 940 941 } else { 942 943 DPRINTF(">>> unknown packet\n"); 944 945 /* update tally counter */ 946 ++s->tally_counters.RxERR; 947 948 return size; 949 } 950 } 951 952 /* if too small buffer, then expand it 953 * Include some tailroom in case a vlan tag is later removed. */ 954 if (size < MIN_BUF_SIZE + VLAN_HLEN) { 955 memcpy(buf1, buf, size); 956 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size); 957 buf = buf1; 958 if (size < MIN_BUF_SIZE) { 959 size = MIN_BUF_SIZE; 960 } 961 } 962 963 if (rtl8139_cp_receiver_enabled(s)) 964 { 965 DPRINTF("in C+ Rx mode ================\n"); 966 967 /* begin C+ receiver mode */ 968 969 /* w0 ownership flag */ 970 #define CP_RX_OWN (1<<31) 971 /* w0 end of ring flag */ 972 #define CP_RX_EOR (1<<30) 973 /* w0 bits 0...12 : buffer size */ 974 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) 975 /* w1 tag available flag */ 976 #define CP_RX_TAVA (1<<16) 977 /* w1 bits 0...15 : VLAN tag */ 978 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) 979 /* w2 low 32bit of Rx buffer ptr */ 980 /* w3 high 32bit of Rx buffer ptr */ 981 982 int descriptor = s->currCPlusRxDesc; 983 dma_addr_t cplus_rx_ring_desc; 984 985 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); 986 cplus_rx_ring_desc += 16 * descriptor; 987 988 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " 989 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, 990 s->RxRingAddrLO, cplus_rx_ring_desc); 991 992 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; 993 994 pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4); 995 rxdw0 = le32_to_cpu(val); 996 pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4); 997 rxdw1 = le32_to_cpu(val); 998 pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4); 999 rxbufLO = le32_to_cpu(val); 1000 pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4); 1001 rxbufHI = le32_to_cpu(val); 1002 1003 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", 1004 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); 1005 1006 if (!(rxdw0 & CP_RX_OWN)) 1007 { 1008 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", 1009 descriptor); 1010 1011 s->IntrStatus |= RxOverflow; 1012 ++s->RxMissed; 1013 1014 /* update tally counter */ 1015 ++s->tally_counters.RxERR; 1016 ++s->tally_counters.MissPkt; 1017 1018 rtl8139_update_irq(s); 1019 return size_; 1020 } 1021 1022 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; 1023 1024 /* write VLAN info to descriptor variables. */ 1025 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *) 1026 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) { 1027 dot1q_buf = &buf[ETHER_ADDR_LEN * 2]; 1028 size -= VLAN_HLEN; 1029 /* if too small buffer, use the tailroom added duing expansion */ 1030 if (size < MIN_BUF_SIZE) { 1031 size = MIN_BUF_SIZE; 1032 } 1033 1034 rxdw1 &= ~CP_RX_VLAN_TAG_MASK; 1035 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ 1036 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *) 1037 &dot1q_buf[ETHER_TYPE_LEN]); 1038 1039 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", 1040 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN])); 1041 } else { 1042 /* reset VLAN tag flag */ 1043 rxdw1 &= ~CP_RX_TAVA; 1044 } 1045 1046 /* TODO: scatter the packet over available receive ring descriptors space */ 1047 1048 if (size+4 > rx_space) 1049 { 1050 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n", 1051 descriptor, rx_space, size); 1052 1053 s->IntrStatus |= RxOverflow; 1054 ++s->RxMissed; 1055 1056 /* update tally counter */ 1057 ++s->tally_counters.RxERR; 1058 ++s->tally_counters.MissPkt; 1059 1060 rtl8139_update_irq(s); 1061 return size_; 1062 } 1063 1064 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); 1065 1066 /* receive/copy to target memory */ 1067 if (dot1q_buf) { 1068 pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN); 1069 pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN, 1070 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN, 1071 size - 2 * ETHER_ADDR_LEN); 1072 } else { 1073 pci_dma_write(&s->dev, rx_addr, buf, size); 1074 } 1075 1076 if (s->CpCmd & CPlusRxChkSum) 1077 { 1078 /* do some packet checksumming */ 1079 } 1080 1081 /* write checksum */ 1082 val = cpu_to_le32(crc32(0, buf, size_)); 1083 pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4); 1084 1085 /* first segment of received packet flag */ 1086 #define CP_RX_STATUS_FS (1<<29) 1087 /* last segment of received packet flag */ 1088 #define CP_RX_STATUS_LS (1<<28) 1089 /* multicast packet flag */ 1090 #define CP_RX_STATUS_MAR (1<<26) 1091 /* physical-matching packet flag */ 1092 #define CP_RX_STATUS_PAM (1<<25) 1093 /* broadcast packet flag */ 1094 #define CP_RX_STATUS_BAR (1<<24) 1095 /* runt packet flag */ 1096 #define CP_RX_STATUS_RUNT (1<<19) 1097 /* crc error flag */ 1098 #define CP_RX_STATUS_CRC (1<<18) 1099 /* IP checksum error flag */ 1100 #define CP_RX_STATUS_IPF (1<<15) 1101 /* UDP checksum error flag */ 1102 #define CP_RX_STATUS_UDPF (1<<14) 1103 /* TCP checksum error flag */ 1104 #define CP_RX_STATUS_TCPF (1<<13) 1105 1106 /* transfer ownership to target */ 1107 rxdw0 &= ~CP_RX_OWN; 1108 1109 /* set first segment bit */ 1110 rxdw0 |= CP_RX_STATUS_FS; 1111 1112 /* set last segment bit */ 1113 rxdw0 |= CP_RX_STATUS_LS; 1114 1115 /* set received packet type flags */ 1116 if (packet_header & RxBroadcast) 1117 rxdw0 |= CP_RX_STATUS_BAR; 1118 if (packet_header & RxMulticast) 1119 rxdw0 |= CP_RX_STATUS_MAR; 1120 if (packet_header & RxPhysical) 1121 rxdw0 |= CP_RX_STATUS_PAM; 1122 1123 /* set received size */ 1124 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; 1125 rxdw0 |= (size+4); 1126 1127 /* update ring data */ 1128 val = cpu_to_le32(rxdw0); 1129 pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4); 1130 val = cpu_to_le32(rxdw1); 1131 pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); 1132 1133 /* update tally counter */ 1134 ++s->tally_counters.RxOk; 1135 1136 /* seek to next Rx descriptor */ 1137 if (rxdw0 & CP_RX_EOR) 1138 { 1139 s->currCPlusRxDesc = 0; 1140 } 1141 else 1142 { 1143 ++s->currCPlusRxDesc; 1144 } 1145 1146 DPRINTF("done C+ Rx mode ----------------\n"); 1147 1148 } 1149 else 1150 { 1151 DPRINTF("in ring Rx mode ================\n"); 1152 1153 /* begin ring receiver mode */ 1154 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); 1155 1156 /* if receiver buffer is empty then avail == 0 */ 1157 1158 if (avail != 0 && size + 8 >= avail) 1159 { 1160 DPRINTF("rx overflow: rx buffer length %d head 0x%04x " 1161 "read 0x%04x === available 0x%04x need 0x%04x\n", 1162 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); 1163 1164 s->IntrStatus |= RxOverflow; 1165 ++s->RxMissed; 1166 rtl8139_update_irq(s); 1167 return size_; 1168 } 1169 1170 packet_header |= RxStatusOK; 1171 1172 packet_header |= (((size+4) << 16) & 0xffff0000); 1173 1174 /* write header */ 1175 uint32_t val = cpu_to_le32(packet_header); 1176 1177 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1178 1179 rtl8139_write_buffer(s, buf, size); 1180 1181 /* write checksum */ 1182 val = cpu_to_le32(crc32(0, buf, size)); 1183 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1184 1185 /* correct buffer write pointer */ 1186 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize); 1187 1188 /* now we can signal we have received something */ 1189 1190 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", 1191 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 1192 } 1193 1194 s->IntrStatus |= RxOK; 1195 1196 if (do_interrupt) 1197 { 1198 rtl8139_update_irq(s); 1199 } 1200 1201 return size_; 1202 } 1203 1204 static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size) 1205 { 1206 return rtl8139_do_receive(nc, buf, size, 1); 1207 } 1208 1209 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) 1210 { 1211 s->RxBufferSize = bufferSize; 1212 s->RxBufPtr = 0; 1213 s->RxBufAddr = 0; 1214 } 1215 1216 static void rtl8139_reset(DeviceState *d) 1217 { 1218 RTL8139State *s = container_of(d, RTL8139State, dev.qdev); 1219 int i; 1220 1221 /* restore MAC address */ 1222 memcpy(s->phys, s->conf.macaddr.a, 6); 1223 1224 /* reset interrupt mask */ 1225 s->IntrStatus = 0; 1226 s->IntrMask = 0; 1227 1228 rtl8139_update_irq(s); 1229 1230 /* mark all status registers as owned by host */ 1231 for (i = 0; i < 4; ++i) 1232 { 1233 s->TxStatus[i] = TxHostOwns; 1234 } 1235 1236 s->currTxDesc = 0; 1237 s->currCPlusRxDesc = 0; 1238 s->currCPlusTxDesc = 0; 1239 1240 s->RxRingAddrLO = 0; 1241 s->RxRingAddrHI = 0; 1242 1243 s->RxBuf = 0; 1244 1245 rtl8139_reset_rxring(s, 8192); 1246 1247 /* ACK the reset */ 1248 s->TxConfig = 0; 1249 1250 #if 0 1251 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk 1252 s->clock_enabled = 0; 1253 #else 1254 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake 1255 s->clock_enabled = 1; 1256 #endif 1257 1258 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; 1259 1260 /* set initial state data */ 1261 s->Config0 = 0x0; /* No boot ROM */ 1262 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ 1263 s->Config3 = 0x1; /* fast back-to-back compatible */ 1264 s->Config5 = 0x0; 1265 1266 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; 1267 1268 s->CpCmd = 0x0; /* reset C+ mode */ 1269 s->cplus_enabled = 0; 1270 1271 1272 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation 1273 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex 1274 s->BasicModeCtrl = 0x1000; // autonegotiation 1275 1276 s->BasicModeStatus = 0x7809; 1277 //s->BasicModeStatus |= 0x0040; /* UTP medium */ 1278 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ 1279 s->BasicModeStatus |= 0x0004; /* link is up */ 1280 1281 s->NWayAdvert = 0x05e1; /* all modes, full duplex */ 1282 s->NWayLPAR = 0x05e1; /* all modes, full duplex */ 1283 s->NWayExpansion = 0x0001; /* autonegotiation supported */ 1284 1285 /* also reset timer and disable timer interrupt */ 1286 s->TCTR = 0; 1287 s->TimerInt = 0; 1288 s->TCTR_base = 0; 1289 1290 /* reset tally counters */ 1291 RTL8139TallyCounters_clear(&s->tally_counters); 1292 } 1293 1294 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) 1295 { 1296 counters->TxOk = 0; 1297 counters->RxOk = 0; 1298 counters->TxERR = 0; 1299 counters->RxERR = 0; 1300 counters->MissPkt = 0; 1301 counters->FAE = 0; 1302 counters->Tx1Col = 0; 1303 counters->TxMCol = 0; 1304 counters->RxOkPhy = 0; 1305 counters->RxOkBrd = 0; 1306 counters->RxOkMul = 0; 1307 counters->TxAbt = 0; 1308 counters->TxUndrn = 0; 1309 } 1310 1311 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) 1312 { 1313 RTL8139TallyCounters *tally_counters = &s->tally_counters; 1314 uint16_t val16; 1315 uint32_t val32; 1316 uint64_t val64; 1317 1318 val64 = cpu_to_le64(tally_counters->TxOk); 1319 pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8); 1320 1321 val64 = cpu_to_le64(tally_counters->RxOk); 1322 pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8); 1323 1324 val64 = cpu_to_le64(tally_counters->TxERR); 1325 pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8); 1326 1327 val32 = cpu_to_le32(tally_counters->RxERR); 1328 pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4); 1329 1330 val16 = cpu_to_le16(tally_counters->MissPkt); 1331 pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2); 1332 1333 val16 = cpu_to_le16(tally_counters->FAE); 1334 pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2); 1335 1336 val32 = cpu_to_le32(tally_counters->Tx1Col); 1337 pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4); 1338 1339 val32 = cpu_to_le32(tally_counters->TxMCol); 1340 pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4); 1341 1342 val64 = cpu_to_le64(tally_counters->RxOkPhy); 1343 pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8); 1344 1345 val64 = cpu_to_le64(tally_counters->RxOkBrd); 1346 pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8); 1347 1348 val32 = cpu_to_le32(tally_counters->RxOkMul); 1349 pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4); 1350 1351 val16 = cpu_to_le16(tally_counters->TxAbt); 1352 pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2); 1353 1354 val16 = cpu_to_le16(tally_counters->TxUndrn); 1355 pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2); 1356 } 1357 1358 /* Loads values of tally counters from VM state file */ 1359 1360 static const VMStateDescription vmstate_tally_counters = { 1361 .name = "tally_counters", 1362 .version_id = 1, 1363 .minimum_version_id = 1, 1364 .minimum_version_id_old = 1, 1365 .fields = (VMStateField []) { 1366 VMSTATE_UINT64(TxOk, RTL8139TallyCounters), 1367 VMSTATE_UINT64(RxOk, RTL8139TallyCounters), 1368 VMSTATE_UINT64(TxERR, RTL8139TallyCounters), 1369 VMSTATE_UINT32(RxERR, RTL8139TallyCounters), 1370 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters), 1371 VMSTATE_UINT16(FAE, RTL8139TallyCounters), 1372 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters), 1373 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters), 1374 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters), 1375 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters), 1376 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters), 1377 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters), 1378 VMSTATE_END_OF_LIST() 1379 } 1380 }; 1381 1382 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) 1383 { 1384 val &= 0xff; 1385 1386 DPRINTF("ChipCmd write val=0x%08x\n", val); 1387 1388 if (val & CmdReset) 1389 { 1390 DPRINTF("ChipCmd reset\n"); 1391 rtl8139_reset(&s->dev.qdev); 1392 } 1393 if (val & CmdRxEnb) 1394 { 1395 DPRINTF("ChipCmd enable receiver\n"); 1396 1397 s->currCPlusRxDesc = 0; 1398 } 1399 if (val & CmdTxEnb) 1400 { 1401 DPRINTF("ChipCmd enable transmitter\n"); 1402 1403 s->currCPlusTxDesc = 0; 1404 } 1405 1406 /* mask unwritable bits */ 1407 val = SET_MASKED(val, 0xe3, s->bChipCmdState); 1408 1409 /* Deassert reset pin before next read */ 1410 val &= ~CmdReset; 1411 1412 s->bChipCmdState = val; 1413 } 1414 1415 static int rtl8139_RxBufferEmpty(RTL8139State *s) 1416 { 1417 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); 1418 1419 if (unread != 0) 1420 { 1421 DPRINTF("receiver buffer data available 0x%04x\n", unread); 1422 return 0; 1423 } 1424 1425 DPRINTF("receiver buffer is empty\n"); 1426 1427 return 1; 1428 } 1429 1430 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) 1431 { 1432 uint32_t ret = s->bChipCmdState; 1433 1434 if (rtl8139_RxBufferEmpty(s)) 1435 ret |= RxBufEmpty; 1436 1437 DPRINTF("ChipCmd read val=0x%04x\n", ret); 1438 1439 return ret; 1440 } 1441 1442 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) 1443 { 1444 val &= 0xffff; 1445 1446 DPRINTF("C+ command register write(w) val=0x%04x\n", val); 1447 1448 s->cplus_enabled = 1; 1449 1450 /* mask unwritable bits */ 1451 val = SET_MASKED(val, 0xff84, s->CpCmd); 1452 1453 s->CpCmd = val; 1454 } 1455 1456 static uint32_t rtl8139_CpCmd_read(RTL8139State *s) 1457 { 1458 uint32_t ret = s->CpCmd; 1459 1460 DPRINTF("C+ command register read(w) val=0x%04x\n", ret); 1461 1462 return ret; 1463 } 1464 1465 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) 1466 { 1467 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val); 1468 } 1469 1470 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) 1471 { 1472 uint32_t ret = 0; 1473 1474 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret); 1475 1476 return ret; 1477 } 1478 1479 static int rtl8139_config_writable(RTL8139State *s) 1480 { 1481 if (s->Cfg9346 & Cfg9346_Unlock) 1482 { 1483 return 1; 1484 } 1485 1486 DPRINTF("Configuration registers are write-protected\n"); 1487 1488 return 0; 1489 } 1490 1491 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) 1492 { 1493 val &= 0xffff; 1494 1495 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val); 1496 1497 /* mask unwritable bits */ 1498 uint32_t mask = 0x4cff; 1499 1500 if (1 || !rtl8139_config_writable(s)) 1501 { 1502 /* Speed setting and autonegotiation enable bits are read-only */ 1503 mask |= 0x3000; 1504 /* Duplex mode setting is read-only */ 1505 mask |= 0x0100; 1506 } 1507 1508 val = SET_MASKED(val, mask, s->BasicModeCtrl); 1509 1510 s->BasicModeCtrl = val; 1511 } 1512 1513 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) 1514 { 1515 uint32_t ret = s->BasicModeCtrl; 1516 1517 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret); 1518 1519 return ret; 1520 } 1521 1522 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) 1523 { 1524 val &= 0xffff; 1525 1526 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val); 1527 1528 /* mask unwritable bits */ 1529 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); 1530 1531 s->BasicModeStatus = val; 1532 } 1533 1534 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) 1535 { 1536 uint32_t ret = s->BasicModeStatus; 1537 1538 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret); 1539 1540 return ret; 1541 } 1542 1543 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) 1544 { 1545 val &= 0xff; 1546 1547 DPRINTF("Cfg9346 write val=0x%02x\n", val); 1548 1549 /* mask unwritable bits */ 1550 val = SET_MASKED(val, 0x31, s->Cfg9346); 1551 1552 uint32_t opmode = val & 0xc0; 1553 uint32_t eeprom_val = val & 0xf; 1554 1555 if (opmode == 0x80) { 1556 /* eeprom access */ 1557 int eecs = (eeprom_val & 0x08)?1:0; 1558 int eesk = (eeprom_val & 0x04)?1:0; 1559 int eedi = (eeprom_val & 0x02)?1:0; 1560 prom9346_set_wire(s, eecs, eesk, eedi); 1561 } else if (opmode == 0x40) { 1562 /* Reset. */ 1563 val = 0; 1564 rtl8139_reset(&s->dev.qdev); 1565 } 1566 1567 s->Cfg9346 = val; 1568 } 1569 1570 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) 1571 { 1572 uint32_t ret = s->Cfg9346; 1573 1574 uint32_t opmode = ret & 0xc0; 1575 1576 if (opmode == 0x80) 1577 { 1578 /* eeprom access */ 1579 int eedo = prom9346_get_wire(s); 1580 if (eedo) 1581 { 1582 ret |= 0x01; 1583 } 1584 else 1585 { 1586 ret &= ~0x01; 1587 } 1588 } 1589 1590 DPRINTF("Cfg9346 read val=0x%02x\n", ret); 1591 1592 return ret; 1593 } 1594 1595 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) 1596 { 1597 val &= 0xff; 1598 1599 DPRINTF("Config0 write val=0x%02x\n", val); 1600 1601 if (!rtl8139_config_writable(s)) { 1602 return; 1603 } 1604 1605 /* mask unwritable bits */ 1606 val = SET_MASKED(val, 0xf8, s->Config0); 1607 1608 s->Config0 = val; 1609 } 1610 1611 static uint32_t rtl8139_Config0_read(RTL8139State *s) 1612 { 1613 uint32_t ret = s->Config0; 1614 1615 DPRINTF("Config0 read val=0x%02x\n", ret); 1616 1617 return ret; 1618 } 1619 1620 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) 1621 { 1622 val &= 0xff; 1623 1624 DPRINTF("Config1 write val=0x%02x\n", val); 1625 1626 if (!rtl8139_config_writable(s)) { 1627 return; 1628 } 1629 1630 /* mask unwritable bits */ 1631 val = SET_MASKED(val, 0xC, s->Config1); 1632 1633 s->Config1 = val; 1634 } 1635 1636 static uint32_t rtl8139_Config1_read(RTL8139State *s) 1637 { 1638 uint32_t ret = s->Config1; 1639 1640 DPRINTF("Config1 read val=0x%02x\n", ret); 1641 1642 return ret; 1643 } 1644 1645 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) 1646 { 1647 val &= 0xff; 1648 1649 DPRINTF("Config3 write val=0x%02x\n", val); 1650 1651 if (!rtl8139_config_writable(s)) { 1652 return; 1653 } 1654 1655 /* mask unwritable bits */ 1656 val = SET_MASKED(val, 0x8F, s->Config3); 1657 1658 s->Config3 = val; 1659 } 1660 1661 static uint32_t rtl8139_Config3_read(RTL8139State *s) 1662 { 1663 uint32_t ret = s->Config3; 1664 1665 DPRINTF("Config3 read val=0x%02x\n", ret); 1666 1667 return ret; 1668 } 1669 1670 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) 1671 { 1672 val &= 0xff; 1673 1674 DPRINTF("Config4 write val=0x%02x\n", val); 1675 1676 if (!rtl8139_config_writable(s)) { 1677 return; 1678 } 1679 1680 /* mask unwritable bits */ 1681 val = SET_MASKED(val, 0x0a, s->Config4); 1682 1683 s->Config4 = val; 1684 } 1685 1686 static uint32_t rtl8139_Config4_read(RTL8139State *s) 1687 { 1688 uint32_t ret = s->Config4; 1689 1690 DPRINTF("Config4 read val=0x%02x\n", ret); 1691 1692 return ret; 1693 } 1694 1695 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) 1696 { 1697 val &= 0xff; 1698 1699 DPRINTF("Config5 write val=0x%02x\n", val); 1700 1701 /* mask unwritable bits */ 1702 val = SET_MASKED(val, 0x80, s->Config5); 1703 1704 s->Config5 = val; 1705 } 1706 1707 static uint32_t rtl8139_Config5_read(RTL8139State *s) 1708 { 1709 uint32_t ret = s->Config5; 1710 1711 DPRINTF("Config5 read val=0x%02x\n", ret); 1712 1713 return ret; 1714 } 1715 1716 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) 1717 { 1718 if (!rtl8139_transmitter_enabled(s)) 1719 { 1720 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val); 1721 return; 1722 } 1723 1724 DPRINTF("TxConfig write val=0x%08x\n", val); 1725 1726 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); 1727 1728 s->TxConfig = val; 1729 } 1730 1731 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) 1732 { 1733 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val); 1734 1735 uint32_t tc = s->TxConfig; 1736 tc &= 0xFFFFFF00; 1737 tc |= (val & 0x000000FF); 1738 rtl8139_TxConfig_write(s, tc); 1739 } 1740 1741 static uint32_t rtl8139_TxConfig_read(RTL8139State *s) 1742 { 1743 uint32_t ret = s->TxConfig; 1744 1745 DPRINTF("TxConfig read val=0x%04x\n", ret); 1746 1747 return ret; 1748 } 1749 1750 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) 1751 { 1752 DPRINTF("RxConfig write val=0x%08x\n", val); 1753 1754 /* mask unwritable bits */ 1755 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); 1756 1757 s->RxConfig = val; 1758 1759 /* reset buffer size and read/write pointers */ 1760 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); 1761 1762 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); 1763 } 1764 1765 static uint32_t rtl8139_RxConfig_read(RTL8139State *s) 1766 { 1767 uint32_t ret = s->RxConfig; 1768 1769 DPRINTF("RxConfig read val=0x%08x\n", ret); 1770 1771 return ret; 1772 } 1773 1774 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, 1775 int do_interrupt, const uint8_t *dot1q_buf) 1776 { 1777 struct iovec *iov = NULL; 1778 1779 if (!size) 1780 { 1781 DPRINTF("+++ empty ethernet frame\n"); 1782 return; 1783 } 1784 1785 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) { 1786 iov = (struct iovec[3]) { 1787 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 }, 1788 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN }, 1789 { .iov_base = buf + ETHER_ADDR_LEN * 2, 1790 .iov_len = size - ETHER_ADDR_LEN * 2 }, 1791 }; 1792 } 1793 1794 if (TxLoopBack == (s->TxConfig & TxLoopBack)) 1795 { 1796 size_t buf2_size; 1797 uint8_t *buf2; 1798 1799 if (iov) { 1800 buf2_size = iov_size(iov, 3); 1801 buf2 = g_malloc(buf2_size); 1802 iov_to_buf(iov, 3, buf2, 0, buf2_size); 1803 buf = buf2; 1804 } 1805 1806 DPRINTF("+++ transmit loopback mode\n"); 1807 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt); 1808 1809 if (iov) { 1810 g_free(buf2); 1811 } 1812 } 1813 else 1814 { 1815 if (iov) { 1816 qemu_sendv_packet(&s->nic->nc, iov, 3); 1817 } else { 1818 qemu_send_packet(&s->nic->nc, buf, size); 1819 } 1820 } 1821 } 1822 1823 static int rtl8139_transmit_one(RTL8139State *s, int descriptor) 1824 { 1825 if (!rtl8139_transmitter_enabled(s)) 1826 { 1827 DPRINTF("+++ cannot transmit from descriptor %d: transmitter " 1828 "disabled\n", descriptor); 1829 return 0; 1830 } 1831 1832 if (s->TxStatus[descriptor] & TxHostOwns) 1833 { 1834 DPRINTF("+++ cannot transmit from descriptor %d: owned by host " 1835 "(%08x)\n", descriptor, s->TxStatus[descriptor]); 1836 return 0; 1837 } 1838 1839 DPRINTF("+++ transmitting from descriptor %d\n", descriptor); 1840 1841 int txsize = s->TxStatus[descriptor] & 0x1fff; 1842 uint8_t txbuffer[0x2000]; 1843 1844 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", 1845 txsize, s->TxAddr[descriptor]); 1846 1847 pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize); 1848 1849 /* Mark descriptor as transferred */ 1850 s->TxStatus[descriptor] |= TxHostOwns; 1851 s->TxStatus[descriptor] |= TxStatOK; 1852 1853 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); 1854 1855 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, 1856 descriptor); 1857 1858 /* update interrupt */ 1859 s->IntrStatus |= TxOK; 1860 rtl8139_update_irq(s); 1861 1862 return 1; 1863 } 1864 1865 /* structures and macros for task offloading */ 1866 typedef struct ip_header 1867 { 1868 uint8_t ip_ver_len; /* version and header length */ 1869 uint8_t ip_tos; /* type of service */ 1870 uint16_t ip_len; /* total length */ 1871 uint16_t ip_id; /* identification */ 1872 uint16_t ip_off; /* fragment offset field */ 1873 uint8_t ip_ttl; /* time to live */ 1874 uint8_t ip_p; /* protocol */ 1875 uint16_t ip_sum; /* checksum */ 1876 uint32_t ip_src,ip_dst; /* source and dest address */ 1877 } ip_header; 1878 1879 #define IP_HEADER_VERSION_4 4 1880 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf) 1881 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2) 1882 1883 typedef struct tcp_header 1884 { 1885 uint16_t th_sport; /* source port */ 1886 uint16_t th_dport; /* destination port */ 1887 uint32_t th_seq; /* sequence number */ 1888 uint32_t th_ack; /* acknowledgement number */ 1889 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */ 1890 uint16_t th_win; /* window */ 1891 uint16_t th_sum; /* checksum */ 1892 uint16_t th_urp; /* urgent pointer */ 1893 } tcp_header; 1894 1895 typedef struct udp_header 1896 { 1897 uint16_t uh_sport; /* source port */ 1898 uint16_t uh_dport; /* destination port */ 1899 uint16_t uh_ulen; /* udp length */ 1900 uint16_t uh_sum; /* udp checksum */ 1901 } udp_header; 1902 1903 typedef struct ip_pseudo_header 1904 { 1905 uint32_t ip_src; 1906 uint32_t ip_dst; 1907 uint8_t zeros; 1908 uint8_t ip_proto; 1909 uint16_t ip_payload; 1910 } ip_pseudo_header; 1911 1912 #define IP_PROTO_TCP 6 1913 #define IP_PROTO_UDP 17 1914 1915 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2) 1916 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f) 1917 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags)) 1918 1919 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) 1920 1921 #define TCP_FLAG_FIN 0x01 1922 #define TCP_FLAG_PUSH 0x08 1923 1924 /* produces ones' complement sum of data */ 1925 static uint16_t ones_complement_sum(uint8_t *data, size_t len) 1926 { 1927 uint32_t result = 0; 1928 1929 for (; len > 1; data+=2, len-=2) 1930 { 1931 result += *(uint16_t*)data; 1932 } 1933 1934 /* add the remainder byte */ 1935 if (len) 1936 { 1937 uint8_t odd[2] = {*data, 0}; 1938 result += *(uint16_t*)odd; 1939 } 1940 1941 while (result>>16) 1942 result = (result & 0xffff) + (result >> 16); 1943 1944 return result; 1945 } 1946 1947 static uint16_t ip_checksum(void *data, size_t len) 1948 { 1949 return ~ones_complement_sum((uint8_t*)data, len); 1950 } 1951 1952 static int rtl8139_cplus_transmit_one(RTL8139State *s) 1953 { 1954 if (!rtl8139_transmitter_enabled(s)) 1955 { 1956 DPRINTF("+++ C+ mode: transmitter disabled\n"); 1957 return 0; 1958 } 1959 1960 if (!rtl8139_cp_transmitter_enabled(s)) 1961 { 1962 DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); 1963 return 0 ; 1964 } 1965 1966 int descriptor = s->currCPlusTxDesc; 1967 1968 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); 1969 1970 /* Normal priority ring */ 1971 cplus_tx_ring_desc += 16 * descriptor; 1972 1973 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " 1974 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], 1975 s->TxAddr[0], cplus_tx_ring_desc); 1976 1977 uint32_t val, txdw0,txdw1,txbufLO,txbufHI; 1978 1979 pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4); 1980 txdw0 = le32_to_cpu(val); 1981 pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); 1982 txdw1 = le32_to_cpu(val); 1983 pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); 1984 txbufLO = le32_to_cpu(val); 1985 pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); 1986 txbufHI = le32_to_cpu(val); 1987 1988 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, 1989 txdw0, txdw1, txbufLO, txbufHI); 1990 1991 /* w0 ownership flag */ 1992 #define CP_TX_OWN (1<<31) 1993 /* w0 end of ring flag */ 1994 #define CP_TX_EOR (1<<30) 1995 /* first segment of received packet flag */ 1996 #define CP_TX_FS (1<<29) 1997 /* last segment of received packet flag */ 1998 #define CP_TX_LS (1<<28) 1999 /* large send packet flag */ 2000 #define CP_TX_LGSEN (1<<27) 2001 /* large send MSS mask, bits 16...25 */ 2002 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) 2003 2004 /* IP checksum offload flag */ 2005 #define CP_TX_IPCS (1<<18) 2006 /* UDP checksum offload flag */ 2007 #define CP_TX_UDPCS (1<<17) 2008 /* TCP checksum offload flag */ 2009 #define CP_TX_TCPCS (1<<16) 2010 2011 /* w0 bits 0...15 : buffer size */ 2012 #define CP_TX_BUFFER_SIZE (1<<16) 2013 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) 2014 /* w1 add tag flag */ 2015 #define CP_TX_TAGC (1<<17) 2016 /* w1 bits 0...15 : VLAN tag (big endian) */ 2017 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) 2018 /* w2 low 32bit of Rx buffer ptr */ 2019 /* w3 high 32bit of Rx buffer ptr */ 2020 2021 /* set after transmission */ 2022 /* FIFO underrun flag */ 2023 #define CP_TX_STATUS_UNF (1<<25) 2024 /* transmit error summary flag, valid if set any of three below */ 2025 #define CP_TX_STATUS_TES (1<<23) 2026 /* out-of-window collision flag */ 2027 #define CP_TX_STATUS_OWC (1<<22) 2028 /* link failure flag */ 2029 #define CP_TX_STATUS_LNKF (1<<21) 2030 /* excessive collisions flag */ 2031 #define CP_TX_STATUS_EXC (1<<20) 2032 2033 if (!(txdw0 & CP_TX_OWN)) 2034 { 2035 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); 2036 return 0 ; 2037 } 2038 2039 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); 2040 2041 if (txdw0 & CP_TX_FS) 2042 { 2043 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " 2044 "descriptor\n", descriptor); 2045 2046 /* reset internal buffer offset */ 2047 s->cplus_txbuffer_offset = 0; 2048 } 2049 2050 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; 2051 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); 2052 2053 /* make sure we have enough space to assemble the packet */ 2054 if (!s->cplus_txbuffer) 2055 { 2056 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; 2057 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); 2058 s->cplus_txbuffer_offset = 0; 2059 2060 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", 2061 s->cplus_txbuffer_len); 2062 } 2063 2064 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) 2065 { 2066 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ 2067 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; 2068 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" 2069 "length to %d\n", txsize); 2070 } 2071 2072 if (!s->cplus_txbuffer) 2073 { 2074 /* out of memory */ 2075 2076 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n", 2077 s->cplus_txbuffer_len); 2078 2079 /* update tally counter */ 2080 ++s->tally_counters.TxERR; 2081 ++s->tally_counters.TxAbt; 2082 2083 return 0; 2084 } 2085 2086 /* append more data to the packet */ 2087 2088 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " 2089 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr, 2090 s->cplus_txbuffer_offset); 2091 2092 pci_dma_read(&s->dev, tx_addr, 2093 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); 2094 s->cplus_txbuffer_offset += txsize; 2095 2096 /* seek to next Rx descriptor */ 2097 if (txdw0 & CP_TX_EOR) 2098 { 2099 s->currCPlusTxDesc = 0; 2100 } 2101 else 2102 { 2103 ++s->currCPlusTxDesc; 2104 if (s->currCPlusTxDesc >= 64) 2105 s->currCPlusTxDesc = 0; 2106 } 2107 2108 /* transfer ownership to target */ 2109 txdw0 &= ~CP_RX_OWN; 2110 2111 /* reset error indicator bits */ 2112 txdw0 &= ~CP_TX_STATUS_UNF; 2113 txdw0 &= ~CP_TX_STATUS_TES; 2114 txdw0 &= ~CP_TX_STATUS_OWC; 2115 txdw0 &= ~CP_TX_STATUS_LNKF; 2116 txdw0 &= ~CP_TX_STATUS_EXC; 2117 2118 /* update ring data */ 2119 val = cpu_to_le32(txdw0); 2120 pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4); 2121 2122 /* Now decide if descriptor being processed is holding the last segment of packet */ 2123 if (txdw0 & CP_TX_LS) 2124 { 2125 uint8_t dot1q_buffer_space[VLAN_HLEN]; 2126 uint16_t *dot1q_buffer; 2127 2128 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", 2129 descriptor); 2130 2131 /* can transfer fully assembled packet */ 2132 2133 uint8_t *saved_buffer = s->cplus_txbuffer; 2134 int saved_size = s->cplus_txbuffer_offset; 2135 int saved_buffer_len = s->cplus_txbuffer_len; 2136 2137 /* create vlan tag */ 2138 if (txdw1 & CP_TX_TAGC) { 2139 /* the vlan tag is in BE byte order in the descriptor 2140 * BE + le_to_cpu() + ~swap()~ = cpu */ 2141 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", 2142 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); 2143 2144 dot1q_buffer = (uint16_t *) dot1q_buffer_space; 2145 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q); 2146 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ 2147 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); 2148 } else { 2149 dot1q_buffer = NULL; 2150 } 2151 2152 /* reset the card space to protect from recursive call */ 2153 s->cplus_txbuffer = NULL; 2154 s->cplus_txbuffer_offset = 0; 2155 s->cplus_txbuffer_len = 0; 2156 2157 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) 2158 { 2159 DPRINTF("+++ C+ mode offloaded task checksum\n"); 2160 2161 /* ip packet header */ 2162 ip_header *ip = NULL; 2163 int hlen = 0; 2164 uint8_t ip_protocol = 0; 2165 uint16_t ip_data_len = 0; 2166 2167 uint8_t *eth_payload_data = NULL; 2168 size_t eth_payload_len = 0; 2169 2170 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); 2171 if (proto == ETH_P_IP) 2172 { 2173 DPRINTF("+++ C+ mode has IP packet\n"); 2174 2175 /* not aligned */ 2176 eth_payload_data = saved_buffer + ETH_HLEN; 2177 eth_payload_len = saved_size - ETH_HLEN; 2178 2179 ip = (ip_header*)eth_payload_data; 2180 2181 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { 2182 DPRINTF("+++ C+ mode packet has bad IP version %d " 2183 "expected %d\n", IP_HEADER_VERSION(ip), 2184 IP_HEADER_VERSION_4); 2185 ip = NULL; 2186 } else { 2187 hlen = IP_HEADER_LENGTH(ip); 2188 ip_protocol = ip->ip_p; 2189 ip_data_len = be16_to_cpu(ip->ip_len) - hlen; 2190 } 2191 } 2192 2193 if (ip) 2194 { 2195 if (txdw0 & CP_TX_IPCS) 2196 { 2197 DPRINTF("+++ C+ mode need IP checksum\n"); 2198 2199 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */ 2200 /* bad packet header len */ 2201 /* or packet too short */ 2202 } 2203 else 2204 { 2205 ip->ip_sum = 0; 2206 ip->ip_sum = ip_checksum(ip, hlen); 2207 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", 2208 hlen, ip->ip_sum); 2209 } 2210 } 2211 2212 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) 2213 { 2214 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; 2215 2216 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d " 2217 "frame data %d specified MSS=%d\n", ETH_MTU, 2218 ip_data_len, saved_size - ETH_HLEN, large_send_mss); 2219 2220 int tcp_send_offset = 0; 2221 int send_count = 0; 2222 2223 /* maximum IP header length is 60 bytes */ 2224 uint8_t saved_ip_header[60]; 2225 2226 /* save IP header template; data area is used in tcp checksum calculation */ 2227 memcpy(saved_ip_header, eth_payload_data, hlen); 2228 2229 /* a placeholder for checksum calculation routine in tcp case */ 2230 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2231 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2232 2233 /* pointer to TCP header */ 2234 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); 2235 2236 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); 2237 2238 /* ETH_MTU = ip header len + tcp header len + payload */ 2239 int tcp_data_len = ip_data_len - tcp_hlen; 2240 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen; 2241 2242 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " 2243 "data len %d TCP chunk size %d\n", ip_data_len, 2244 tcp_hlen, tcp_data_len, tcp_chunk_size); 2245 2246 /* note the cycle below overwrites IP header data, 2247 but restores it from saved_ip_header before sending packet */ 2248 2249 int is_last_frame = 0; 2250 2251 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) 2252 { 2253 uint16_t chunk_size = tcp_chunk_size; 2254 2255 /* check if this is the last frame */ 2256 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len) 2257 { 2258 is_last_frame = 1; 2259 chunk_size = tcp_data_len - tcp_send_offset; 2260 } 2261 2262 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", 2263 be32_to_cpu(p_tcp_hdr->th_seq)); 2264 2265 /* add 4 TCP pseudoheader fields */ 2266 /* copy IP source and destination fields */ 2267 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2268 2269 DPRINTF("+++ C+ mode TSO calculating TCP checksum for " 2270 "packet with %d bytes data\n", tcp_hlen + 2271 chunk_size); 2272 2273 if (tcp_send_offset) 2274 { 2275 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); 2276 } 2277 2278 /* keep PUSH and FIN flags only for the last frame */ 2279 if (!is_last_frame) 2280 { 2281 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN); 2282 } 2283 2284 /* recalculate TCP checksum */ 2285 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2286 p_tcpip_hdr->zeros = 0; 2287 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2288 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); 2289 2290 p_tcp_hdr->th_sum = 0; 2291 2292 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); 2293 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", 2294 tcp_checksum); 2295 2296 p_tcp_hdr->th_sum = tcp_checksum; 2297 2298 /* restore IP header */ 2299 memcpy(eth_payload_data, saved_ip_header, hlen); 2300 2301 /* set IP data length and recalculate IP checksum */ 2302 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); 2303 2304 /* increment IP id for subsequent frames */ 2305 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); 2306 2307 ip->ip_sum = 0; 2308 ip->ip_sum = ip_checksum(eth_payload_data, hlen); 2309 DPRINTF("+++ C+ mode TSO IP header len=%d " 2310 "checksum=%04x\n", hlen, ip->ip_sum); 2311 2312 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; 2313 DPRINTF("+++ C+ mode TSO transferring packet size " 2314 "%d\n", tso_send_size); 2315 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 2316 0, (uint8_t *) dot1q_buffer); 2317 2318 /* add transferred count to TCP sequence number */ 2319 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq)); 2320 ++send_count; 2321 } 2322 2323 /* Stop sending this frame */ 2324 saved_size = 0; 2325 } 2326 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) 2327 { 2328 DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); 2329 2330 /* maximum IP header length is 60 bytes */ 2331 uint8_t saved_ip_header[60]; 2332 memcpy(saved_ip_header, eth_payload_data, hlen); 2333 2334 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2335 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2336 2337 /* add 4 TCP pseudoheader fields */ 2338 /* copy IP source and destination fields */ 2339 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2340 2341 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) 2342 { 2343 DPRINTF("+++ C+ mode calculating TCP checksum for " 2344 "packet with %d bytes data\n", ip_data_len); 2345 2346 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2347 p_tcpip_hdr->zeros = 0; 2348 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2349 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2350 2351 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); 2352 2353 p_tcp_hdr->th_sum = 0; 2354 2355 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2356 DPRINTF("+++ C+ mode TCP checksum %04x\n", 2357 tcp_checksum); 2358 2359 p_tcp_hdr->th_sum = tcp_checksum; 2360 } 2361 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) 2362 { 2363 DPRINTF("+++ C+ mode calculating UDP checksum for " 2364 "packet with %d bytes data\n", ip_data_len); 2365 2366 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; 2367 p_udpip_hdr->zeros = 0; 2368 p_udpip_hdr->ip_proto = IP_PROTO_UDP; 2369 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2370 2371 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); 2372 2373 p_udp_hdr->uh_sum = 0; 2374 2375 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2376 DPRINTF("+++ C+ mode UDP checksum %04x\n", 2377 udp_checksum); 2378 2379 p_udp_hdr->uh_sum = udp_checksum; 2380 } 2381 2382 /* restore IP header */ 2383 memcpy(eth_payload_data, saved_ip_header, hlen); 2384 } 2385 } 2386 } 2387 2388 /* update tally counter */ 2389 ++s->tally_counters.TxOk; 2390 2391 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); 2392 2393 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, 2394 (uint8_t *) dot1q_buffer); 2395 2396 /* restore card space if there was no recursion and reset offset */ 2397 if (!s->cplus_txbuffer) 2398 { 2399 s->cplus_txbuffer = saved_buffer; 2400 s->cplus_txbuffer_len = saved_buffer_len; 2401 s->cplus_txbuffer_offset = 0; 2402 } 2403 else 2404 { 2405 g_free(saved_buffer); 2406 } 2407 } 2408 else 2409 { 2410 DPRINTF("+++ C+ mode transmission continue to next descriptor\n"); 2411 } 2412 2413 return 1; 2414 } 2415 2416 static void rtl8139_cplus_transmit(RTL8139State *s) 2417 { 2418 int txcount = 0; 2419 2420 while (rtl8139_cplus_transmit_one(s)) 2421 { 2422 ++txcount; 2423 } 2424 2425 /* Mark transfer completed */ 2426 if (!txcount) 2427 { 2428 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", 2429 s->currCPlusTxDesc); 2430 } 2431 else 2432 { 2433 /* update interrupt status */ 2434 s->IntrStatus |= TxOK; 2435 rtl8139_update_irq(s); 2436 } 2437 } 2438 2439 static void rtl8139_transmit(RTL8139State *s) 2440 { 2441 int descriptor = s->currTxDesc, txcount = 0; 2442 2443 /*while*/ 2444 if (rtl8139_transmit_one(s, descriptor)) 2445 { 2446 ++s->currTxDesc; 2447 s->currTxDesc %= 4; 2448 ++txcount; 2449 } 2450 2451 /* Mark transfer completed */ 2452 if (!txcount) 2453 { 2454 DPRINTF("transmitter queue stalled, current TxDesc = %d\n", 2455 s->currTxDesc); 2456 } 2457 } 2458 2459 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) 2460 { 2461 2462 int descriptor = txRegOffset/4; 2463 2464 /* handle C+ transmit mode register configuration */ 2465 2466 if (s->cplus_enabled) 2467 { 2468 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " 2469 "descriptor=%d\n", txRegOffset, val, descriptor); 2470 2471 /* handle Dump Tally Counters command */ 2472 s->TxStatus[descriptor] = val; 2473 2474 if (descriptor == 0 && (val & 0x8)) 2475 { 2476 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); 2477 2478 /* dump tally counters to specified memory location */ 2479 RTL8139TallyCounters_dma_write(s, tc_addr); 2480 2481 /* mark dump completed */ 2482 s->TxStatus[0] &= ~0x8; 2483 } 2484 2485 return; 2486 } 2487 2488 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", 2489 txRegOffset, val, descriptor); 2490 2491 /* mask only reserved bits */ 2492 val &= ~0xff00c000; /* these bits are reset on write */ 2493 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); 2494 2495 s->TxStatus[descriptor] = val; 2496 2497 /* attempt to start transmission */ 2498 rtl8139_transmit(s); 2499 } 2500 2501 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset) 2502 { 2503 uint32_t ret = s->TxStatus[txRegOffset/4]; 2504 2505 DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret); 2506 2507 return ret; 2508 } 2509 2510 static uint16_t rtl8139_TSAD_read(RTL8139State *s) 2511 { 2512 uint16_t ret = 0; 2513 2514 /* Simulate TSAD, it is read only anyway */ 2515 2516 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) 2517 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) 2518 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) 2519 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) 2520 2521 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) 2522 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) 2523 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) 2524 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) 2525 2526 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) 2527 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) 2528 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) 2529 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) 2530 2531 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) 2532 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) 2533 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) 2534 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; 2535 2536 2537 DPRINTF("TSAD read val=0x%04x\n", ret); 2538 2539 return ret; 2540 } 2541 2542 static uint16_t rtl8139_CSCR_read(RTL8139State *s) 2543 { 2544 uint16_t ret = s->CSCR; 2545 2546 DPRINTF("CSCR read val=0x%04x\n", ret); 2547 2548 return ret; 2549 } 2550 2551 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) 2552 { 2553 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); 2554 2555 s->TxAddr[txAddrOffset/4] = val; 2556 } 2557 2558 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) 2559 { 2560 uint32_t ret = s->TxAddr[txAddrOffset/4]; 2561 2562 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); 2563 2564 return ret; 2565 } 2566 2567 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) 2568 { 2569 DPRINTF("RxBufPtr write val=0x%04x\n", val); 2570 2571 /* this value is off by 16 */ 2572 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); 2573 2574 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", 2575 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 2576 } 2577 2578 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) 2579 { 2580 /* this value is off by 16 */ 2581 uint32_t ret = s->RxBufPtr - 0x10; 2582 2583 DPRINTF("RxBufPtr read val=0x%04x\n", ret); 2584 2585 return ret; 2586 } 2587 2588 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) 2589 { 2590 /* this value is NOT off by 16 */ 2591 uint32_t ret = s->RxBufAddr; 2592 2593 DPRINTF("RxBufAddr read val=0x%04x\n", ret); 2594 2595 return ret; 2596 } 2597 2598 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) 2599 { 2600 DPRINTF("RxBuf write val=0x%08x\n", val); 2601 2602 s->RxBuf = val; 2603 2604 /* may need to reset rxring here */ 2605 } 2606 2607 static uint32_t rtl8139_RxBuf_read(RTL8139State *s) 2608 { 2609 uint32_t ret = s->RxBuf; 2610 2611 DPRINTF("RxBuf read val=0x%08x\n", ret); 2612 2613 return ret; 2614 } 2615 2616 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) 2617 { 2618 DPRINTF("IntrMask write(w) val=0x%04x\n", val); 2619 2620 /* mask unwritable bits */ 2621 val = SET_MASKED(val, 0x1e00, s->IntrMask); 2622 2623 s->IntrMask = val; 2624 2625 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); 2626 rtl8139_update_irq(s); 2627 2628 } 2629 2630 static uint32_t rtl8139_IntrMask_read(RTL8139State *s) 2631 { 2632 uint32_t ret = s->IntrMask; 2633 2634 DPRINTF("IntrMask read(w) val=0x%04x\n", ret); 2635 2636 return ret; 2637 } 2638 2639 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) 2640 { 2641 DPRINTF("IntrStatus write(w) val=0x%04x\n", val); 2642 2643 #if 0 2644 2645 /* writing to ISR has no effect */ 2646 2647 return; 2648 2649 #else 2650 uint16_t newStatus = s->IntrStatus & ~val; 2651 2652 /* mask unwritable bits */ 2653 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); 2654 2655 /* writing 1 to interrupt status register bit clears it */ 2656 s->IntrStatus = 0; 2657 rtl8139_update_irq(s); 2658 2659 s->IntrStatus = newStatus; 2660 /* 2661 * Computing if we miss an interrupt here is not that correct but 2662 * considered that we should have had already an interrupt 2663 * and probably emulated is slower is better to assume this resetting was 2664 * done before testing on previous rtl8139_update_irq lead to IRQ losing 2665 */ 2666 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); 2667 rtl8139_update_irq(s); 2668 2669 #endif 2670 } 2671 2672 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) 2673 { 2674 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); 2675 2676 uint32_t ret = s->IntrStatus; 2677 2678 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret); 2679 2680 #if 0 2681 2682 /* reading ISR clears all interrupts */ 2683 s->IntrStatus = 0; 2684 2685 rtl8139_update_irq(s); 2686 2687 #endif 2688 2689 return ret; 2690 } 2691 2692 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) 2693 { 2694 DPRINTF("MultiIntr write(w) val=0x%04x\n", val); 2695 2696 /* mask unwritable bits */ 2697 val = SET_MASKED(val, 0xf000, s->MultiIntr); 2698 2699 s->MultiIntr = val; 2700 } 2701 2702 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) 2703 { 2704 uint32_t ret = s->MultiIntr; 2705 2706 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret); 2707 2708 return ret; 2709 } 2710 2711 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) 2712 { 2713 RTL8139State *s = opaque; 2714 2715 switch (addr) 2716 { 2717 case MAC0 ... MAC0+5: 2718 s->phys[addr - MAC0] = val; 2719 break; 2720 case MAC0+6 ... MAC0+7: 2721 /* reserved */ 2722 break; 2723 case MAR0 ... MAR0+7: 2724 s->mult[addr - MAR0] = val; 2725 break; 2726 case ChipCmd: 2727 rtl8139_ChipCmd_write(s, val); 2728 break; 2729 case Cfg9346: 2730 rtl8139_Cfg9346_write(s, val); 2731 break; 2732 case TxConfig: /* windows driver sometimes writes using byte-lenth call */ 2733 rtl8139_TxConfig_writeb(s, val); 2734 break; 2735 case Config0: 2736 rtl8139_Config0_write(s, val); 2737 break; 2738 case Config1: 2739 rtl8139_Config1_write(s, val); 2740 break; 2741 case Config3: 2742 rtl8139_Config3_write(s, val); 2743 break; 2744 case Config4: 2745 rtl8139_Config4_write(s, val); 2746 break; 2747 case Config5: 2748 rtl8139_Config5_write(s, val); 2749 break; 2750 case MediaStatus: 2751 /* ignore */ 2752 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", 2753 val); 2754 break; 2755 2756 case HltClk: 2757 DPRINTF("HltClk write val=0x%08x\n", val); 2758 if (val == 'R') 2759 { 2760 s->clock_enabled = 1; 2761 } 2762 else if (val == 'H') 2763 { 2764 s->clock_enabled = 0; 2765 } 2766 break; 2767 2768 case TxThresh: 2769 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val); 2770 s->TxThresh = val; 2771 break; 2772 2773 case TxPoll: 2774 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); 2775 if (val & (1 << 7)) 2776 { 2777 DPRINTF("C+ TxPoll high priority transmission (not " 2778 "implemented)\n"); 2779 //rtl8139_cplus_transmit(s); 2780 } 2781 if (val & (1 << 6)) 2782 { 2783 DPRINTF("C+ TxPoll normal priority transmission\n"); 2784 rtl8139_cplus_transmit(s); 2785 } 2786 2787 break; 2788 2789 default: 2790 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, 2791 val); 2792 break; 2793 } 2794 } 2795 2796 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) 2797 { 2798 RTL8139State *s = opaque; 2799 2800 switch (addr) 2801 { 2802 case IntrMask: 2803 rtl8139_IntrMask_write(s, val); 2804 break; 2805 2806 case IntrStatus: 2807 rtl8139_IntrStatus_write(s, val); 2808 break; 2809 2810 case MultiIntr: 2811 rtl8139_MultiIntr_write(s, val); 2812 break; 2813 2814 case RxBufPtr: 2815 rtl8139_RxBufPtr_write(s, val); 2816 break; 2817 2818 case BasicModeCtrl: 2819 rtl8139_BasicModeCtrl_write(s, val); 2820 break; 2821 case BasicModeStatus: 2822 rtl8139_BasicModeStatus_write(s, val); 2823 break; 2824 case NWayAdvert: 2825 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val); 2826 s->NWayAdvert = val; 2827 break; 2828 case NWayLPAR: 2829 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val); 2830 break; 2831 case NWayExpansion: 2832 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val); 2833 s->NWayExpansion = val; 2834 break; 2835 2836 case CpCmd: 2837 rtl8139_CpCmd_write(s, val); 2838 break; 2839 2840 case IntrMitigate: 2841 rtl8139_IntrMitigate_write(s, val); 2842 break; 2843 2844 default: 2845 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", 2846 addr, val); 2847 2848 rtl8139_io_writeb(opaque, addr, val & 0xff); 2849 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2850 break; 2851 } 2852 } 2853 2854 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time) 2855 { 2856 int64_t pci_time, next_time; 2857 uint32_t low_pci; 2858 2859 DPRINTF("entered rtl8139_set_next_tctr_time\n"); 2860 2861 if (s->TimerExpire && current_time >= s->TimerExpire) { 2862 s->IntrStatus |= PCSTimeout; 2863 rtl8139_update_irq(s); 2864 } 2865 2866 /* Set QEMU timer only if needed that is 2867 * - TimerInt <> 0 (we have a timer) 2868 * - mask = 1 (we want an interrupt timer) 2869 * - irq = 0 (irq is not already active) 2870 * If any of above change we need to compute timer again 2871 * Also we must check if timer is passed without QEMU timer 2872 */ 2873 s->TimerExpire = 0; 2874 if (!s->TimerInt) { 2875 return; 2876 } 2877 2878 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, 2879 get_ticks_per_sec()); 2880 low_pci = pci_time & 0xffffffff; 2881 pci_time = pci_time - low_pci + s->TimerInt; 2882 if (low_pci >= s->TimerInt) { 2883 pci_time += 0x100000000LL; 2884 } 2885 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(), 2886 PCI_FREQUENCY); 2887 s->TimerExpire = next_time; 2888 2889 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) { 2890 qemu_mod_timer(s->timer, next_time); 2891 } 2892 } 2893 2894 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) 2895 { 2896 RTL8139State *s = opaque; 2897 2898 switch (addr) 2899 { 2900 case RxMissed: 2901 DPRINTF("RxMissed clearing on write\n"); 2902 s->RxMissed = 0; 2903 break; 2904 2905 case TxConfig: 2906 rtl8139_TxConfig_write(s, val); 2907 break; 2908 2909 case RxConfig: 2910 rtl8139_RxConfig_write(s, val); 2911 break; 2912 2913 case TxStatus0 ... TxStatus0+4*4-1: 2914 rtl8139_TxStatus_write(s, addr-TxStatus0, val); 2915 break; 2916 2917 case TxAddr0 ... TxAddr0+4*4-1: 2918 rtl8139_TxAddr_write(s, addr-TxAddr0, val); 2919 break; 2920 2921 case RxBuf: 2922 rtl8139_RxBuf_write(s, val); 2923 break; 2924 2925 case RxRingAddrLO: 2926 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val); 2927 s->RxRingAddrLO = val; 2928 break; 2929 2930 case RxRingAddrHI: 2931 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val); 2932 s->RxRingAddrHI = val; 2933 break; 2934 2935 case Timer: 2936 DPRINTF("TCTR Timer reset on write\n"); 2937 s->TCTR_base = qemu_get_clock_ns(vm_clock); 2938 rtl8139_set_next_tctr_time(s, s->TCTR_base); 2939 break; 2940 2941 case FlashReg: 2942 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val); 2943 if (s->TimerInt != val) { 2944 s->TimerInt = val; 2945 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); 2946 } 2947 break; 2948 2949 default: 2950 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", 2951 addr, val); 2952 rtl8139_io_writeb(opaque, addr, val & 0xff); 2953 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2954 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); 2955 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); 2956 break; 2957 } 2958 } 2959 2960 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) 2961 { 2962 RTL8139State *s = opaque; 2963 int ret; 2964 2965 switch (addr) 2966 { 2967 case MAC0 ... MAC0+5: 2968 ret = s->phys[addr - MAC0]; 2969 break; 2970 case MAC0+6 ... MAC0+7: 2971 ret = 0; 2972 break; 2973 case MAR0 ... MAR0+7: 2974 ret = s->mult[addr - MAR0]; 2975 break; 2976 case ChipCmd: 2977 ret = rtl8139_ChipCmd_read(s); 2978 break; 2979 case Cfg9346: 2980 ret = rtl8139_Cfg9346_read(s); 2981 break; 2982 case Config0: 2983 ret = rtl8139_Config0_read(s); 2984 break; 2985 case Config1: 2986 ret = rtl8139_Config1_read(s); 2987 break; 2988 case Config3: 2989 ret = rtl8139_Config3_read(s); 2990 break; 2991 case Config4: 2992 ret = rtl8139_Config4_read(s); 2993 break; 2994 case Config5: 2995 ret = rtl8139_Config5_read(s); 2996 break; 2997 2998 case MediaStatus: 2999 ret = 0xd0; 3000 DPRINTF("MediaStatus read 0x%x\n", ret); 3001 break; 3002 3003 case HltClk: 3004 ret = s->clock_enabled; 3005 DPRINTF("HltClk read 0x%x\n", ret); 3006 break; 3007 3008 case PCIRevisionID: 3009 ret = RTL8139_PCI_REVID; 3010 DPRINTF("PCI Revision ID read 0x%x\n", ret); 3011 break; 3012 3013 case TxThresh: 3014 ret = s->TxThresh; 3015 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret); 3016 break; 3017 3018 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ 3019 ret = s->TxConfig >> 24; 3020 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); 3021 break; 3022 3023 default: 3024 DPRINTF("not implemented read(b) addr=0x%x\n", addr); 3025 ret = 0; 3026 break; 3027 } 3028 3029 return ret; 3030 } 3031 3032 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) 3033 { 3034 RTL8139State *s = opaque; 3035 uint32_t ret; 3036 3037 switch (addr) 3038 { 3039 case IntrMask: 3040 ret = rtl8139_IntrMask_read(s); 3041 break; 3042 3043 case IntrStatus: 3044 ret = rtl8139_IntrStatus_read(s); 3045 break; 3046 3047 case MultiIntr: 3048 ret = rtl8139_MultiIntr_read(s); 3049 break; 3050 3051 case RxBufPtr: 3052 ret = rtl8139_RxBufPtr_read(s); 3053 break; 3054 3055 case RxBufAddr: 3056 ret = rtl8139_RxBufAddr_read(s); 3057 break; 3058 3059 case BasicModeCtrl: 3060 ret = rtl8139_BasicModeCtrl_read(s); 3061 break; 3062 case BasicModeStatus: 3063 ret = rtl8139_BasicModeStatus_read(s); 3064 break; 3065 case NWayAdvert: 3066 ret = s->NWayAdvert; 3067 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret); 3068 break; 3069 case NWayLPAR: 3070 ret = s->NWayLPAR; 3071 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret); 3072 break; 3073 case NWayExpansion: 3074 ret = s->NWayExpansion; 3075 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret); 3076 break; 3077 3078 case CpCmd: 3079 ret = rtl8139_CpCmd_read(s); 3080 break; 3081 3082 case IntrMitigate: 3083 ret = rtl8139_IntrMitigate_read(s); 3084 break; 3085 3086 case TxSummary: 3087 ret = rtl8139_TSAD_read(s); 3088 break; 3089 3090 case CSCR: 3091 ret = rtl8139_CSCR_read(s); 3092 break; 3093 3094 default: 3095 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); 3096 3097 ret = rtl8139_io_readb(opaque, addr); 3098 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3099 3100 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); 3101 break; 3102 } 3103 3104 return ret; 3105 } 3106 3107 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) 3108 { 3109 RTL8139State *s = opaque; 3110 uint32_t ret; 3111 3112 switch (addr) 3113 { 3114 case RxMissed: 3115 ret = s->RxMissed; 3116 3117 DPRINTF("RxMissed read val=0x%08x\n", ret); 3118 break; 3119 3120 case TxConfig: 3121 ret = rtl8139_TxConfig_read(s); 3122 break; 3123 3124 case RxConfig: 3125 ret = rtl8139_RxConfig_read(s); 3126 break; 3127 3128 case TxStatus0 ... TxStatus0+4*4-1: 3129 ret = rtl8139_TxStatus_read(s, addr-TxStatus0); 3130 break; 3131 3132 case TxAddr0 ... TxAddr0+4*4-1: 3133 ret = rtl8139_TxAddr_read(s, addr-TxAddr0); 3134 break; 3135 3136 case RxBuf: 3137 ret = rtl8139_RxBuf_read(s); 3138 break; 3139 3140 case RxRingAddrLO: 3141 ret = s->RxRingAddrLO; 3142 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret); 3143 break; 3144 3145 case RxRingAddrHI: 3146 ret = s->RxRingAddrHI; 3147 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret); 3148 break; 3149 3150 case Timer: 3151 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base, 3152 PCI_FREQUENCY, get_ticks_per_sec()); 3153 DPRINTF("TCTR Timer read val=0x%08x\n", ret); 3154 break; 3155 3156 case FlashReg: 3157 ret = s->TimerInt; 3158 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret); 3159 break; 3160 3161 default: 3162 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); 3163 3164 ret = rtl8139_io_readb(opaque, addr); 3165 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3166 ret |= rtl8139_io_readb(opaque, addr + 2) << 16; 3167 ret |= rtl8139_io_readb(opaque, addr + 3) << 24; 3168 3169 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret); 3170 break; 3171 } 3172 3173 return ret; 3174 } 3175 3176 /* */ 3177 3178 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) 3179 { 3180 rtl8139_io_writeb(opaque, addr & 0xFF, val); 3181 } 3182 3183 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val) 3184 { 3185 rtl8139_io_writew(opaque, addr & 0xFF, val); 3186 } 3187 3188 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 3189 { 3190 rtl8139_io_writel(opaque, addr & 0xFF, val); 3191 } 3192 3193 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr) 3194 { 3195 return rtl8139_io_readb(opaque, addr & 0xFF); 3196 } 3197 3198 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr) 3199 { 3200 return rtl8139_io_readw(opaque, addr & 0xFF); 3201 } 3202 3203 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr) 3204 { 3205 return rtl8139_io_readl(opaque, addr & 0xFF); 3206 } 3207 3208 /* */ 3209 3210 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) 3211 { 3212 rtl8139_io_writeb(opaque, addr & 0xFF, val); 3213 } 3214 3215 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) 3216 { 3217 rtl8139_io_writew(opaque, addr & 0xFF, val); 3218 } 3219 3220 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) 3221 { 3222 rtl8139_io_writel(opaque, addr & 0xFF, val); 3223 } 3224 3225 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr) 3226 { 3227 return rtl8139_io_readb(opaque, addr & 0xFF); 3228 } 3229 3230 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr) 3231 { 3232 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF); 3233 return val; 3234 } 3235 3236 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr) 3237 { 3238 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF); 3239 return val; 3240 } 3241 3242 static int rtl8139_post_load(void *opaque, int version_id) 3243 { 3244 RTL8139State* s = opaque; 3245 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); 3246 if (version_id < 4) { 3247 s->cplus_enabled = s->CpCmd != 0; 3248 } 3249 3250 return 0; 3251 } 3252 3253 static bool rtl8139_hotplug_ready_needed(void *opaque) 3254 { 3255 return qdev_machine_modified(); 3256 } 3257 3258 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ 3259 .name = "rtl8139/hotplug_ready", 3260 .version_id = 1, 3261 .minimum_version_id = 1, 3262 .minimum_version_id_old = 1, 3263 .fields = (VMStateField []) { 3264 VMSTATE_END_OF_LIST() 3265 } 3266 }; 3267 3268 static void rtl8139_pre_save(void *opaque) 3269 { 3270 RTL8139State* s = opaque; 3271 int64_t current_time = qemu_get_clock_ns(vm_clock); 3272 3273 /* set IntrStatus correctly */ 3274 rtl8139_set_next_tctr_time(s, current_time); 3275 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY, 3276 get_ticks_per_sec()); 3277 s->rtl8139_mmio_io_addr_dummy = 0; 3278 } 3279 3280 static const VMStateDescription vmstate_rtl8139 = { 3281 .name = "rtl8139", 3282 .version_id = 4, 3283 .minimum_version_id = 3, 3284 .minimum_version_id_old = 3, 3285 .post_load = rtl8139_post_load, 3286 .pre_save = rtl8139_pre_save, 3287 .fields = (VMStateField []) { 3288 VMSTATE_PCI_DEVICE(dev, RTL8139State), 3289 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6), 3290 VMSTATE_BUFFER(mult, RTL8139State), 3291 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4), 3292 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4), 3293 3294 VMSTATE_UINT32(RxBuf, RTL8139State), 3295 VMSTATE_UINT32(RxBufferSize, RTL8139State), 3296 VMSTATE_UINT32(RxBufPtr, RTL8139State), 3297 VMSTATE_UINT32(RxBufAddr, RTL8139State), 3298 3299 VMSTATE_UINT16(IntrStatus, RTL8139State), 3300 VMSTATE_UINT16(IntrMask, RTL8139State), 3301 3302 VMSTATE_UINT32(TxConfig, RTL8139State), 3303 VMSTATE_UINT32(RxConfig, RTL8139State), 3304 VMSTATE_UINT32(RxMissed, RTL8139State), 3305 VMSTATE_UINT16(CSCR, RTL8139State), 3306 3307 VMSTATE_UINT8(Cfg9346, RTL8139State), 3308 VMSTATE_UINT8(Config0, RTL8139State), 3309 VMSTATE_UINT8(Config1, RTL8139State), 3310 VMSTATE_UINT8(Config3, RTL8139State), 3311 VMSTATE_UINT8(Config4, RTL8139State), 3312 VMSTATE_UINT8(Config5, RTL8139State), 3313 3314 VMSTATE_UINT8(clock_enabled, RTL8139State), 3315 VMSTATE_UINT8(bChipCmdState, RTL8139State), 3316 3317 VMSTATE_UINT16(MultiIntr, RTL8139State), 3318 3319 VMSTATE_UINT16(BasicModeCtrl, RTL8139State), 3320 VMSTATE_UINT16(BasicModeStatus, RTL8139State), 3321 VMSTATE_UINT16(NWayAdvert, RTL8139State), 3322 VMSTATE_UINT16(NWayLPAR, RTL8139State), 3323 VMSTATE_UINT16(NWayExpansion, RTL8139State), 3324 3325 VMSTATE_UINT16(CpCmd, RTL8139State), 3326 VMSTATE_UINT8(TxThresh, RTL8139State), 3327 3328 VMSTATE_UNUSED(4), 3329 VMSTATE_MACADDR(conf.macaddr, RTL8139State), 3330 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), 3331 3332 VMSTATE_UINT32(currTxDesc, RTL8139State), 3333 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), 3334 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), 3335 VMSTATE_UINT32(RxRingAddrLO, RTL8139State), 3336 VMSTATE_UINT32(RxRingAddrHI, RTL8139State), 3337 3338 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), 3339 VMSTATE_INT32(eeprom.mode, RTL8139State), 3340 VMSTATE_UINT32(eeprom.tick, RTL8139State), 3341 VMSTATE_UINT8(eeprom.address, RTL8139State), 3342 VMSTATE_UINT16(eeprom.input, RTL8139State), 3343 VMSTATE_UINT16(eeprom.output, RTL8139State), 3344 3345 VMSTATE_UINT8(eeprom.eecs, RTL8139State), 3346 VMSTATE_UINT8(eeprom.eesk, RTL8139State), 3347 VMSTATE_UINT8(eeprom.eedi, RTL8139State), 3348 VMSTATE_UINT8(eeprom.eedo, RTL8139State), 3349 3350 VMSTATE_UINT32(TCTR, RTL8139State), 3351 VMSTATE_UINT32(TimerInt, RTL8139State), 3352 VMSTATE_INT64(TCTR_base, RTL8139State), 3353 3354 VMSTATE_STRUCT(tally_counters, RTL8139State, 0, 3355 vmstate_tally_counters, RTL8139TallyCounters), 3356 3357 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4), 3358 VMSTATE_END_OF_LIST() 3359 }, 3360 .subsections = (VMStateSubsection []) { 3361 { 3362 .vmsd = &vmstate_rtl8139_hotplug_ready, 3363 .needed = rtl8139_hotplug_ready_needed, 3364 }, { 3365 /* empty */ 3366 } 3367 } 3368 }; 3369 3370 /***********************************************************/ 3371 /* PCI RTL8139 definitions */ 3372 3373 static const MemoryRegionPortio rtl8139_portio[] = { 3374 { 0, 0x100, 1, .read = rtl8139_ioport_readb, }, 3375 { 0, 0x100, 1, .write = rtl8139_ioport_writeb, }, 3376 { 0, 0x100, 2, .read = rtl8139_ioport_readw, }, 3377 { 0, 0x100, 2, .write = rtl8139_ioport_writew, }, 3378 { 0, 0x100, 4, .read = rtl8139_ioport_readl, }, 3379 { 0, 0x100, 4, .write = rtl8139_ioport_writel, }, 3380 PORTIO_END_OF_LIST() 3381 }; 3382 3383 static const MemoryRegionOps rtl8139_io_ops = { 3384 .old_portio = rtl8139_portio, 3385 .endianness = DEVICE_LITTLE_ENDIAN, 3386 }; 3387 3388 static const MemoryRegionOps rtl8139_mmio_ops = { 3389 .old_mmio = { 3390 .read = { 3391 rtl8139_mmio_readb, 3392 rtl8139_mmio_readw, 3393 rtl8139_mmio_readl, 3394 }, 3395 .write = { 3396 rtl8139_mmio_writeb, 3397 rtl8139_mmio_writew, 3398 rtl8139_mmio_writel, 3399 }, 3400 }, 3401 .endianness = DEVICE_LITTLE_ENDIAN, 3402 }; 3403 3404 static void rtl8139_timer(void *opaque) 3405 { 3406 RTL8139State *s = opaque; 3407 3408 if (!s->clock_enabled) 3409 { 3410 DPRINTF(">>> timer: clock is not running\n"); 3411 return; 3412 } 3413 3414 s->IntrStatus |= PCSTimeout; 3415 rtl8139_update_irq(s); 3416 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); 3417 } 3418 3419 static void rtl8139_cleanup(VLANClientState *nc) 3420 { 3421 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque; 3422 3423 s->nic = NULL; 3424 } 3425 3426 static int pci_rtl8139_uninit(PCIDevice *dev) 3427 { 3428 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev); 3429 3430 memory_region_destroy(&s->bar_io); 3431 memory_region_destroy(&s->bar_mem); 3432 if (s->cplus_txbuffer) { 3433 g_free(s->cplus_txbuffer); 3434 s->cplus_txbuffer = NULL; 3435 } 3436 qemu_del_timer(s->timer); 3437 qemu_free_timer(s->timer); 3438 qemu_del_vlan_client(&s->nic->nc); 3439 return 0; 3440 } 3441 3442 static NetClientInfo net_rtl8139_info = { 3443 .type = NET_CLIENT_TYPE_NIC, 3444 .size = sizeof(NICState), 3445 .can_receive = rtl8139_can_receive, 3446 .receive = rtl8139_receive, 3447 .cleanup = rtl8139_cleanup, 3448 }; 3449 3450 static int pci_rtl8139_init(PCIDevice *dev) 3451 { 3452 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev); 3453 uint8_t *pci_conf; 3454 3455 pci_conf = s->dev.config; 3456 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 3457 /* TODO: start of capability list, but no capability 3458 * list bit in status register, and offset 0xdc seems unused. */ 3459 pci_conf[PCI_CAPABILITY_LIST] = 0xdc; 3460 3461 memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100); 3462 memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100); 3463 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); 3464 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); 3465 3466 qemu_macaddr_default_if_unset(&s->conf.macaddr); 3467 3468 /* prepare eeprom */ 3469 s->eeprom.contents[0] = 0x8129; 3470 #if 1 3471 /* PCI vendor and device ID should be mirrored here */ 3472 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; 3473 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; 3474 #endif 3475 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; 3476 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; 3477 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; 3478 3479 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, 3480 object_get_typename(OBJECT(dev)), dev->qdev.id, s); 3481 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); 3482 3483 s->cplus_txbuffer = NULL; 3484 s->cplus_txbuffer_len = 0; 3485 s->cplus_txbuffer_offset = 0; 3486 3487 s->TimerExpire = 0; 3488 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s); 3489 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock)); 3490 3491 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0"); 3492 3493 return 0; 3494 } 3495 3496 static Property rtl8139_properties[] = { 3497 DEFINE_NIC_PROPERTIES(RTL8139State, conf), 3498 DEFINE_PROP_END_OF_LIST(), 3499 }; 3500 3501 static void rtl8139_class_init(ObjectClass *klass, void *data) 3502 { 3503 DeviceClass *dc = DEVICE_CLASS(klass); 3504 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3505 3506 k->init = pci_rtl8139_init; 3507 k->exit = pci_rtl8139_uninit; 3508 k->romfile = "pxe-rtl8139.rom"; 3509 k->vendor_id = PCI_VENDOR_ID_REALTEK; 3510 k->device_id = PCI_DEVICE_ID_REALTEK_8139; 3511 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ 3512 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 3513 dc->reset = rtl8139_reset; 3514 dc->vmsd = &vmstate_rtl8139; 3515 dc->props = rtl8139_properties; 3516 } 3517 3518 static TypeInfo rtl8139_info = { 3519 .name = "rtl8139", 3520 .parent = TYPE_PCI_DEVICE, 3521 .instance_size = sizeof(RTL8139State), 3522 .class_init = rtl8139_class_init, 3523 }; 3524 3525 static void rtl8139_register_types(void) 3526 { 3527 type_register_static(&rtl8139_info); 3528 } 3529 3530 type_init(rtl8139_register_types) 3531