1 /* 2 * Faraday FTGMAC100 Gigabit Ethernet 3 * 4 * Copyright (C) 2016-2017, IBM Corporation. 5 * 6 * Based on Coldfire Fast Ethernet Controller emulation. 7 * 8 * Copyright (c) 2007 CodeSourcery. 9 * 10 * This code is licensed under the GPL version 2 or later. See the 11 * COPYING file in the top-level directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "hw/irq.h" 16 #include "hw/net/ftgmac100.h" 17 #include "sysemu/dma.h" 18 #include "qapi/error.h" 19 #include "qemu/log.h" 20 #include "qemu/module.h" 21 #include "net/checksum.h" 22 #include "net/eth.h" 23 #include "hw/net/mii.h" 24 #include "hw/qdev-properties.h" 25 #include "migration/vmstate.h" 26 27 /* For crc32 */ 28 #include <zlib.h> 29 30 /* 31 * FTGMAC100 registers 32 */ 33 #define FTGMAC100_ISR 0x00 34 #define FTGMAC100_IER 0x04 35 #define FTGMAC100_MAC_MADR 0x08 36 #define FTGMAC100_MAC_LADR 0x0c 37 #define FTGMAC100_MATH0 0x10 38 #define FTGMAC100_MATH1 0x14 39 #define FTGMAC100_NPTXPD 0x18 40 #define FTGMAC100_RXPD 0x1C 41 #define FTGMAC100_NPTXR_BADR 0x20 42 #define FTGMAC100_RXR_BADR 0x24 43 #define FTGMAC100_HPTXPD 0x28 44 #define FTGMAC100_HPTXR_BADR 0x2c 45 #define FTGMAC100_ITC 0x30 46 #define FTGMAC100_APTC 0x34 47 #define FTGMAC100_DBLAC 0x38 48 #define FTGMAC100_REVR 0x40 49 #define FTGMAC100_FEAR1 0x44 50 #define FTGMAC100_RBSR 0x4c 51 #define FTGMAC100_TPAFCR 0x48 52 53 #define FTGMAC100_MACCR 0x50 54 #define FTGMAC100_MACSR 0x54 55 #define FTGMAC100_PHYCR 0x60 56 #define FTGMAC100_PHYDATA 0x64 57 #define FTGMAC100_FCR 0x68 58 59 /* 60 * Interrupt status register & interrupt enable register 61 */ 62 #define FTGMAC100_INT_RPKT_BUF (1 << 0) 63 #define FTGMAC100_INT_RPKT_FIFO (1 << 1) 64 #define FTGMAC100_INT_NO_RXBUF (1 << 2) 65 #define FTGMAC100_INT_RPKT_LOST (1 << 3) 66 #define FTGMAC100_INT_XPKT_ETH (1 << 4) 67 #define FTGMAC100_INT_XPKT_FIFO (1 << 5) 68 #define FTGMAC100_INT_NO_NPTXBUF (1 << 6) 69 #define FTGMAC100_INT_XPKT_LOST (1 << 7) 70 #define FTGMAC100_INT_AHB_ERR (1 << 8) 71 #define FTGMAC100_INT_PHYSTS_CHG (1 << 9) 72 #define FTGMAC100_INT_NO_HPTXBUF (1 << 10) 73 74 /* 75 * Automatic polling timer control register 76 */ 77 #define FTGMAC100_APTC_RXPOLL_CNT(x) ((x) & 0xf) 78 #define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) 79 #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) >> 8) & 0xf) 80 #define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) 81 82 /* 83 * DMA burst length and arbitration control register 84 */ 85 #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) >> 8) & 0x3) 86 #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) >> 10) & 0x3) 87 #define FTGMAC100_DBLAC_RXDES_SIZE(x) ((((x) >> 12) & 0xf) * 8) 88 #define FTGMAC100_DBLAC_TXDES_SIZE(x) ((((x) >> 16) & 0xf) * 8) 89 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) >> 20) & 0x7) 90 #define FTGMAC100_DBLAC_IFG_INC (1 << 23) 91 92 /* 93 * PHY control register 94 */ 95 #define FTGMAC100_PHYCR_MIIRD (1 << 26) 96 #define FTGMAC100_PHYCR_MIIWR (1 << 27) 97 98 #define FTGMAC100_PHYCR_DEV(x) (((x) >> 16) & 0x1f) 99 #define FTGMAC100_PHYCR_REG(x) (((x) >> 21) & 0x1f) 100 101 /* 102 * PHY data register 103 */ 104 #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) 105 #define FTGMAC100_PHYDATA_MIIRDATA(x) (((x) >> 16) & 0xffff) 106 107 /* 108 * PHY control register - New MDC/MDIO interface 109 */ 110 #define FTGMAC100_PHYCR_NEW_DATA(x) (((x) >> 16) & 0xffff) 111 #define FTGMAC100_PHYCR_NEW_FIRE (1 << 15) 112 #define FTGMAC100_PHYCR_NEW_ST_22 (1 << 12) 113 #define FTGMAC100_PHYCR_NEW_OP(x) (((x) >> 10) & 3) 114 #define FTGMAC100_PHYCR_NEW_OP_WRITE 0x1 115 #define FTGMAC100_PHYCR_NEW_OP_READ 0x2 116 #define FTGMAC100_PHYCR_NEW_DEV(x) (((x) >> 5) & 0x1f) 117 #define FTGMAC100_PHYCR_NEW_REG(x) ((x) & 0x1f) 118 119 /* 120 * Feature Register 121 */ 122 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE (1 << 31) 123 124 /* 125 * MAC control register 126 */ 127 #define FTGMAC100_MACCR_TXDMA_EN (1 << 0) 128 #define FTGMAC100_MACCR_RXDMA_EN (1 << 1) 129 #define FTGMAC100_MACCR_TXMAC_EN (1 << 2) 130 #define FTGMAC100_MACCR_RXMAC_EN (1 << 3) 131 #define FTGMAC100_MACCR_RM_VLAN (1 << 4) 132 #define FTGMAC100_MACCR_HPTXR_EN (1 << 5) 133 #define FTGMAC100_MACCR_LOOP_EN (1 << 6) 134 #define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7) 135 #define FTGMAC100_MACCR_FULLDUP (1 << 8) 136 #define FTGMAC100_MACCR_GIGA_MODE (1 << 9) 137 #define FTGMAC100_MACCR_CRC_APD (1 << 10) /* not needed */ 138 #define FTGMAC100_MACCR_RX_RUNT (1 << 12) 139 #define FTGMAC100_MACCR_JUMBO_LF (1 << 13) 140 #define FTGMAC100_MACCR_RX_ALL (1 << 14) 141 #define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15) 142 #define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) 143 #define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) 144 #define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) 145 #define FTGMAC100_MACCR_FAST_MODE (1 << 19) 146 #define FTGMAC100_MACCR_SW_RST (1 << 31) 147 148 /* 149 * Transmit descriptor 150 */ 151 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) 152 #define FTGMAC100_TXDES0_EDOTR (1 << 15) 153 #define FTGMAC100_TXDES0_CRC_ERR (1 << 19) 154 #define FTGMAC100_TXDES0_LTS (1 << 28) 155 #define FTGMAC100_TXDES0_FTS (1 << 29) 156 #define FTGMAC100_TXDES0_EDOTR_ASPEED (1 << 30) 157 #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31) 158 159 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) 160 #define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16) 161 #define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17) 162 #define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18) 163 #define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19) 164 #define FTGMAC100_TXDES1_LLC (1 << 22) 165 #define FTGMAC100_TXDES1_TX2FIC (1 << 30) 166 #define FTGMAC100_TXDES1_TXIC (1 << 31) 167 168 /* 169 * Receive descriptor 170 */ 171 #define FTGMAC100_RXDES0_VDBC 0x3fff 172 #define FTGMAC100_RXDES0_EDORR (1 << 15) 173 #define FTGMAC100_RXDES0_MULTICAST (1 << 16) 174 #define FTGMAC100_RXDES0_BROADCAST (1 << 17) 175 #define FTGMAC100_RXDES0_RX_ERR (1 << 18) 176 #define FTGMAC100_RXDES0_CRC_ERR (1 << 19) 177 #define FTGMAC100_RXDES0_FTL (1 << 20) 178 #define FTGMAC100_RXDES0_RUNT (1 << 21) 179 #define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22) 180 #define FTGMAC100_RXDES0_FIFO_FULL (1 << 23) 181 #define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24) 182 #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25) 183 #define FTGMAC100_RXDES0_LRS (1 << 28) 184 #define FTGMAC100_RXDES0_FRS (1 << 29) 185 #define FTGMAC100_RXDES0_EDORR_ASPEED (1 << 30) 186 #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31) 187 188 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff 189 #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) 190 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) 191 #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) 192 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) 193 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) 194 #define FTGMAC100_RXDES1_LLC (1 << 22) 195 #define FTGMAC100_RXDES1_DF (1 << 23) 196 #define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24) 197 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25) 198 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) 199 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) 200 201 /* 202 * Receive and transmit Buffer Descriptor 203 */ 204 typedef struct { 205 uint32_t des0; 206 uint32_t des1; 207 uint32_t des2; /* not used by HW */ 208 uint32_t des3; 209 } FTGMAC100Desc; 210 211 #define FTGMAC100_DESC_ALIGNMENT 16 212 213 /* 214 * Specific RTL8211E MII Registers 215 */ 216 #define RTL8211E_MII_PHYCR 16 /* PHY Specific Control */ 217 #define RTL8211E_MII_PHYSR 17 /* PHY Specific Status */ 218 #define RTL8211E_MII_INER 18 /* Interrupt Enable */ 219 #define RTL8211E_MII_INSR 19 /* Interrupt Status */ 220 #define RTL8211E_MII_RXERC 24 /* Receive Error Counter */ 221 #define RTL8211E_MII_LDPSR 27 /* Link Down Power Saving */ 222 #define RTL8211E_MII_EPAGSR 30 /* Extension Page Select */ 223 #define RTL8211E_MII_PAGSEL 31 /* Page Select */ 224 225 /* 226 * RTL8211E Interrupt Status 227 */ 228 #define PHY_INT_AUTONEG_ERROR (1 << 15) 229 #define PHY_INT_PAGE_RECV (1 << 12) 230 #define PHY_INT_AUTONEG_COMPLETE (1 << 11) 231 #define PHY_INT_LINK_STATUS (1 << 10) 232 #define PHY_INT_ERROR (1 << 9) 233 #define PHY_INT_DOWN (1 << 8) 234 #define PHY_INT_JABBER (1 << 0) 235 236 /* 237 * Max frame size for the receiving buffer 238 */ 239 #define FTGMAC100_MAX_FRAME_SIZE 9220 240 241 /* 242 * Limits depending on the type of the frame 243 * 244 * 9216 for Jumbo frames (+ 4 for VLAN) 245 * 1518 for other frames (+ 4 for VLAN) 246 */ 247 static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto) 248 { 249 int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518); 250 251 return max + (proto == ETH_P_VLAN ? 4 : 0); 252 } 253 254 static void ftgmac100_update_irq(FTGMAC100State *s) 255 { 256 qemu_set_irq(s->irq, s->isr & s->ier); 257 } 258 259 /* 260 * The MII phy could raise a GPIO to the processor which in turn 261 * could be handled as an interrpt by the OS. 262 * For now we don't handle any GPIO/interrupt line, so the OS will 263 * have to poll for the PHY status. 264 */ 265 static void phy_update_irq(FTGMAC100State *s) 266 { 267 ftgmac100_update_irq(s); 268 } 269 270 static void phy_update_link(FTGMAC100State *s) 271 { 272 /* Autonegotiation status mirrors link status. */ 273 if (qemu_get_queue(s->nic)->link_down) { 274 s->phy_status &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); 275 s->phy_int |= PHY_INT_DOWN; 276 } else { 277 s->phy_status |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); 278 s->phy_int |= PHY_INT_AUTONEG_COMPLETE; 279 } 280 phy_update_irq(s); 281 } 282 283 static void ftgmac100_set_link(NetClientState *nc) 284 { 285 phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc))); 286 } 287 288 static void phy_reset(FTGMAC100State *s) 289 { 290 s->phy_status = (MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | 291 MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_MFPS | 292 MII_BMSR_AN_COMP | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST | 293 MII_BMSR_EXTCAP); 294 s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000); 295 s->phy_advertise = (MII_ANAR_PAUSE_ASYM | MII_ANAR_PAUSE | MII_ANAR_TXFD | 296 MII_ANAR_TX | MII_ANAR_10FD | MII_ANAR_10 | 297 MII_ANAR_CSMACD); 298 s->phy_int_mask = 0; 299 s->phy_int = 0; 300 } 301 302 static uint16_t do_phy_read(FTGMAC100State *s, uint8_t reg) 303 { 304 uint16_t val; 305 306 switch (reg) { 307 case MII_BMCR: /* Basic Control */ 308 val = s->phy_control; 309 break; 310 case MII_BMSR: /* Basic Status */ 311 val = s->phy_status; 312 break; 313 case MII_PHYID1: /* ID1 */ 314 val = RTL8211E_PHYID1; 315 break; 316 case MII_PHYID2: /* ID2 */ 317 val = RTL8211E_PHYID2; 318 break; 319 case MII_ANAR: /* Auto-neg advertisement */ 320 val = s->phy_advertise; 321 break; 322 case MII_ANLPAR: /* Auto-neg Link Partner Ability */ 323 val = (MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | MII_ANLPAR_TXFD | 324 MII_ANLPAR_TX | MII_ANLPAR_10FD | MII_ANLPAR_10 | 325 MII_ANLPAR_CSMACD); 326 break; 327 case MII_ANER: /* Auto-neg Expansion */ 328 val = MII_ANER_NWAY; 329 break; 330 case MII_CTRL1000: /* 1000BASE-T control */ 331 val = (MII_CTRL1000_HALF | MII_CTRL1000_FULL); 332 break; 333 case MII_STAT1000: /* 1000BASE-T status */ 334 val = MII_STAT1000_FULL; 335 break; 336 case RTL8211E_MII_INSR: /* Interrupt status. */ 337 val = s->phy_int; 338 s->phy_int = 0; 339 phy_update_irq(s); 340 break; 341 case RTL8211E_MII_INER: /* Interrupt enable */ 342 val = s->phy_int_mask; 343 break; 344 case RTL8211E_MII_PHYCR: 345 case RTL8211E_MII_PHYSR: 346 case RTL8211E_MII_RXERC: 347 case RTL8211E_MII_LDPSR: 348 case RTL8211E_MII_EPAGSR: 349 case RTL8211E_MII_PAGSEL: 350 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", 351 __func__, reg); 352 val = 0; 353 break; 354 default: 355 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", 356 __func__, reg); 357 val = 0; 358 break; 359 } 360 361 return val; 362 } 363 364 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | \ 365 MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \ 366 MII_BMCR_FD | MII_BMCR_CTST) 367 #define MII_ANAR_MASK 0x2d7f 368 369 static void do_phy_write(FTGMAC100State *s, uint8_t reg, uint16_t val) 370 { 371 switch (reg) { 372 case MII_BMCR: /* Basic Control */ 373 if (val & MII_BMCR_RESET) { 374 phy_reset(s); 375 } else { 376 s->phy_control = val & MII_BMCR_MASK; 377 /* Complete autonegotiation immediately. */ 378 if (val & MII_BMCR_AUTOEN) { 379 s->phy_status |= MII_BMSR_AN_COMP; 380 } 381 } 382 break; 383 case MII_ANAR: /* Auto-neg advertisement */ 384 s->phy_advertise = (val & MII_ANAR_MASK) | MII_ANAR_TX; 385 break; 386 case RTL8211E_MII_INER: /* Interrupt enable */ 387 s->phy_int_mask = val & 0xff; 388 phy_update_irq(s); 389 break; 390 case RTL8211E_MII_PHYCR: 391 case RTL8211E_MII_PHYSR: 392 case RTL8211E_MII_RXERC: 393 case RTL8211E_MII_LDPSR: 394 case RTL8211E_MII_EPAGSR: 395 case RTL8211E_MII_PAGSEL: 396 qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n", 397 __func__, reg); 398 break; 399 default: 400 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n", 401 __func__, reg); 402 break; 403 } 404 } 405 406 static void do_phy_new_ctl(FTGMAC100State *s) 407 { 408 uint8_t reg; 409 uint16_t data; 410 411 if (!(s->phycr & FTGMAC100_PHYCR_NEW_ST_22)) { 412 qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__); 413 return; 414 } 415 416 /* Nothing to do */ 417 if (!(s->phycr & FTGMAC100_PHYCR_NEW_FIRE)) { 418 return; 419 } 420 421 reg = FTGMAC100_PHYCR_NEW_REG(s->phycr); 422 data = FTGMAC100_PHYCR_NEW_DATA(s->phycr); 423 424 switch (FTGMAC100_PHYCR_NEW_OP(s->phycr)) { 425 case FTGMAC100_PHYCR_NEW_OP_WRITE: 426 do_phy_write(s, reg, data); 427 break; 428 case FTGMAC100_PHYCR_NEW_OP_READ: 429 s->phydata = do_phy_read(s, reg) & 0xffff; 430 break; 431 default: 432 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n", 433 __func__, s->phycr); 434 } 435 436 s->phycr &= ~FTGMAC100_PHYCR_NEW_FIRE; 437 } 438 439 static void do_phy_ctl(FTGMAC100State *s) 440 { 441 uint8_t reg = FTGMAC100_PHYCR_REG(s->phycr); 442 443 if (s->phycr & FTGMAC100_PHYCR_MIIWR) { 444 do_phy_write(s, reg, s->phydata & 0xffff); 445 s->phycr &= ~FTGMAC100_PHYCR_MIIWR; 446 } else if (s->phycr & FTGMAC100_PHYCR_MIIRD) { 447 s->phydata = do_phy_read(s, reg) << 16; 448 s->phycr &= ~FTGMAC100_PHYCR_MIIRD; 449 } else { 450 qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n", 451 __func__, s->phycr); 452 } 453 } 454 455 static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr) 456 { 457 if (dma_memory_read(&address_space_memory, addr, 458 bd, sizeof(*bd), MEMTXATTRS_UNSPECIFIED)) { 459 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x%" 460 HWADDR_PRIx "\n", __func__, addr); 461 return -1; 462 } 463 bd->des0 = le32_to_cpu(bd->des0); 464 bd->des1 = le32_to_cpu(bd->des1); 465 bd->des2 = le32_to_cpu(bd->des2); 466 bd->des3 = le32_to_cpu(bd->des3); 467 return 0; 468 } 469 470 static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr) 471 { 472 FTGMAC100Desc lebd; 473 474 lebd.des0 = cpu_to_le32(bd->des0); 475 lebd.des1 = cpu_to_le32(bd->des1); 476 lebd.des2 = cpu_to_le32(bd->des2); 477 lebd.des3 = cpu_to_le32(bd->des3); 478 if (dma_memory_write(&address_space_memory, addr, 479 &lebd, sizeof(lebd), MEMTXATTRS_UNSPECIFIED)) { 480 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0x%" 481 HWADDR_PRIx "\n", __func__, addr); 482 return -1; 483 } 484 return 0; 485 } 486 487 static int ftgmac100_insert_vlan(FTGMAC100State *s, int frame_size, 488 uint8_t vlan_tci) 489 { 490 uint8_t *vlan_hdr = s->frame + (ETH_ALEN * 2); 491 uint8_t *payload = vlan_hdr + sizeof(struct vlan_header); 492 493 if (frame_size < sizeof(struct eth_header)) { 494 qemu_log_mask(LOG_GUEST_ERROR, 495 "%s: frame too small for VLAN insertion : %d bytes\n", 496 __func__, frame_size); 497 s->isr |= FTGMAC100_INT_XPKT_LOST; 498 goto out; 499 } 500 501 if (frame_size + sizeof(struct vlan_header) > sizeof(s->frame)) { 502 qemu_log_mask(LOG_GUEST_ERROR, 503 "%s: frame too big : %d bytes\n", 504 __func__, frame_size); 505 s->isr |= FTGMAC100_INT_XPKT_LOST; 506 frame_size -= sizeof(struct vlan_header); 507 } 508 509 memmove(payload, vlan_hdr, frame_size - (ETH_ALEN * 2)); 510 stw_be_p(vlan_hdr, ETH_P_VLAN); 511 stw_be_p(vlan_hdr + 2, vlan_tci); 512 frame_size += sizeof(struct vlan_header); 513 514 out: 515 return frame_size; 516 } 517 518 static void ftgmac100_do_tx(FTGMAC100State *s, uint64_t tx_ring, 519 uint64_t tx_descriptor) 520 { 521 int frame_size = 0; 522 uint8_t *ptr = s->frame; 523 uint64_t addr = tx_descriptor; 524 uint32_t flags = 0; 525 526 while (1) { 527 FTGMAC100Desc bd; 528 int len; 529 530 if (ftgmac100_read_bd(&bd, addr) || 531 ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0)) { 532 /* Run out of descriptors to transmit. */ 533 s->isr |= FTGMAC100_INT_NO_NPTXBUF; 534 break; 535 } 536 537 /* 538 * record transmit flags as they are valid only on the first 539 * segment 540 */ 541 if (bd.des0 & FTGMAC100_TXDES0_FTS) { 542 flags = bd.des1; 543 } 544 545 len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0); 546 if (!len) { 547 /* 548 * 0 is an invalid size, however the HW does not raise any 549 * interrupt. Flag an error because the guest is buggy. 550 */ 551 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid segment size\n", 552 __func__); 553 } 554 555 if (frame_size + len > sizeof(s->frame)) { 556 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n", 557 __func__, len); 558 s->isr |= FTGMAC100_INT_XPKT_LOST; 559 len = sizeof(s->frame) - frame_size; 560 } 561 562 if (dma_memory_read(&address_space_memory, bd.des3, 563 ptr, len, MEMTXATTRS_UNSPECIFIED)) { 564 qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n", 565 __func__, bd.des3); 566 s->isr |= FTGMAC100_INT_AHB_ERR; 567 break; 568 } 569 570 ptr += len; 571 frame_size += len; 572 if (bd.des0 & FTGMAC100_TXDES0_LTS) { 573 int csum = 0; 574 575 /* Check for VLAN */ 576 if (flags & FTGMAC100_TXDES1_INS_VLANTAG && 577 be16_to_cpu(PKT_GET_ETH_HDR(s->frame)->h_proto) != ETH_P_VLAN) { 578 frame_size = ftgmac100_insert_vlan(s, frame_size, 579 FTGMAC100_TXDES1_VLANTAG_CI(flags)); 580 } 581 582 if (flags & FTGMAC100_TXDES1_IP_CHKSUM) { 583 csum |= CSUM_IP; 584 } 585 if (flags & FTGMAC100_TXDES1_TCP_CHKSUM) { 586 csum |= CSUM_TCP; 587 } 588 if (flags & FTGMAC100_TXDES1_UDP_CHKSUM) { 589 csum |= CSUM_UDP; 590 } 591 if (csum) { 592 net_checksum_calculate(s->frame, frame_size, csum); 593 } 594 595 /* Last buffer in frame. */ 596 qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size); 597 ptr = s->frame; 598 frame_size = 0; 599 s->isr |= FTGMAC100_INT_XPKT_ETH; 600 } 601 602 if (flags & FTGMAC100_TXDES1_TX2FIC) { 603 s->isr |= FTGMAC100_INT_XPKT_FIFO; 604 } 605 bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN; 606 607 /* Write back the modified descriptor. */ 608 ftgmac100_write_bd(&bd, addr); 609 /* Advance to the next descriptor. */ 610 if (bd.des0 & s->txdes0_edotr) { 611 addr = tx_ring; 612 } else { 613 addr += FTGMAC100_DBLAC_TXDES_SIZE(s->dblac); 614 } 615 } 616 617 s->tx_descriptor = addr; 618 619 ftgmac100_update_irq(s); 620 } 621 622 static bool ftgmac100_can_receive(NetClientState *nc) 623 { 624 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc)); 625 FTGMAC100Desc bd; 626 627 if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) 628 != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) { 629 return false; 630 } 631 632 if (ftgmac100_read_bd(&bd, s->rx_descriptor)) { 633 return false; 634 } 635 return !(bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY); 636 } 637 638 /* 639 * This is purely informative. The HW can poll the RW (and RX) ring 640 * buffers for available descriptors but we don't need to trigger a 641 * timer for that in qemu. 642 */ 643 static uint32_t ftgmac100_rxpoll(FTGMAC100State *s) 644 { 645 /* 646 * Polling times : 647 * 648 * Speed TIME_SEL=0 TIME_SEL=1 649 * 650 * 10 51.2 ms 819.2 ms 651 * 100 5.12 ms 81.92 ms 652 * 1000 1.024 ms 16.384 ms 653 */ 654 static const int div[] = { 20, 200, 1000 }; 655 656 uint32_t cnt = 1024 * FTGMAC100_APTC_RXPOLL_CNT(s->aptcr); 657 uint32_t speed = (s->maccr & FTGMAC100_MACCR_FAST_MODE) ? 1 : 0; 658 659 if (s->aptcr & FTGMAC100_APTC_RXPOLL_TIME_SEL) { 660 cnt <<= 4; 661 } 662 663 if (s->maccr & FTGMAC100_MACCR_GIGA_MODE) { 664 speed = 2; 665 } 666 667 return cnt / div[speed]; 668 } 669 670 static void ftgmac100_do_reset(FTGMAC100State *s, bool sw_reset) 671 { 672 /* Reset the FTGMAC100 */ 673 s->isr = 0; 674 s->ier = 0; 675 s->rx_enabled = 0; 676 s->rx_ring = 0; 677 s->rbsr = 0x640; 678 s->rx_descriptor = 0; 679 s->tx_ring = 0; 680 s->tx_descriptor = 0; 681 s->math[0] = 0; 682 s->math[1] = 0; 683 s->itc = 0; 684 s->aptcr = 1; 685 s->dblac = 0x00022f00; 686 s->revr = 0; 687 s->fear1 = 0; 688 s->tpafcr = 0xf1; 689 690 if (sw_reset) { 691 s->maccr &= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FAST_MODE; 692 } else { 693 s->maccr = 0; 694 } 695 696 s->phycr = 0; 697 s->phydata = 0; 698 s->fcr = 0x400; 699 700 /* and the PHY */ 701 phy_reset(s); 702 } 703 704 static void ftgmac100_reset(DeviceState *d) 705 { 706 ftgmac100_do_reset(FTGMAC100(d), false); 707 } 708 709 static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size) 710 { 711 FTGMAC100State *s = FTGMAC100(opaque); 712 713 switch (addr & 0xff) { 714 case FTGMAC100_ISR: 715 return s->isr; 716 case FTGMAC100_IER: 717 return s->ier; 718 case FTGMAC100_MAC_MADR: 719 return (s->conf.macaddr.a[0] << 8) | s->conf.macaddr.a[1]; 720 case FTGMAC100_MAC_LADR: 721 return ((uint32_t) s->conf.macaddr.a[2] << 24) | 722 (s->conf.macaddr.a[3] << 16) | (s->conf.macaddr.a[4] << 8) | 723 s->conf.macaddr.a[5]; 724 case FTGMAC100_MATH0: 725 return s->math[0]; 726 case FTGMAC100_MATH1: 727 return s->math[1]; 728 case FTGMAC100_RXR_BADR: 729 return extract64(s->rx_ring, 0, 32); 730 case FTGMAC100_NPTXR_BADR: 731 return extract64(s->tx_ring, 0, 32); 732 case FTGMAC100_ITC: 733 return s->itc; 734 case FTGMAC100_DBLAC: 735 return s->dblac; 736 case FTGMAC100_REVR: 737 return s->revr; 738 case FTGMAC100_FEAR1: 739 return s->fear1; 740 case FTGMAC100_TPAFCR: 741 return s->tpafcr; 742 case FTGMAC100_FCR: 743 return s->fcr; 744 case FTGMAC100_MACCR: 745 return s->maccr; 746 case FTGMAC100_PHYCR: 747 return s->phycr; 748 case FTGMAC100_PHYDATA: 749 return s->phydata; 750 751 /* We might want to support these one day */ 752 case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */ 753 case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */ 754 case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */ 755 qemu_log_mask(LOG_UNIMP, "%s: read to unimplemented register 0x%" 756 HWADDR_PRIx "\n", __func__, addr); 757 return 0; 758 default: 759 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%" 760 HWADDR_PRIx "\n", __func__, addr); 761 return 0; 762 } 763 } 764 765 static void ftgmac100_write(void *opaque, hwaddr addr, 766 uint64_t value, unsigned size) 767 { 768 FTGMAC100State *s = FTGMAC100(opaque); 769 770 switch (addr & 0xff) { 771 case FTGMAC100_ISR: /* Interrupt status */ 772 s->isr &= ~value; 773 break; 774 case FTGMAC100_IER: /* Interrupt control */ 775 s->ier = value; 776 break; 777 case FTGMAC100_MAC_MADR: /* MAC */ 778 s->conf.macaddr.a[0] = value >> 8; 779 s->conf.macaddr.a[1] = value; 780 break; 781 case FTGMAC100_MAC_LADR: 782 s->conf.macaddr.a[2] = value >> 24; 783 s->conf.macaddr.a[3] = value >> 16; 784 s->conf.macaddr.a[4] = value >> 8; 785 s->conf.macaddr.a[5] = value; 786 break; 787 case FTGMAC100_MATH0: /* Multicast Address Hash Table 0 */ 788 s->math[0] = value; 789 break; 790 case FTGMAC100_MATH1: /* Multicast Address Hash Table 1 */ 791 s->math[1] = value; 792 break; 793 case FTGMAC100_ITC: /* TODO: Interrupt Timer Control */ 794 s->itc = value; 795 break; 796 case FTGMAC100_RXR_BADR: /* Ring buffer address */ 797 if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) { 798 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad RX buffer alignment 0x%" 799 HWADDR_PRIx "\n", __func__, value); 800 return; 801 } 802 s->rx_ring = deposit64(s->rx_ring, 0, 32, value); 803 s->rx_descriptor = deposit64(s->rx_descriptor, 0, 32, value); 804 break; 805 806 case FTGMAC100_RBSR: /* DMA buffer size */ 807 s->rbsr = value; 808 break; 809 810 case FTGMAC100_NPTXR_BADR: /* Transmit buffer address */ 811 if (!QEMU_IS_ALIGNED(value, FTGMAC100_DESC_ALIGNMENT)) { 812 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad TX buffer alignment 0x%" 813 HWADDR_PRIx "\n", __func__, value); 814 return; 815 } 816 s->tx_ring = deposit64(s->tx_ring, 0, 32, value); 817 s->tx_descriptor = deposit64(s->tx_descriptor, 0, 32, value); 818 break; 819 820 case FTGMAC100_NPTXPD: /* Trigger transmit */ 821 if ((s->maccr & (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) 822 == (FTGMAC100_MACCR_TXDMA_EN | FTGMAC100_MACCR_TXMAC_EN)) { 823 /* TODO: high priority tx ring */ 824 ftgmac100_do_tx(s, s->tx_ring, s->tx_descriptor); 825 } 826 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) { 827 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 828 } 829 break; 830 831 case FTGMAC100_RXPD: /* Receive Poll Demand Register */ 832 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) { 833 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 834 } 835 break; 836 837 case FTGMAC100_APTC: /* Automatic polling */ 838 s->aptcr = value; 839 840 if (FTGMAC100_APTC_RXPOLL_CNT(s->aptcr)) { 841 ftgmac100_rxpoll(s); 842 } 843 844 if (FTGMAC100_APTC_TXPOLL_CNT(s->aptcr)) { 845 qemu_log_mask(LOG_UNIMP, "%s: no transmit polling\n", __func__); 846 } 847 break; 848 849 case FTGMAC100_MACCR: /* MAC Device control */ 850 s->maccr = value; 851 if (value & FTGMAC100_MACCR_SW_RST) { 852 ftgmac100_do_reset(s, true); 853 } 854 855 if (ftgmac100_can_receive(qemu_get_queue(s->nic))) { 856 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 857 } 858 break; 859 860 case FTGMAC100_PHYCR: /* PHY Device control */ 861 s->phycr = value; 862 if (s->revr & FTGMAC100_REVR_NEW_MDIO_INTERFACE) { 863 do_phy_new_ctl(s); 864 } else { 865 do_phy_ctl(s); 866 } 867 break; 868 case FTGMAC100_PHYDATA: 869 s->phydata = value & 0xffff; 870 break; 871 case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */ 872 if (FTGMAC100_DBLAC_TXDES_SIZE(value) < sizeof(FTGMAC100Desc)) { 873 qemu_log_mask(LOG_GUEST_ERROR, 874 "%s: transmit descriptor too small: %" PRIx64 875 " bytes\n", __func__, 876 FTGMAC100_DBLAC_TXDES_SIZE(value)); 877 break; 878 } 879 if (FTGMAC100_DBLAC_RXDES_SIZE(value) < sizeof(FTGMAC100Desc)) { 880 qemu_log_mask(LOG_GUEST_ERROR, 881 "%s: receive descriptor too small : %" PRIx64 882 " bytes\n", __func__, 883 FTGMAC100_DBLAC_RXDES_SIZE(value)); 884 break; 885 } 886 s->dblac = value; 887 break; 888 case FTGMAC100_REVR: /* Feature Register */ 889 s->revr = value; 890 break; 891 case FTGMAC100_FEAR1: /* Feature Register 1 */ 892 s->fear1 = value; 893 break; 894 case FTGMAC100_TPAFCR: /* Transmit Priority Arbitration and FIFO Control */ 895 s->tpafcr = value; 896 break; 897 case FTGMAC100_FCR: /* Flow Control */ 898 s->fcr = value; 899 break; 900 901 case FTGMAC100_HPTXPD: /* High Priority Transmit Poll Demand */ 902 case FTGMAC100_HPTXR_BADR: /* High Priority Transmit Ring Base Address */ 903 case FTGMAC100_MACSR: /* MAC Status Register (MACSR) */ 904 qemu_log_mask(LOG_UNIMP, "%s: write to unimplemented register 0x%" 905 HWADDR_PRIx "\n", __func__, addr); 906 break; 907 default: 908 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset 0x%" 909 HWADDR_PRIx "\n", __func__, addr); 910 break; 911 } 912 913 ftgmac100_update_irq(s); 914 } 915 916 static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len) 917 { 918 unsigned mcast_idx; 919 920 if (s->maccr & FTGMAC100_MACCR_RX_ALL) { 921 return 1; 922 } 923 924 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) { 925 case ETH_PKT_BCAST: 926 if (!(s->maccr & FTGMAC100_MACCR_RX_BROADPKT)) { 927 return 0; 928 } 929 break; 930 case ETH_PKT_MCAST: 931 if (!(s->maccr & FTGMAC100_MACCR_RX_MULTIPKT)) { 932 if (!(s->maccr & FTGMAC100_MACCR_HT_MULTI_EN)) { 933 return 0; 934 } 935 936 mcast_idx = net_crc32_le(buf, ETH_ALEN); 937 mcast_idx = (~(mcast_idx >> 2)) & 0x3f; 938 if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) { 939 return 0; 940 } 941 } 942 break; 943 case ETH_PKT_UCAST: 944 if (memcmp(s->conf.macaddr.a, buf, 6)) { 945 return 0; 946 } 947 break; 948 } 949 950 return 1; 951 } 952 953 static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf, 954 size_t len) 955 { 956 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc)); 957 FTGMAC100Desc bd; 958 uint32_t flags = 0; 959 uint64_t addr; 960 uint32_t crc; 961 uint32_t buf_addr; 962 uint8_t *crc_ptr; 963 uint32_t buf_len; 964 size_t size = len; 965 uint32_t first = FTGMAC100_RXDES0_FRS; 966 uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto); 967 int max_frame_size = ftgmac100_max_frame_size(s, proto); 968 969 if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) 970 != (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) { 971 return -1; 972 } 973 974 if (!ftgmac100_filter(s, buf, size)) { 975 return size; 976 } 977 978 crc = cpu_to_be32(crc32(~0, buf, size)); 979 /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */ 980 size += 4; 981 crc_ptr = (uint8_t *) &crc; 982 983 /* Huge frames are truncated. */ 984 if (size > max_frame_size) { 985 qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n", 986 __func__, size); 987 size = max_frame_size; 988 flags |= FTGMAC100_RXDES0_FTL; 989 } 990 991 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf))) { 992 case ETH_PKT_BCAST: 993 flags |= FTGMAC100_RXDES0_BROADCAST; 994 break; 995 case ETH_PKT_MCAST: 996 flags |= FTGMAC100_RXDES0_MULTICAST; 997 break; 998 case ETH_PKT_UCAST: 999 break; 1000 } 1001 1002 s->isr |= FTGMAC100_INT_RPKT_FIFO; 1003 addr = s->rx_descriptor; 1004 while (size > 0) { 1005 if (!ftgmac100_can_receive(nc)) { 1006 qemu_log_mask(LOG_GUEST_ERROR, "%s: Unexpected packet\n", __func__); 1007 return -1; 1008 } 1009 1010 if (ftgmac100_read_bd(&bd, addr) || 1011 (bd.des0 & FTGMAC100_RXDES0_RXPKT_RDY)) { 1012 /* No descriptors available. Bail out. */ 1013 qemu_log_mask(LOG_GUEST_ERROR, "%s: Lost end of frame\n", 1014 __func__); 1015 s->isr |= FTGMAC100_INT_NO_RXBUF; 1016 break; 1017 } 1018 buf_len = (size <= s->rbsr) ? size : s->rbsr; 1019 bd.des0 |= buf_len & 0x3fff; 1020 size -= buf_len; 1021 1022 /* The last 4 bytes are the CRC. */ 1023 if (size < 4) { 1024 buf_len += size - 4; 1025 } 1026 buf_addr = bd.des3; 1027 if (first && proto == ETH_P_VLAN && buf_len >= 18) { 1028 bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL; 1029 1030 if (s->maccr & FTGMAC100_MACCR_RM_VLAN) { 1031 dma_memory_write(&address_space_memory, buf_addr, buf, 12, 1032 MEMTXATTRS_UNSPECIFIED); 1033 dma_memory_write(&address_space_memory, buf_addr + 12, 1034 buf + 16, buf_len - 16, 1035 MEMTXATTRS_UNSPECIFIED); 1036 } else { 1037 dma_memory_write(&address_space_memory, buf_addr, buf, 1038 buf_len, MEMTXATTRS_UNSPECIFIED); 1039 } 1040 } else { 1041 bd.des1 = 0; 1042 dma_memory_write(&address_space_memory, buf_addr, buf, buf_len, 1043 MEMTXATTRS_UNSPECIFIED); 1044 } 1045 buf += buf_len; 1046 if (size < 4) { 1047 dma_memory_write(&address_space_memory, buf_addr + buf_len, 1048 crc_ptr, 4 - size, MEMTXATTRS_UNSPECIFIED); 1049 crc_ptr += 4 - size; 1050 } 1051 1052 bd.des0 |= first | FTGMAC100_RXDES0_RXPKT_RDY; 1053 first = 0; 1054 if (size == 0) { 1055 /* Last buffer in frame. */ 1056 bd.des0 |= flags | FTGMAC100_RXDES0_LRS; 1057 s->isr |= FTGMAC100_INT_RPKT_BUF; 1058 } 1059 ftgmac100_write_bd(&bd, addr); 1060 if (bd.des0 & s->rxdes0_edorr) { 1061 addr = s->rx_ring; 1062 } else { 1063 addr += FTGMAC100_DBLAC_RXDES_SIZE(s->dblac); 1064 } 1065 } 1066 s->rx_descriptor = addr; 1067 1068 ftgmac100_update_irq(s); 1069 return len; 1070 } 1071 1072 static const MemoryRegionOps ftgmac100_ops = { 1073 .read = ftgmac100_read, 1074 .write = ftgmac100_write, 1075 .valid.min_access_size = 4, 1076 .valid.max_access_size = 4, 1077 .endianness = DEVICE_LITTLE_ENDIAN, 1078 }; 1079 1080 static void ftgmac100_cleanup(NetClientState *nc) 1081 { 1082 FTGMAC100State *s = FTGMAC100(qemu_get_nic_opaque(nc)); 1083 1084 s->nic = NULL; 1085 } 1086 1087 static NetClientInfo net_ftgmac100_info = { 1088 .type = NET_CLIENT_DRIVER_NIC, 1089 .size = sizeof(NICState), 1090 .can_receive = ftgmac100_can_receive, 1091 .receive = ftgmac100_receive, 1092 .cleanup = ftgmac100_cleanup, 1093 .link_status_changed = ftgmac100_set_link, 1094 }; 1095 1096 static void ftgmac100_realize(DeviceState *dev, Error **errp) 1097 { 1098 FTGMAC100State *s = FTGMAC100(dev); 1099 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1100 1101 if (s->aspeed) { 1102 s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR_ASPEED; 1103 s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR_ASPEED; 1104 } else { 1105 s->txdes0_edotr = FTGMAC100_TXDES0_EDOTR; 1106 s->rxdes0_edorr = FTGMAC100_RXDES0_EDORR; 1107 } 1108 1109 memory_region_init(&s->iomem_container, OBJECT(s), 1110 TYPE_FTGMAC100 ".container", FTGMAC100_MEM_SIZE); 1111 sysbus_init_mmio(sbd, &s->iomem_container); 1112 1113 memory_region_init_io(&s->iomem, OBJECT(s), &ftgmac100_ops, s, 1114 TYPE_FTGMAC100 ".regs", FTGMAC100_REG_MEM_SIZE); 1115 memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem); 1116 1117 sysbus_init_irq(sbd, &s->irq); 1118 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1119 1120 s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf, 1121 object_get_typename(OBJECT(dev)), dev->id, 1122 &dev->mem_reentrancy_guard, s); 1123 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 1124 } 1125 1126 static const VMStateDescription vmstate_ftgmac100 = { 1127 .name = TYPE_FTGMAC100, 1128 .version_id = 2, 1129 .minimum_version_id = 2, 1130 .fields = (const VMStateField[]) { 1131 VMSTATE_UINT32(irq_state, FTGMAC100State), 1132 VMSTATE_UINT32(isr, FTGMAC100State), 1133 VMSTATE_UINT32(ier, FTGMAC100State), 1134 VMSTATE_UINT32(rx_enabled, FTGMAC100State), 1135 VMSTATE_UINT32(rbsr, FTGMAC100State), 1136 VMSTATE_UINT32_ARRAY(math, FTGMAC100State, 2), 1137 VMSTATE_UINT32(itc, FTGMAC100State), 1138 VMSTATE_UINT32(aptcr, FTGMAC100State), 1139 VMSTATE_UINT32(dblac, FTGMAC100State), 1140 VMSTATE_UINT32(revr, FTGMAC100State), 1141 VMSTATE_UINT32(fear1, FTGMAC100State), 1142 VMSTATE_UINT32(tpafcr, FTGMAC100State), 1143 VMSTATE_UINT32(maccr, FTGMAC100State), 1144 VMSTATE_UINT32(phycr, FTGMAC100State), 1145 VMSTATE_UINT32(phydata, FTGMAC100State), 1146 VMSTATE_UINT32(fcr, FTGMAC100State), 1147 VMSTATE_UINT32(phy_status, FTGMAC100State), 1148 VMSTATE_UINT32(phy_control, FTGMAC100State), 1149 VMSTATE_UINT32(phy_advertise, FTGMAC100State), 1150 VMSTATE_UINT32(phy_int, FTGMAC100State), 1151 VMSTATE_UINT32(phy_int_mask, FTGMAC100State), 1152 VMSTATE_UINT32(txdes0_edotr, FTGMAC100State), 1153 VMSTATE_UINT32(rxdes0_edorr, FTGMAC100State), 1154 VMSTATE_UINT64(rx_ring, FTGMAC100State), 1155 VMSTATE_UINT64(tx_ring, FTGMAC100State), 1156 VMSTATE_UINT64(rx_descriptor, FTGMAC100State), 1157 VMSTATE_UINT64(tx_descriptor, FTGMAC100State), 1158 VMSTATE_END_OF_LIST() 1159 } 1160 }; 1161 1162 static Property ftgmac100_properties[] = { 1163 DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false), 1164 DEFINE_NIC_PROPERTIES(FTGMAC100State, conf), 1165 DEFINE_PROP_END_OF_LIST(), 1166 }; 1167 1168 static void ftgmac100_class_init(ObjectClass *klass, void *data) 1169 { 1170 DeviceClass *dc = DEVICE_CLASS(klass); 1171 1172 dc->vmsd = &vmstate_ftgmac100; 1173 dc->reset = ftgmac100_reset; 1174 device_class_set_props(dc, ftgmac100_properties); 1175 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1176 dc->realize = ftgmac100_realize; 1177 dc->desc = "Faraday FTGMAC100 Gigabit Ethernet emulation"; 1178 } 1179 1180 static const TypeInfo ftgmac100_info = { 1181 .name = TYPE_FTGMAC100, 1182 .parent = TYPE_SYS_BUS_DEVICE, 1183 .instance_size = sizeof(FTGMAC100State), 1184 .class_init = ftgmac100_class_init, 1185 }; 1186 1187 /* 1188 * AST2600 MII controller 1189 */ 1190 #define ASPEED_MII_PHYCR_FIRE BIT(31) 1191 #define ASPEED_MII_PHYCR_ST_22 BIT(28) 1192 #define ASPEED_MII_PHYCR_OP(x) ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \ 1193 ASPEED_MII_PHYCR_OP_READ)) 1194 #define ASPEED_MII_PHYCR_OP_WRITE BIT(26) 1195 #define ASPEED_MII_PHYCR_OP_READ BIT(27) 1196 #define ASPEED_MII_PHYCR_DATA(x) (x & 0xffff) 1197 #define ASPEED_MII_PHYCR_PHY(x) (((x) >> 21) & 0x1f) 1198 #define ASPEED_MII_PHYCR_REG(x) (((x) >> 16) & 0x1f) 1199 1200 #define ASPEED_MII_PHYDATA_IDLE BIT(16) 1201 1202 static void aspeed_mii_transition(AspeedMiiState *s, bool fire) 1203 { 1204 if (fire) { 1205 s->phycr |= ASPEED_MII_PHYCR_FIRE; 1206 s->phydata &= ~ASPEED_MII_PHYDATA_IDLE; 1207 } else { 1208 s->phycr &= ~ASPEED_MII_PHYCR_FIRE; 1209 s->phydata |= ASPEED_MII_PHYDATA_IDLE; 1210 } 1211 } 1212 1213 static void aspeed_mii_do_phy_ctl(AspeedMiiState *s) 1214 { 1215 uint8_t reg; 1216 uint16_t data; 1217 1218 if (!(s->phycr & ASPEED_MII_PHYCR_ST_22)) { 1219 aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE); 1220 qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__); 1221 return; 1222 } 1223 1224 /* Nothing to do */ 1225 if (!(s->phycr & ASPEED_MII_PHYCR_FIRE)) { 1226 return; 1227 } 1228 1229 reg = ASPEED_MII_PHYCR_REG(s->phycr); 1230 data = ASPEED_MII_PHYCR_DATA(s->phycr); 1231 1232 switch (ASPEED_MII_PHYCR_OP(s->phycr)) { 1233 case ASPEED_MII_PHYCR_OP_WRITE: 1234 do_phy_write(s->nic, reg, data); 1235 break; 1236 case ASPEED_MII_PHYCR_OP_READ: 1237 s->phydata = (s->phydata & ~0xffff) | do_phy_read(s->nic, reg); 1238 break; 1239 default: 1240 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n", 1241 __func__, s->phycr); 1242 } 1243 1244 aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE); 1245 } 1246 1247 static uint64_t aspeed_mii_read(void *opaque, hwaddr addr, unsigned size) 1248 { 1249 AspeedMiiState *s = ASPEED_MII(opaque); 1250 1251 switch (addr) { 1252 case 0x0: 1253 return s->phycr; 1254 case 0x4: 1255 return s->phydata; 1256 default: 1257 g_assert_not_reached(); 1258 } 1259 } 1260 1261 static void aspeed_mii_write(void *opaque, hwaddr addr, 1262 uint64_t value, unsigned size) 1263 { 1264 AspeedMiiState *s = ASPEED_MII(opaque); 1265 1266 switch (addr) { 1267 case 0x0: 1268 s->phycr = value & ~(s->phycr & ASPEED_MII_PHYCR_FIRE); 1269 break; 1270 case 0x4: 1271 s->phydata = value & ~(0xffff | ASPEED_MII_PHYDATA_IDLE); 1272 break; 1273 default: 1274 g_assert_not_reached(); 1275 } 1276 1277 aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE)); 1278 aspeed_mii_do_phy_ctl(s); 1279 } 1280 1281 static const MemoryRegionOps aspeed_mii_ops = { 1282 .read = aspeed_mii_read, 1283 .write = aspeed_mii_write, 1284 .valid.min_access_size = 4, 1285 .valid.max_access_size = 4, 1286 .endianness = DEVICE_LITTLE_ENDIAN, 1287 }; 1288 1289 static void aspeed_mii_reset(DeviceState *dev) 1290 { 1291 AspeedMiiState *s = ASPEED_MII(dev); 1292 1293 s->phycr = 0; 1294 s->phydata = 0; 1295 1296 aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE)); 1297 }; 1298 1299 static void aspeed_mii_realize(DeviceState *dev, Error **errp) 1300 { 1301 AspeedMiiState *s = ASPEED_MII(dev); 1302 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1303 1304 assert(s->nic); 1305 1306 memory_region_init_io(&s->iomem, OBJECT(dev), &aspeed_mii_ops, s, 1307 TYPE_ASPEED_MII, 0x8); 1308 sysbus_init_mmio(sbd, &s->iomem); 1309 } 1310 1311 static const VMStateDescription vmstate_aspeed_mii = { 1312 .name = TYPE_ASPEED_MII, 1313 .version_id = 1, 1314 .minimum_version_id = 1, 1315 .fields = (const VMStateField[]) { 1316 VMSTATE_UINT32(phycr, FTGMAC100State), 1317 VMSTATE_UINT32(phydata, FTGMAC100State), 1318 VMSTATE_END_OF_LIST() 1319 } 1320 }; 1321 1322 static Property aspeed_mii_properties[] = { 1323 DEFINE_PROP_LINK("nic", AspeedMiiState, nic, TYPE_FTGMAC100, 1324 FTGMAC100State *), 1325 DEFINE_PROP_END_OF_LIST(), 1326 }; 1327 1328 static void aspeed_mii_class_init(ObjectClass *klass, void *data) 1329 { 1330 DeviceClass *dc = DEVICE_CLASS(klass); 1331 1332 dc->vmsd = &vmstate_aspeed_mii; 1333 dc->reset = aspeed_mii_reset; 1334 dc->realize = aspeed_mii_realize; 1335 dc->desc = "Aspeed MII controller"; 1336 device_class_set_props(dc, aspeed_mii_properties); 1337 } 1338 1339 static const TypeInfo aspeed_mii_info = { 1340 .name = TYPE_ASPEED_MII, 1341 .parent = TYPE_SYS_BUS_DEVICE, 1342 .instance_size = sizeof(AspeedMiiState), 1343 .class_init = aspeed_mii_class_init, 1344 }; 1345 1346 static void ftgmac100_register_types(void) 1347 { 1348 type_register_static(&ftgmac100_info); 1349 type_register_static(&aspeed_mii_info); 1350 } 1351 1352 type_init(ftgmac100_register_types) 1353