1093454e2SDmitry Fleytman /* 2093454e2SDmitry Fleytman * QEMU e1000(e) emulation - shared code 3093454e2SDmitry Fleytman * 4093454e2SDmitry Fleytman * Copyright (c) 2008 Qumranet 5093454e2SDmitry Fleytman * 6093454e2SDmitry Fleytman * Based on work done by: 7093454e2SDmitry Fleytman * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc. 8093454e2SDmitry Fleytman * Copyright (c) 2007 Dan Aloni 9093454e2SDmitry Fleytman * Copyright (c) 2004 Antony T Curtis 10093454e2SDmitry Fleytman * 11093454e2SDmitry Fleytman * This library is free software; you can redistribute it and/or 12093454e2SDmitry Fleytman * modify it under the terms of the GNU Lesser General Public 13093454e2SDmitry Fleytman * License as published by the Free Software Foundation; either 147cd2a9faSChetan Pant * version 2.1 of the License, or (at your option) any later version. 15093454e2SDmitry Fleytman * 16093454e2SDmitry Fleytman * This library is distributed in the hope that it will be useful, 17093454e2SDmitry Fleytman * but WITHOUT ANY WARRANTY; without even the implied warranty of 18093454e2SDmitry Fleytman * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19093454e2SDmitry Fleytman * Lesser General Public License for more details. 20093454e2SDmitry Fleytman * 21093454e2SDmitry Fleytman * You should have received a copy of the GNU Lesser General Public 22093454e2SDmitry Fleytman * License along with this library; if not, see <http://www.gnu.org/licenses/>. 23093454e2SDmitry Fleytman */ 24093454e2SDmitry Fleytman 25093454e2SDmitry Fleytman #include "qemu/osdep.h" 26872a2b7cSPhilippe Mathieu-Daudé #include "qemu/units.h" 27b7728c9fSAkihiko Odaki #include "hw/net/mii.h" 28edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h" 29*2fe63579SAkihiko Odaki #include "net/eth.h" 30093454e2SDmitry Fleytman #include "net/net.h" 31093454e2SDmitry Fleytman 32093454e2SDmitry Fleytman #include "e1000x_common.h" 33093454e2SDmitry Fleytman 34093454e2SDmitry Fleytman #include "trace.h" 35093454e2SDmitry Fleytman 36093454e2SDmitry Fleytman bool e1000x_rx_ready(PCIDevice *d, uint32_t *mac) 37093454e2SDmitry Fleytman { 38093454e2SDmitry Fleytman bool link_up = mac[STATUS] & E1000_STATUS_LU; 39093454e2SDmitry Fleytman bool rx_enabled = mac[RCTL] & E1000_RCTL_EN; 40093454e2SDmitry Fleytman bool pci_master = d->config[PCI_COMMAND] & PCI_COMMAND_MASTER; 41093454e2SDmitry Fleytman 42093454e2SDmitry Fleytman if (!link_up || !rx_enabled || !pci_master) { 43093454e2SDmitry Fleytman trace_e1000x_rx_can_recv_disabled(link_up, rx_enabled, pci_master); 44093454e2SDmitry Fleytman return false; 45093454e2SDmitry Fleytman } 46093454e2SDmitry Fleytman 47093454e2SDmitry Fleytman return true; 48093454e2SDmitry Fleytman } 49093454e2SDmitry Fleytman 50093454e2SDmitry Fleytman bool e1000x_is_vlan_packet(const uint8_t *buf, uint16_t vet) 51093454e2SDmitry Fleytman { 52*2fe63579SAkihiko Odaki uint16_t eth_proto = lduw_be_p(&PKT_GET_ETH_HDR(buf)->h_proto); 53093454e2SDmitry Fleytman bool res = (eth_proto == vet); 54093454e2SDmitry Fleytman 55093454e2SDmitry Fleytman trace_e1000x_vlan_is_vlan_pkt(res, eth_proto, vet); 56093454e2SDmitry Fleytman 57093454e2SDmitry Fleytman return res; 58093454e2SDmitry Fleytman } 59093454e2SDmitry Fleytman 60093454e2SDmitry Fleytman bool e1000x_rx_group_filter(uint32_t *mac, const uint8_t *buf) 61093454e2SDmitry Fleytman { 62093454e2SDmitry Fleytman static const int mta_shift[] = { 4, 3, 2, 0 }; 63093454e2SDmitry Fleytman uint32_t f, ra[2], *rp, rctl = mac[RCTL]; 64093454e2SDmitry Fleytman 65093454e2SDmitry Fleytman for (rp = mac + RA; rp < mac + RA + 32; rp += 2) { 66093454e2SDmitry Fleytman if (!(rp[1] & E1000_RAH_AV)) { 67093454e2SDmitry Fleytman continue; 68093454e2SDmitry Fleytman } 69093454e2SDmitry Fleytman ra[0] = cpu_to_le32(rp[0]); 70093454e2SDmitry Fleytman ra[1] = cpu_to_le32(rp[1]); 71*2fe63579SAkihiko Odaki if (!memcmp(buf, (uint8_t *)ra, ETH_ALEN)) { 72093454e2SDmitry Fleytman trace_e1000x_rx_flt_ucast_match((int)(rp - mac - RA) / 2, 73093454e2SDmitry Fleytman MAC_ARG(buf)); 74093454e2SDmitry Fleytman return true; 75093454e2SDmitry Fleytman } 76093454e2SDmitry Fleytman } 77093454e2SDmitry Fleytman trace_e1000x_rx_flt_ucast_mismatch(MAC_ARG(buf)); 78093454e2SDmitry Fleytman 79093454e2SDmitry Fleytman f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3]; 80093454e2SDmitry Fleytman f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff; 81093454e2SDmitry Fleytman if (mac[MTA + (f >> 5)] & (1 << (f & 0x1f))) { 82093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, MPRC); 83093454e2SDmitry Fleytman return true; 84093454e2SDmitry Fleytman } 85093454e2SDmitry Fleytman 86093454e2SDmitry Fleytman trace_e1000x_rx_flt_inexact_mismatch(MAC_ARG(buf), 87093454e2SDmitry Fleytman (rctl >> E1000_RCTL_MO_SHIFT) & 3, 88093454e2SDmitry Fleytman f >> 5, 89093454e2SDmitry Fleytman mac[MTA + (f >> 5)]); 90093454e2SDmitry Fleytman 91093454e2SDmitry Fleytman return false; 92093454e2SDmitry Fleytman } 93093454e2SDmitry Fleytman 94093454e2SDmitry Fleytman bool e1000x_hw_rx_enabled(uint32_t *mac) 95093454e2SDmitry Fleytman { 96093454e2SDmitry Fleytman if (!(mac[STATUS] & E1000_STATUS_LU)) { 97093454e2SDmitry Fleytman trace_e1000x_rx_link_down(mac[STATUS]); 98093454e2SDmitry Fleytman return false; 99093454e2SDmitry Fleytman } 100093454e2SDmitry Fleytman 101093454e2SDmitry Fleytman if (!(mac[RCTL] & E1000_RCTL_EN)) { 102093454e2SDmitry Fleytman trace_e1000x_rx_disabled(mac[RCTL]); 103093454e2SDmitry Fleytman return false; 104093454e2SDmitry Fleytman } 105093454e2SDmitry Fleytman 106093454e2SDmitry Fleytman return true; 107093454e2SDmitry Fleytman } 108093454e2SDmitry Fleytman 109093454e2SDmitry Fleytman bool e1000x_is_oversized(uint32_t *mac, size_t size) 110093454e2SDmitry Fleytman { 111093454e2SDmitry Fleytman /* this is the size past which hardware will 112093454e2SDmitry Fleytman drop packets when setting LPE=0 */ 113093454e2SDmitry Fleytman static const int maximum_ethernet_vlan_size = 1522; 114093454e2SDmitry Fleytman /* this is the size past which hardware will 115093454e2SDmitry Fleytman drop packets when setting LPE=1 */ 116872a2b7cSPhilippe Mathieu-Daudé static const int maximum_ethernet_lpe_size = 16 * KiB; 117093454e2SDmitry Fleytman 118093454e2SDmitry Fleytman if ((size > maximum_ethernet_lpe_size || 119093454e2SDmitry Fleytman (size > maximum_ethernet_vlan_size 120093454e2SDmitry Fleytman && !(mac[RCTL] & E1000_RCTL_LPE))) 121093454e2SDmitry Fleytman && !(mac[RCTL] & E1000_RCTL_SBP)) { 122093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, ROC); 123093454e2SDmitry Fleytman trace_e1000x_rx_oversized(size); 124093454e2SDmitry Fleytman return true; 125093454e2SDmitry Fleytman } 126093454e2SDmitry Fleytman 127093454e2SDmitry Fleytman return false; 128093454e2SDmitry Fleytman } 129093454e2SDmitry Fleytman 130093454e2SDmitry Fleytman void e1000x_restart_autoneg(uint32_t *mac, uint16_t *phy, QEMUTimer *timer) 131093454e2SDmitry Fleytman { 132093454e2SDmitry Fleytman e1000x_update_regs_on_link_down(mac, phy); 133093454e2SDmitry Fleytman trace_e1000x_link_negotiation_start(); 134093454e2SDmitry Fleytman timer_mod(timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500); 135093454e2SDmitry Fleytman } 136093454e2SDmitry Fleytman 137093454e2SDmitry Fleytman void e1000x_reset_mac_addr(NICState *nic, uint32_t *mac_regs, 138093454e2SDmitry Fleytman uint8_t *mac_addr) 139093454e2SDmitry Fleytman { 140093454e2SDmitry Fleytman int i; 141093454e2SDmitry Fleytman 142093454e2SDmitry Fleytman mac_regs[RA] = 0; 143093454e2SDmitry Fleytman mac_regs[RA + 1] = E1000_RAH_AV; 144093454e2SDmitry Fleytman for (i = 0; i < 4; i++) { 145093454e2SDmitry Fleytman mac_regs[RA] |= mac_addr[i] << (8 * i); 146093454e2SDmitry Fleytman mac_regs[RA + 1] |= 147093454e2SDmitry Fleytman (i < 2) ? mac_addr[i + 4] << (8 * i) : 0; 148093454e2SDmitry Fleytman } 149093454e2SDmitry Fleytman 150093454e2SDmitry Fleytman qemu_format_nic_info_str(qemu_get_queue(nic), mac_addr); 151093454e2SDmitry Fleytman trace_e1000x_mac_indicate(MAC_ARG(mac_addr)); 152093454e2SDmitry Fleytman } 153093454e2SDmitry Fleytman 154093454e2SDmitry Fleytman void e1000x_update_regs_on_autoneg_done(uint32_t *mac, uint16_t *phy) 155093454e2SDmitry Fleytman { 156093454e2SDmitry Fleytman e1000x_update_regs_on_link_up(mac, phy); 157b7728c9fSAkihiko Odaki phy[MII_ANLPAR] |= MII_ANLPAR_ACK; 158b7728c9fSAkihiko Odaki phy[MII_BMSR] |= MII_BMSR_AN_COMP; 159093454e2SDmitry Fleytman trace_e1000x_link_negotiation_done(); 160093454e2SDmitry Fleytman } 161093454e2SDmitry Fleytman 162093454e2SDmitry Fleytman void 163093454e2SDmitry Fleytman e1000x_core_prepare_eeprom(uint16_t *eeprom, 164093454e2SDmitry Fleytman const uint16_t *templ, 165093454e2SDmitry Fleytman uint32_t templ_size, 166093454e2SDmitry Fleytman uint16_t dev_id, 167093454e2SDmitry Fleytman const uint8_t *macaddr) 168093454e2SDmitry Fleytman { 169093454e2SDmitry Fleytman uint16_t checksum = 0; 170093454e2SDmitry Fleytman int i; 171093454e2SDmitry Fleytman 172093454e2SDmitry Fleytman memmove(eeprom, templ, templ_size); 173093454e2SDmitry Fleytman 174093454e2SDmitry Fleytman for (i = 0; i < 3; i++) { 175093454e2SDmitry Fleytman eeprom[i] = (macaddr[2 * i + 1] << 8) | macaddr[2 * i]; 176093454e2SDmitry Fleytman } 177093454e2SDmitry Fleytman 178093454e2SDmitry Fleytman eeprom[11] = eeprom[13] = dev_id; 179093454e2SDmitry Fleytman 180093454e2SDmitry Fleytman for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 181093454e2SDmitry Fleytman checksum += eeprom[i]; 182093454e2SDmitry Fleytman } 183093454e2SDmitry Fleytman 184093454e2SDmitry Fleytman checksum = (uint16_t) EEPROM_SUM - checksum; 185093454e2SDmitry Fleytman 186093454e2SDmitry Fleytman eeprom[EEPROM_CHECKSUM_REG] = checksum; 187093454e2SDmitry Fleytman } 188093454e2SDmitry Fleytman 189093454e2SDmitry Fleytman uint32_t 190093454e2SDmitry Fleytman e1000x_rxbufsize(uint32_t rctl) 191093454e2SDmitry Fleytman { 192093454e2SDmitry Fleytman rctl &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 | 193093454e2SDmitry Fleytman E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 | 194093454e2SDmitry Fleytman E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256; 195093454e2SDmitry Fleytman switch (rctl) { 196093454e2SDmitry Fleytman case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384: 197093454e2SDmitry Fleytman return 16384; 198093454e2SDmitry Fleytman case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192: 199093454e2SDmitry Fleytman return 8192; 200093454e2SDmitry Fleytman case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096: 201093454e2SDmitry Fleytman return 4096; 202093454e2SDmitry Fleytman case E1000_RCTL_SZ_1024: 203093454e2SDmitry Fleytman return 1024; 204093454e2SDmitry Fleytman case E1000_RCTL_SZ_512: 205093454e2SDmitry Fleytman return 512; 206093454e2SDmitry Fleytman case E1000_RCTL_SZ_256: 207093454e2SDmitry Fleytman return 256; 208093454e2SDmitry Fleytman } 209093454e2SDmitry Fleytman return 2048; 210093454e2SDmitry Fleytman } 211093454e2SDmitry Fleytman 212093454e2SDmitry Fleytman void 213093454e2SDmitry Fleytman e1000x_update_rx_total_stats(uint32_t *mac, 214093454e2SDmitry Fleytman size_t data_size, 215093454e2SDmitry Fleytman size_t data_fcs_size) 216093454e2SDmitry Fleytman { 217093454e2SDmitry Fleytman static const int PRCregs[6] = { PRC64, PRC127, PRC255, PRC511, 218093454e2SDmitry Fleytman PRC1023, PRC1522 }; 219093454e2SDmitry Fleytman 220093454e2SDmitry Fleytman e1000x_increase_size_stats(mac, PRCregs, data_fcs_size); 221093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, TPR); 222093454e2SDmitry Fleytman mac[GPRC] = mac[TPR]; 223093454e2SDmitry Fleytman /* TOR - Total Octets Received: 224093454e2SDmitry Fleytman * This register includes bytes received in a packet from the <Destination 225093454e2SDmitry Fleytman * Address> field through the <CRC> field, inclusively. 226093454e2SDmitry Fleytman * Always include FCS length (4) in size. 227093454e2SDmitry Fleytman */ 228093454e2SDmitry Fleytman e1000x_grow_8reg_if_not_full(mac, TORL, data_size + 4); 229093454e2SDmitry Fleytman mac[GORCL] = mac[TORL]; 230093454e2SDmitry Fleytman mac[GORCH] = mac[TORH]; 231093454e2SDmitry Fleytman } 232093454e2SDmitry Fleytman 233093454e2SDmitry Fleytman void 234093454e2SDmitry Fleytman e1000x_increase_size_stats(uint32_t *mac, const int *size_regs, int size) 235093454e2SDmitry Fleytman { 236093454e2SDmitry Fleytman if (size > 1023) { 237093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, size_regs[5]); 238093454e2SDmitry Fleytman } else if (size > 511) { 239093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, size_regs[4]); 240093454e2SDmitry Fleytman } else if (size > 255) { 241093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, size_regs[3]); 242093454e2SDmitry Fleytman } else if (size > 127) { 243093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, size_regs[2]); 244093454e2SDmitry Fleytman } else if (size > 64) { 245093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, size_regs[1]); 246093454e2SDmitry Fleytman } else if (size == 64) { 247093454e2SDmitry Fleytman e1000x_inc_reg_if_not_full(mac, size_regs[0]); 248093454e2SDmitry Fleytman } 249093454e2SDmitry Fleytman } 250093454e2SDmitry Fleytman 251093454e2SDmitry Fleytman void 252093454e2SDmitry Fleytman e1000x_read_tx_ctx_descr(struct e1000_context_desc *d, 253093454e2SDmitry Fleytman e1000x_txd_props *props) 254093454e2SDmitry Fleytman { 255093454e2SDmitry Fleytman uint32_t op = le32_to_cpu(d->cmd_and_length); 256093454e2SDmitry Fleytman 257093454e2SDmitry Fleytman props->ipcss = d->lower_setup.ip_fields.ipcss; 258093454e2SDmitry Fleytman props->ipcso = d->lower_setup.ip_fields.ipcso; 259093454e2SDmitry Fleytman props->ipcse = le16_to_cpu(d->lower_setup.ip_fields.ipcse); 260093454e2SDmitry Fleytman props->tucss = d->upper_setup.tcp_fields.tucss; 261093454e2SDmitry Fleytman props->tucso = d->upper_setup.tcp_fields.tucso; 262093454e2SDmitry Fleytman props->tucse = le16_to_cpu(d->upper_setup.tcp_fields.tucse); 263093454e2SDmitry Fleytman props->paylen = op & 0xfffff; 264093454e2SDmitry Fleytman props->hdr_len = d->tcp_seg_setup.fields.hdr_len; 265093454e2SDmitry Fleytman props->mss = le16_to_cpu(d->tcp_seg_setup.fields.mss); 266093454e2SDmitry Fleytman props->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0; 267093454e2SDmitry Fleytman props->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0; 268093454e2SDmitry Fleytman props->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0; 269093454e2SDmitry Fleytman } 270