1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "hw/hw.h" 21 #include "qemu/timer.h" 22 #include "net/net.h" 23 #include "hw/mips/mips.h" 24 #include <zlib.h> 25 26 //#define DEBUG_SONIC 27 28 29 #ifdef DEBUG_SONIC 30 #define DPRINTF(fmt, ...) \ 31 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 32 static const char* reg_names[] = { 33 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 34 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 35 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 36 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 37 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 38 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 39 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 40 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 41 #else 42 #define DPRINTF(fmt, ...) do {} while (0) 43 #endif 44 45 #define SONIC_ERROR(fmt, ...) \ 46 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 47 48 #define SONIC_CR 0x00 49 #define SONIC_DCR 0x01 50 #define SONIC_RCR 0x02 51 #define SONIC_TCR 0x03 52 #define SONIC_IMR 0x04 53 #define SONIC_ISR 0x05 54 #define SONIC_UTDA 0x06 55 #define SONIC_CTDA 0x07 56 #define SONIC_TPS 0x08 57 #define SONIC_TFC 0x09 58 #define SONIC_TSA0 0x0a 59 #define SONIC_TSA1 0x0b 60 #define SONIC_TFS 0x0c 61 #define SONIC_URDA 0x0d 62 #define SONIC_CRDA 0x0e 63 #define SONIC_CRBA0 0x0f 64 #define SONIC_CRBA1 0x10 65 #define SONIC_RBWC0 0x11 66 #define SONIC_RBWC1 0x12 67 #define SONIC_EOBC 0x13 68 #define SONIC_URRA 0x14 69 #define SONIC_RSA 0x15 70 #define SONIC_REA 0x16 71 #define SONIC_RRP 0x17 72 #define SONIC_RWP 0x18 73 #define SONIC_TRBA0 0x19 74 #define SONIC_TRBA1 0x1a 75 #define SONIC_LLFA 0x1f 76 #define SONIC_TTDA 0x20 77 #define SONIC_CEP 0x21 78 #define SONIC_CAP2 0x22 79 #define SONIC_CAP1 0x23 80 #define SONIC_CAP0 0x24 81 #define SONIC_CE 0x25 82 #define SONIC_CDP 0x26 83 #define SONIC_CDC 0x27 84 #define SONIC_SR 0x28 85 #define SONIC_WT0 0x29 86 #define SONIC_WT1 0x2a 87 #define SONIC_RSC 0x2b 88 #define SONIC_CRCT 0x2c 89 #define SONIC_FAET 0x2d 90 #define SONIC_MPT 0x2e 91 #define SONIC_MDT 0x2f 92 #define SONIC_DCR2 0x3f 93 94 #define SONIC_CR_HTX 0x0001 95 #define SONIC_CR_TXP 0x0002 96 #define SONIC_CR_RXDIS 0x0004 97 #define SONIC_CR_RXEN 0x0008 98 #define SONIC_CR_STP 0x0010 99 #define SONIC_CR_ST 0x0020 100 #define SONIC_CR_RST 0x0080 101 #define SONIC_CR_RRRA 0x0100 102 #define SONIC_CR_LCAM 0x0200 103 #define SONIC_CR_MASK 0x03bf 104 105 #define SONIC_DCR_DW 0x0020 106 #define SONIC_DCR_LBR 0x2000 107 #define SONIC_DCR_EXBUS 0x8000 108 109 #define SONIC_RCR_PRX 0x0001 110 #define SONIC_RCR_LBK 0x0002 111 #define SONIC_RCR_FAER 0x0004 112 #define SONIC_RCR_CRCR 0x0008 113 #define SONIC_RCR_CRS 0x0020 114 #define SONIC_RCR_LPKT 0x0040 115 #define SONIC_RCR_BC 0x0080 116 #define SONIC_RCR_MC 0x0100 117 #define SONIC_RCR_LB0 0x0200 118 #define SONIC_RCR_LB1 0x0400 119 #define SONIC_RCR_AMC 0x0800 120 #define SONIC_RCR_PRO 0x1000 121 #define SONIC_RCR_BRD 0x2000 122 #define SONIC_RCR_RNT 0x4000 123 124 #define SONIC_TCR_PTX 0x0001 125 #define SONIC_TCR_BCM 0x0002 126 #define SONIC_TCR_FU 0x0004 127 #define SONIC_TCR_EXC 0x0040 128 #define SONIC_TCR_CRSL 0x0080 129 #define SONIC_TCR_NCRS 0x0100 130 #define SONIC_TCR_EXD 0x0400 131 #define SONIC_TCR_CRCI 0x2000 132 #define SONIC_TCR_PINT 0x8000 133 134 #define SONIC_ISR_RBE 0x0020 135 #define SONIC_ISR_RDE 0x0040 136 #define SONIC_ISR_TC 0x0080 137 #define SONIC_ISR_TXDN 0x0200 138 #define SONIC_ISR_PKTRX 0x0400 139 #define SONIC_ISR_PINT 0x0800 140 #define SONIC_ISR_LCD 0x1000 141 142 typedef struct dp8393xState { 143 /* Hardware */ 144 int it_shift; 145 qemu_irq irq; 146 #ifdef DEBUG_SONIC 147 int irq_level; 148 #endif 149 QEMUTimer *watchdog; 150 int64_t wt_last_update; 151 NICConf conf; 152 NICState *nic; 153 MemoryRegion *address_space; 154 MemoryRegion mmio; 155 156 /* Registers */ 157 uint8_t cam[16][6]; 158 uint16_t regs[0x40]; 159 160 /* Temporaries */ 161 uint8_t tx_buffer[0x10000]; 162 int loopback_packet; 163 164 /* Memory access */ 165 AddressSpace as; 166 } dp8393xState; 167 168 static void dp8393x_update_irq(dp8393xState *s) 169 { 170 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 171 172 #ifdef DEBUG_SONIC 173 if (level != s->irq_level) { 174 s->irq_level = level; 175 if (level) { 176 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 177 } else { 178 DPRINTF("lower irq\n"); 179 } 180 } 181 #endif 182 183 qemu_set_irq(s->irq, level); 184 } 185 186 static void do_load_cam(dp8393xState *s) 187 { 188 uint16_t data[8]; 189 int width, size; 190 uint16_t index = 0; 191 192 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 193 size = sizeof(uint16_t) * 4 * width; 194 195 while (s->regs[SONIC_CDC] & 0x1f) { 196 /* Fill current entry */ 197 address_space_rw(&s->as, 198 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP], 199 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 200 s->cam[index][0] = data[1 * width] & 0xff; 201 s->cam[index][1] = data[1 * width] >> 8; 202 s->cam[index][2] = data[2 * width] & 0xff; 203 s->cam[index][3] = data[2 * width] >> 8; 204 s->cam[index][4] = data[3 * width] & 0xff; 205 s->cam[index][5] = data[3 * width] >> 8; 206 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 207 s->cam[index][0], s->cam[index][1], s->cam[index][2], 208 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 209 /* Move to next entry */ 210 s->regs[SONIC_CDC]--; 211 s->regs[SONIC_CDP] += size; 212 index++; 213 } 214 215 /* Read CAM enable */ 216 address_space_rw(&s->as, 217 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP], 218 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 219 s->regs[SONIC_CE] = data[0 * width]; 220 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 221 222 /* Done */ 223 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 224 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 225 dp8393x_update_irq(s); 226 } 227 228 static void do_read_rra(dp8393xState *s) 229 { 230 uint16_t data[8]; 231 int width, size; 232 233 /* Read memory */ 234 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 235 size = sizeof(uint16_t) * 4 * width; 236 address_space_rw(&s->as, 237 (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP], 238 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 239 240 /* Update SONIC registers */ 241 s->regs[SONIC_CRBA0] = data[0 * width]; 242 s->regs[SONIC_CRBA1] = data[1 * width]; 243 s->regs[SONIC_RBWC0] = data[2 * width]; 244 s->regs[SONIC_RBWC1] = data[3 * width]; 245 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 246 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 247 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 248 249 /* Go to next entry */ 250 s->regs[SONIC_RRP] += size; 251 252 /* Handle wrap */ 253 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 254 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 255 } 256 257 /* Check resource exhaustion */ 258 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 259 { 260 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 261 dp8393x_update_irq(s); 262 } 263 264 /* Done */ 265 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 266 } 267 268 static void do_software_reset(dp8393xState *s) 269 { 270 timer_del(s->watchdog); 271 272 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 273 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 274 } 275 276 static void set_next_tick(dp8393xState *s) 277 { 278 uint32_t ticks; 279 int64_t delay; 280 281 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 282 timer_del(s->watchdog); 283 return; 284 } 285 286 ticks = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 287 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 288 delay = get_ticks_per_sec() * ticks / 5000000; 289 timer_mod(s->watchdog, s->wt_last_update + delay); 290 } 291 292 static void update_wt_regs(dp8393xState *s) 293 { 294 int64_t elapsed; 295 uint32_t val; 296 297 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 298 timer_del(s->watchdog); 299 return; 300 } 301 302 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 303 val = s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 304 val -= elapsed / 5000000; 305 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 306 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 307 set_next_tick(s); 308 309 } 310 311 static void do_start_timer(dp8393xState *s) 312 { 313 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 314 set_next_tick(s); 315 } 316 317 static void do_stop_timer(dp8393xState *s) 318 { 319 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 320 update_wt_regs(s); 321 } 322 323 static void do_receiver_enable(dp8393xState *s) 324 { 325 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 326 } 327 328 static void do_receiver_disable(dp8393xState *s) 329 { 330 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 331 } 332 333 static void do_transmit_packets(dp8393xState *s) 334 { 335 NetClientState *nc = qemu_get_queue(s->nic); 336 uint16_t data[12]; 337 int width, size; 338 int tx_len, len; 339 uint16_t i; 340 341 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 342 343 while (1) { 344 /* Read memory */ 345 DPRINTF("Transmit packet at %08x\n", 346 (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_CTDA]); 347 size = sizeof(uint16_t) * 6 * width; 348 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 349 address_space_rw(&s->as, 350 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * width, 351 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 352 tx_len = 0; 353 354 /* Update registers */ 355 s->regs[SONIC_TCR] = data[0 * width] & 0xf000; 356 s->regs[SONIC_TPS] = data[1 * width]; 357 s->regs[SONIC_TFC] = data[2 * width]; 358 s->regs[SONIC_TSA0] = data[3 * width]; 359 s->regs[SONIC_TSA1] = data[4 * width]; 360 s->regs[SONIC_TFS] = data[5 * width]; 361 362 /* Handle programmable interrupt */ 363 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 364 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 365 } else { 366 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 367 } 368 369 for (i = 0; i < s->regs[SONIC_TFC]; ) { 370 /* Append fragment */ 371 len = s->regs[SONIC_TFS]; 372 if (tx_len + len > sizeof(s->tx_buffer)) { 373 len = sizeof(s->tx_buffer) - tx_len; 374 } 375 address_space_rw(&s->as, 376 (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0], 377 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0); 378 tx_len += len; 379 380 i++; 381 if (i != s->regs[SONIC_TFC]) { 382 /* Read next fragment details */ 383 size = sizeof(uint16_t) * 3 * width; 384 address_space_rw(&s->as, 385 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * i) * width, 386 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 387 s->regs[SONIC_TSA0] = data[0 * width]; 388 s->regs[SONIC_TSA1] = data[1 * width]; 389 s->regs[SONIC_TFS] = data[2 * width]; 390 } 391 } 392 393 /* Handle Ethernet checksum */ 394 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 395 /* Don't append FCS there, to look like slirp packets 396 * which don't have one */ 397 } else { 398 /* Remove existing FCS */ 399 tx_len -= 4; 400 } 401 402 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 403 /* Loopback */ 404 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 405 if (nc->info->can_receive(nc)) { 406 s->loopback_packet = 1; 407 nc->info->receive(nc, s->tx_buffer, tx_len); 408 } 409 } else { 410 /* Transmit packet */ 411 qemu_send_packet(nc, s->tx_buffer, tx_len); 412 } 413 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 414 415 /* Write status */ 416 data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */ 417 size = sizeof(uint16_t) * width; 418 address_space_rw(&s->as, 419 (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA], 420 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 421 422 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 423 /* Read footer of packet */ 424 size = sizeof(uint16_t) * width; 425 address_space_rw(&s->as, 426 ((s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]) + sizeof(uint16_t) * (4 + 3 * s->regs[SONIC_TFC]) * width, 427 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 428 s->regs[SONIC_CTDA] = data[0 * width] & ~0x1; 429 if (data[0 * width] & 0x1) { 430 /* EOL detected */ 431 break; 432 } 433 } 434 } 435 436 /* Done */ 437 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 438 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 439 dp8393x_update_irq(s); 440 } 441 442 static void do_halt_transmission(dp8393xState *s) 443 { 444 /* Nothing to do */ 445 } 446 447 static void do_command(dp8393xState *s, uint16_t command) 448 { 449 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 450 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 451 return; 452 } 453 454 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 455 456 if (command & SONIC_CR_HTX) 457 do_halt_transmission(s); 458 if (command & SONIC_CR_TXP) 459 do_transmit_packets(s); 460 if (command & SONIC_CR_RXDIS) 461 do_receiver_disable(s); 462 if (command & SONIC_CR_RXEN) 463 do_receiver_enable(s); 464 if (command & SONIC_CR_STP) 465 do_stop_timer(s); 466 if (command & SONIC_CR_ST) 467 do_start_timer(s); 468 if (command & SONIC_CR_RST) 469 do_software_reset(s); 470 if (command & SONIC_CR_RRRA) 471 do_read_rra(s); 472 if (command & SONIC_CR_LCAM) 473 do_load_cam(s); 474 } 475 476 static uint16_t read_register(dp8393xState *s, int reg) 477 { 478 uint16_t val = 0; 479 480 switch (reg) { 481 /* Update data before reading it */ 482 case SONIC_WT0: 483 case SONIC_WT1: 484 update_wt_regs(s); 485 val = s->regs[reg]; 486 break; 487 /* Accept read to some registers only when in reset mode */ 488 case SONIC_CAP2: 489 case SONIC_CAP1: 490 case SONIC_CAP0: 491 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 492 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 493 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 494 } 495 break; 496 /* All other registers have no special contrainst */ 497 default: 498 val = s->regs[reg]; 499 } 500 501 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 502 503 return val; 504 } 505 506 static void write_register(dp8393xState *s, int reg, uint16_t val) 507 { 508 DPRINTF("write 0x%04x to reg %s\n", val, reg_names[reg]); 509 510 switch (reg) { 511 /* Command register */ 512 case SONIC_CR: 513 do_command(s, val); 514 break; 515 /* Prevent write to read-only registers */ 516 case SONIC_CAP2: 517 case SONIC_CAP1: 518 case SONIC_CAP0: 519 case SONIC_SR: 520 case SONIC_MDT: 521 DPRINTF("writing to reg %d invalid\n", reg); 522 break; 523 /* Accept write to some registers only when in reset mode */ 524 case SONIC_DCR: 525 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 526 s->regs[reg] = val & 0xbfff; 527 } else { 528 DPRINTF("writing to DCR invalid\n"); 529 } 530 break; 531 case SONIC_DCR2: 532 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 533 s->regs[reg] = val & 0xf017; 534 } else { 535 DPRINTF("writing to DCR2 invalid\n"); 536 } 537 break; 538 /* 12 lower bytes are Read Only */ 539 case SONIC_TCR: 540 s->regs[reg] = val & 0xf000; 541 break; 542 /* 9 lower bytes are Read Only */ 543 case SONIC_RCR: 544 s->regs[reg] = val & 0xffe0; 545 break; 546 /* Ignore most significant bit */ 547 case SONIC_IMR: 548 s->regs[reg] = val & 0x7fff; 549 dp8393x_update_irq(s); 550 break; 551 /* Clear bits by writing 1 to them */ 552 case SONIC_ISR: 553 val &= s->regs[reg]; 554 s->regs[reg] &= ~val; 555 if (val & SONIC_ISR_RBE) { 556 do_read_rra(s); 557 } 558 dp8393x_update_irq(s); 559 break; 560 /* Ignore least significant bit */ 561 case SONIC_RSA: 562 case SONIC_REA: 563 case SONIC_RRP: 564 case SONIC_RWP: 565 s->regs[reg] = val & 0xfffe; 566 break; 567 /* Invert written value for some registers */ 568 case SONIC_CRCT: 569 case SONIC_FAET: 570 case SONIC_MPT: 571 s->regs[reg] = val ^ 0xffff; 572 break; 573 /* All other registers have no special contrainst */ 574 default: 575 s->regs[reg] = val; 576 } 577 578 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 579 set_next_tick(s); 580 } 581 } 582 583 static void dp8393x_watchdog(void *opaque) 584 { 585 dp8393xState *s = opaque; 586 587 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 588 return; 589 } 590 591 s->regs[SONIC_WT1] = 0xffff; 592 s->regs[SONIC_WT0] = 0xffff; 593 set_next_tick(s); 594 595 /* Signal underflow */ 596 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 597 dp8393x_update_irq(s); 598 } 599 600 static uint32_t dp8393x_readw(void *opaque, hwaddr addr) 601 { 602 dp8393xState *s = opaque; 603 int reg; 604 605 if ((addr & ((1 << s->it_shift) - 1)) != 0) { 606 return 0; 607 } 608 609 reg = addr >> s->it_shift; 610 return read_register(s, reg); 611 } 612 613 static uint32_t dp8393x_readb(void *opaque, hwaddr addr) 614 { 615 uint16_t v = dp8393x_readw(opaque, addr & ~0x1); 616 return (v >> (8 * (addr & 0x1))) & 0xff; 617 } 618 619 static uint32_t dp8393x_readl(void *opaque, hwaddr addr) 620 { 621 uint32_t v; 622 v = dp8393x_readw(opaque, addr); 623 v |= dp8393x_readw(opaque, addr + 2) << 16; 624 return v; 625 } 626 627 static void dp8393x_writew(void *opaque, hwaddr addr, uint32_t val) 628 { 629 dp8393xState *s = opaque; 630 int reg; 631 632 if ((addr & ((1 << s->it_shift) - 1)) != 0) { 633 return; 634 } 635 636 reg = addr >> s->it_shift; 637 638 write_register(s, reg, (uint16_t)val); 639 } 640 641 static void dp8393x_writeb(void *opaque, hwaddr addr, uint32_t val) 642 { 643 uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1); 644 645 switch (addr & 3) { 646 case 0: 647 val = val | (old_val & 0xff00); 648 break; 649 case 1: 650 val = (val << 8) | (old_val & 0x00ff); 651 break; 652 } 653 dp8393x_writew(opaque, addr & ~0x1, val); 654 } 655 656 static void dp8393x_writel(void *opaque, hwaddr addr, uint32_t val) 657 { 658 dp8393x_writew(opaque, addr, val & 0xffff); 659 dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff); 660 } 661 662 static const MemoryRegionOps dp8393x_ops = { 663 .old_mmio = { 664 .read = { dp8393x_readb, dp8393x_readw, dp8393x_readl, }, 665 .write = { dp8393x_writeb, dp8393x_writew, dp8393x_writel, }, 666 }, 667 .endianness = DEVICE_NATIVE_ENDIAN, 668 }; 669 670 static int nic_can_receive(NetClientState *nc) 671 { 672 dp8393xState *s = qemu_get_nic_opaque(nc); 673 674 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 675 return 0; 676 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 677 return 0; 678 return 1; 679 } 680 681 static int receive_filter(dp8393xState *s, const uint8_t * buf, int size) 682 { 683 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 684 int i; 685 686 /* Check for runt packet (remember that checksum is not there) */ 687 if (size < 64 - 4) { 688 return (s->regs[SONIC_RCR] & SONIC_RCR_RNT) ? 0 : -1; 689 } 690 691 /* Check promiscuous mode */ 692 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 693 return 0; 694 } 695 696 /* Check multicast packets */ 697 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 698 return SONIC_RCR_MC; 699 } 700 701 /* Check broadcast */ 702 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 703 return SONIC_RCR_BC; 704 } 705 706 /* Check CAM */ 707 for (i = 0; i < 16; i++) { 708 if (s->regs[SONIC_CE] & (1 << i)) { 709 /* Entry enabled */ 710 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 711 return 0; 712 } 713 } 714 } 715 716 return -1; 717 } 718 719 static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t size) 720 { 721 dp8393xState *s = qemu_get_nic_opaque(nc); 722 uint16_t data[10]; 723 int packet_type; 724 uint32_t available, address; 725 int width, rx_len = size; 726 uint32_t checksum; 727 728 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 729 730 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 731 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 732 733 packet_type = receive_filter(s, buf, size); 734 if (packet_type < 0) { 735 DPRINTF("packet not for netcard\n"); 736 return -1; 737 } 738 739 /* XXX: Check byte ordering */ 740 741 /* Check for EOL */ 742 if (s->regs[SONIC_LLFA] & 0x1) { 743 /* Are we still in resource exhaustion? */ 744 size = sizeof(uint16_t) * 1 * width; 745 address = ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width; 746 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, 747 (uint8_t *)data, size, 0); 748 if (data[0 * width] & 0x1) { 749 /* Still EOL ; stop reception */ 750 return -1; 751 } else { 752 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 753 } 754 } 755 756 /* Save current position */ 757 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 758 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 759 760 /* Calculate the ethernet checksum */ 761 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 762 763 /* Put packet into RBA */ 764 DPRINTF("Receive packet at %08x\n", (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]); 765 address = (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 766 address_space_rw(&s->as, address, 767 MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1); 768 address += rx_len; 769 address_space_rw(&s->as, address, 770 MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); 771 rx_len += 4; 772 s->regs[SONIC_CRBA1] = address >> 16; 773 s->regs[SONIC_CRBA0] = address & 0xffff; 774 available = (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 775 available -= rx_len / 2; 776 s->regs[SONIC_RBWC1] = available >> 16; 777 s->regs[SONIC_RBWC0] = available & 0xffff; 778 779 /* Update status */ 780 if (((s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]) < s->regs[SONIC_EOBC]) { 781 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 782 } 783 s->regs[SONIC_RCR] |= packet_type; 784 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 785 if (s->loopback_packet) { 786 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 787 s->loopback_packet = 0; 788 } 789 790 /* Write status to memory */ 791 DPRINTF("Write status at %08x\n", (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]); 792 data[0 * width] = s->regs[SONIC_RCR]; /* status */ 793 data[1 * width] = rx_len; /* byte count */ 794 data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */ 795 data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */ 796 data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */ 797 size = sizeof(uint16_t) * 5 * width; 798 address_space_rw(&s->as, (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA], 799 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 800 801 /* Move to next descriptor */ 802 size = sizeof(uint16_t) * width; 803 address_space_rw(&s->as, 804 ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 5 * width, 805 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0); 806 s->regs[SONIC_LLFA] = data[0 * width]; 807 if (s->regs[SONIC_LLFA] & 0x1) { 808 /* EOL detected */ 809 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 810 } else { 811 data[0 * width] = 0; /* in_use */ 812 address_space_rw(&s->as, 813 ((s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]) + sizeof(uint16_t) * 6 * width, 814 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1); 815 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 816 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 817 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 818 819 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 820 /* Read next RRA */ 821 do_read_rra(s); 822 } 823 } 824 825 /* Done */ 826 dp8393x_update_irq(s); 827 828 return size; 829 } 830 831 static void nic_reset(void *opaque) 832 { 833 dp8393xState *s = opaque; 834 timer_del(s->watchdog); 835 836 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 837 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 838 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 839 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 840 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 841 s->regs[SONIC_IMR] = 0; 842 s->regs[SONIC_ISR] = 0; 843 s->regs[SONIC_DCR2] = 0; 844 s->regs[SONIC_EOBC] = 0x02F8; 845 s->regs[SONIC_RSC] = 0; 846 s->regs[SONIC_CE] = 0; 847 s->regs[SONIC_RSC] = 0; 848 849 /* Network cable is connected */ 850 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 851 852 dp8393x_update_irq(s); 853 } 854 855 static NetClientInfo net_dp83932_info = { 856 .type = NET_CLIENT_OPTIONS_KIND_NIC, 857 .size = sizeof(NICState), 858 .can_receive = nic_can_receive, 859 .receive = nic_receive, 860 }; 861 862 void dp83932_init(NICInfo *nd, hwaddr base, int it_shift, 863 MemoryRegion *address_space, 864 qemu_irq irq, MemoryRegion *dma_mr) 865 { 866 dp8393xState *s; 867 868 qemu_check_nic_model(nd, "dp83932"); 869 870 s = g_malloc0(sizeof(dp8393xState)); 871 872 s->address_space = address_space; 873 address_space_init(&s->as, dma_mr, "dp8393x-dma"); 874 s->it_shift = it_shift; 875 s->irq = irq; 876 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 877 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 878 879 s->conf.macaddr = nd->macaddr; 880 s->conf.peers.ncs[0] = nd->netdev; 881 882 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s); 883 884 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 885 qemu_register_reset(nic_reset, s); 886 nic_reset(s); 887 888 memory_region_init_io(&s->mmio, NULL, &dp8393x_ops, s, 889 "dp8393x", 0x40 << it_shift); 890 memory_region_add_subregion(address_space, base, &s->mmio); 891 } 892