1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 31 //#define DEBUG_SONIC 32 33 #define SONIC_PROM_SIZE 0x1000 34 35 #ifdef DEBUG_SONIC 36 #define DPRINTF(fmt, ...) \ 37 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 38 static const char* reg_names[] = { 39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 47 #else 48 #define DPRINTF(fmt, ...) do {} while (0) 49 #endif 50 51 #define SONIC_ERROR(fmt, ...) \ 52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 53 54 #define SONIC_CR 0x00 55 #define SONIC_DCR 0x01 56 #define SONIC_RCR 0x02 57 #define SONIC_TCR 0x03 58 #define SONIC_IMR 0x04 59 #define SONIC_ISR 0x05 60 #define SONIC_UTDA 0x06 61 #define SONIC_CTDA 0x07 62 #define SONIC_TPS 0x08 63 #define SONIC_TFC 0x09 64 #define SONIC_TSA0 0x0a 65 #define SONIC_TSA1 0x0b 66 #define SONIC_TFS 0x0c 67 #define SONIC_URDA 0x0d 68 #define SONIC_CRDA 0x0e 69 #define SONIC_CRBA0 0x0f 70 #define SONIC_CRBA1 0x10 71 #define SONIC_RBWC0 0x11 72 #define SONIC_RBWC1 0x12 73 #define SONIC_EOBC 0x13 74 #define SONIC_URRA 0x14 75 #define SONIC_RSA 0x15 76 #define SONIC_REA 0x16 77 #define SONIC_RRP 0x17 78 #define SONIC_RWP 0x18 79 #define SONIC_TRBA0 0x19 80 #define SONIC_TRBA1 0x1a 81 #define SONIC_LLFA 0x1f 82 #define SONIC_TTDA 0x20 83 #define SONIC_CEP 0x21 84 #define SONIC_CAP2 0x22 85 #define SONIC_CAP1 0x23 86 #define SONIC_CAP0 0x24 87 #define SONIC_CE 0x25 88 #define SONIC_CDP 0x26 89 #define SONIC_CDC 0x27 90 #define SONIC_SR 0x28 91 #define SONIC_WT0 0x29 92 #define SONIC_WT1 0x2a 93 #define SONIC_RSC 0x2b 94 #define SONIC_CRCT 0x2c 95 #define SONIC_FAET 0x2d 96 #define SONIC_MPT 0x2e 97 #define SONIC_MDT 0x2f 98 #define SONIC_DCR2 0x3f 99 100 #define SONIC_CR_HTX 0x0001 101 #define SONIC_CR_TXP 0x0002 102 #define SONIC_CR_RXDIS 0x0004 103 #define SONIC_CR_RXEN 0x0008 104 #define SONIC_CR_STP 0x0010 105 #define SONIC_CR_ST 0x0020 106 #define SONIC_CR_RST 0x0080 107 #define SONIC_CR_RRRA 0x0100 108 #define SONIC_CR_LCAM 0x0200 109 #define SONIC_CR_MASK 0x03bf 110 111 #define SONIC_DCR_DW 0x0020 112 #define SONIC_DCR_LBR 0x2000 113 #define SONIC_DCR_EXBUS 0x8000 114 115 #define SONIC_RCR_PRX 0x0001 116 #define SONIC_RCR_LBK 0x0002 117 #define SONIC_RCR_FAER 0x0004 118 #define SONIC_RCR_CRCR 0x0008 119 #define SONIC_RCR_CRS 0x0020 120 #define SONIC_RCR_LPKT 0x0040 121 #define SONIC_RCR_BC 0x0080 122 #define SONIC_RCR_MC 0x0100 123 #define SONIC_RCR_LB0 0x0200 124 #define SONIC_RCR_LB1 0x0400 125 #define SONIC_RCR_AMC 0x0800 126 #define SONIC_RCR_PRO 0x1000 127 #define SONIC_RCR_BRD 0x2000 128 #define SONIC_RCR_RNT 0x4000 129 130 #define SONIC_TCR_PTX 0x0001 131 #define SONIC_TCR_BCM 0x0002 132 #define SONIC_TCR_FU 0x0004 133 #define SONIC_TCR_EXC 0x0040 134 #define SONIC_TCR_CRSL 0x0080 135 #define SONIC_TCR_NCRS 0x0100 136 #define SONIC_TCR_EXD 0x0400 137 #define SONIC_TCR_CRCI 0x2000 138 #define SONIC_TCR_PINT 0x8000 139 140 #define SONIC_ISR_RBAE 0x0010 141 #define SONIC_ISR_RBE 0x0020 142 #define SONIC_ISR_RDE 0x0040 143 #define SONIC_ISR_TC 0x0080 144 #define SONIC_ISR_TXDN 0x0200 145 #define SONIC_ISR_PKTRX 0x0400 146 #define SONIC_ISR_PINT 0x0800 147 #define SONIC_ISR_LCD 0x1000 148 149 #define SONIC_DESC_EOL 0x0001 150 #define SONIC_DESC_ADDR 0xFFFE 151 152 #define TYPE_DP8393X "dp8393x" 153 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 154 155 typedef struct dp8393xState { 156 SysBusDevice parent_obj; 157 158 /* Hardware */ 159 uint8_t it_shift; 160 bool big_endian; 161 qemu_irq irq; 162 #ifdef DEBUG_SONIC 163 int irq_level; 164 #endif 165 QEMUTimer *watchdog; 166 int64_t wt_last_update; 167 NICConf conf; 168 NICState *nic; 169 MemoryRegion mmio; 170 MemoryRegion prom; 171 172 /* Registers */ 173 uint8_t cam[16][6]; 174 uint16_t regs[0x40]; 175 176 /* Temporaries */ 177 uint8_t tx_buffer[0x10000]; 178 uint16_t data[12]; 179 int loopback_packet; 180 181 /* Memory access */ 182 MemoryRegion *dma_mr; 183 AddressSpace as; 184 } dp8393xState; 185 186 /* Accessor functions for values which are formed by 187 * concatenating two 16 bit device registers. By putting these 188 * in their own functions with a uint32_t return type we avoid the 189 * pitfall of implicit sign extension where ((x << 16) | y) is a 190 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 191 */ 192 static uint32_t dp8393x_cdp(dp8393xState *s) 193 { 194 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 195 } 196 197 static uint32_t dp8393x_crba(dp8393xState *s) 198 { 199 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 200 } 201 202 static uint32_t dp8393x_crda(dp8393xState *s) 203 { 204 return (s->regs[SONIC_URDA] << 16) | 205 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); 206 } 207 208 static uint32_t dp8393x_rbwc(dp8393xState *s) 209 { 210 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 211 } 212 213 static uint32_t dp8393x_rrp(dp8393xState *s) 214 { 215 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 216 } 217 218 static uint32_t dp8393x_tsa(dp8393xState *s) 219 { 220 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 221 } 222 223 static uint32_t dp8393x_ttda(dp8393xState *s) 224 { 225 return (s->regs[SONIC_UTDA] << 16) | 226 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR); 227 } 228 229 static uint32_t dp8393x_wt(dp8393xState *s) 230 { 231 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 232 } 233 234 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 235 { 236 uint16_t val; 237 238 if (s->big_endian) { 239 val = be16_to_cpu(s->data[offset * width + width - 1]); 240 } else { 241 val = le16_to_cpu(s->data[offset * width]); 242 } 243 return val; 244 } 245 246 static void dp8393x_put(dp8393xState *s, int width, int offset, 247 uint16_t val) 248 { 249 if (s->big_endian) { 250 if (width == 2) { 251 s->data[offset * 2] = 0; 252 s->data[offset * 2 + 1] = cpu_to_be16(val); 253 } else { 254 s->data[offset] = cpu_to_be16(val); 255 } 256 } else { 257 if (width == 2) { 258 s->data[offset * 2] = cpu_to_le16(val); 259 s->data[offset * 2 + 1] = 0; 260 } else { 261 s->data[offset] = cpu_to_le16(val); 262 } 263 } 264 } 265 266 static void dp8393x_update_irq(dp8393xState *s) 267 { 268 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 269 270 #ifdef DEBUG_SONIC 271 if (level != s->irq_level) { 272 s->irq_level = level; 273 if (level) { 274 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 275 } else { 276 DPRINTF("lower irq\n"); 277 } 278 } 279 #endif 280 281 qemu_set_irq(s->irq, level); 282 } 283 284 static void dp8393x_do_load_cam(dp8393xState *s) 285 { 286 int width, size; 287 uint16_t index = 0; 288 289 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 290 size = sizeof(uint16_t) * 4 * width; 291 292 while (s->regs[SONIC_CDC] & 0x1f) { 293 /* Fill current entry */ 294 address_space_read(&s->as, dp8393x_cdp(s), 295 MEMTXATTRS_UNSPECIFIED, s->data, size); 296 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 297 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 298 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 299 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 300 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 301 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 302 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 303 s->cam[index][0], s->cam[index][1], s->cam[index][2], 304 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 305 /* Move to next entry */ 306 s->regs[SONIC_CDC]--; 307 s->regs[SONIC_CDP] += size; 308 index++; 309 } 310 311 /* Read CAM enable */ 312 address_space_read(&s->as, dp8393x_cdp(s), 313 MEMTXATTRS_UNSPECIFIED, s->data, size); 314 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 315 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 316 317 /* Done */ 318 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 319 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 320 dp8393x_update_irq(s); 321 } 322 323 static void dp8393x_do_read_rra(dp8393xState *s) 324 { 325 int width, size; 326 327 /* Read memory */ 328 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 329 size = sizeof(uint16_t) * 4 * width; 330 address_space_read(&s->as, dp8393x_rrp(s), 331 MEMTXATTRS_UNSPECIFIED, s->data, size); 332 333 /* Update SONIC registers */ 334 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 335 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 336 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 337 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 338 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 339 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 340 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 341 342 /* Go to next entry */ 343 s->regs[SONIC_RRP] += size; 344 345 /* Handle wrap */ 346 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 347 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 348 } 349 350 /* Check resource exhaustion */ 351 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 352 { 353 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 354 dp8393x_update_irq(s); 355 } 356 } 357 358 static void dp8393x_do_software_reset(dp8393xState *s) 359 { 360 timer_del(s->watchdog); 361 362 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 363 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 364 } 365 366 static void dp8393x_set_next_tick(dp8393xState *s) 367 { 368 uint32_t ticks; 369 int64_t delay; 370 371 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 372 timer_del(s->watchdog); 373 return; 374 } 375 376 ticks = dp8393x_wt(s); 377 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 378 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 379 timer_mod(s->watchdog, s->wt_last_update + delay); 380 } 381 382 static void dp8393x_update_wt_regs(dp8393xState *s) 383 { 384 int64_t elapsed; 385 uint32_t val; 386 387 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 388 timer_del(s->watchdog); 389 return; 390 } 391 392 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 393 val = dp8393x_wt(s); 394 val -= elapsed / 5000000; 395 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 396 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 397 dp8393x_set_next_tick(s); 398 399 } 400 401 static void dp8393x_do_start_timer(dp8393xState *s) 402 { 403 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 404 dp8393x_set_next_tick(s); 405 } 406 407 static void dp8393x_do_stop_timer(dp8393xState *s) 408 { 409 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 410 dp8393x_update_wt_regs(s); 411 } 412 413 static int dp8393x_can_receive(NetClientState *nc); 414 415 static void dp8393x_do_receiver_enable(dp8393xState *s) 416 { 417 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 418 if (dp8393x_can_receive(s->nic->ncs)) { 419 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 420 } 421 } 422 423 static void dp8393x_do_receiver_disable(dp8393xState *s) 424 { 425 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 426 } 427 428 static void dp8393x_do_transmit_packets(dp8393xState *s) 429 { 430 NetClientState *nc = qemu_get_queue(s->nic); 431 int width, size; 432 int tx_len, len; 433 uint16_t i; 434 435 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 436 437 while (1) { 438 /* Read memory */ 439 size = sizeof(uint16_t) * 6 * width; 440 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 441 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 442 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 443 MEMTXATTRS_UNSPECIFIED, s->data, size); 444 tx_len = 0; 445 446 /* Update registers */ 447 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 448 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 449 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 450 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 451 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 452 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 453 454 /* Handle programmable interrupt */ 455 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 456 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 457 } else { 458 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 459 } 460 461 for (i = 0; i < s->regs[SONIC_TFC]; ) { 462 /* Append fragment */ 463 len = s->regs[SONIC_TFS]; 464 if (tx_len + len > sizeof(s->tx_buffer)) { 465 len = sizeof(s->tx_buffer) - tx_len; 466 } 467 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, 468 &s->tx_buffer[tx_len], len); 469 tx_len += len; 470 471 i++; 472 if (i != s->regs[SONIC_TFC]) { 473 /* Read next fragment details */ 474 size = sizeof(uint16_t) * 3 * width; 475 address_space_read(&s->as, 476 dp8393x_ttda(s) 477 + sizeof(uint16_t) * width * (4 + 3 * i), 478 MEMTXATTRS_UNSPECIFIED, s->data, 479 size); 480 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 481 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 482 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 483 } 484 } 485 486 /* Handle Ethernet checksum */ 487 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 488 /* Don't append FCS there, to look like slirp packets 489 * which don't have one */ 490 } else { 491 /* Remove existing FCS */ 492 tx_len -= 4; 493 } 494 495 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 496 /* Loopback */ 497 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 498 if (nc->info->can_receive(nc)) { 499 s->loopback_packet = 1; 500 nc->info->receive(nc, s->tx_buffer, tx_len); 501 } 502 } else { 503 /* Transmit packet */ 504 qemu_send_packet(nc, s->tx_buffer, tx_len); 505 } 506 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 507 508 /* Write status */ 509 dp8393x_put(s, width, 0, 510 s->regs[SONIC_TCR] & 0x0fff); /* status */ 511 size = sizeof(uint16_t) * width; 512 address_space_write(&s->as, dp8393x_ttda(s), 513 MEMTXATTRS_UNSPECIFIED, s->data, size); 514 515 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 516 /* Read footer of packet */ 517 size = sizeof(uint16_t) * width; 518 address_space_read(&s->as, 519 dp8393x_ttda(s) 520 + sizeof(uint16_t) * width 521 * (4 + 3 * s->regs[SONIC_TFC]), 522 MEMTXATTRS_UNSPECIFIED, s->data, 523 size); 524 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; 525 if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) { 526 /* EOL detected */ 527 break; 528 } 529 } 530 } 531 532 /* Done */ 533 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 534 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 535 dp8393x_update_irq(s); 536 } 537 538 static void dp8393x_do_halt_transmission(dp8393xState *s) 539 { 540 /* Nothing to do */ 541 } 542 543 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 544 { 545 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 546 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 547 return; 548 } 549 550 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 551 552 if (command & SONIC_CR_HTX) 553 dp8393x_do_halt_transmission(s); 554 if (command & SONIC_CR_TXP) 555 dp8393x_do_transmit_packets(s); 556 if (command & SONIC_CR_RXDIS) 557 dp8393x_do_receiver_disable(s); 558 if (command & SONIC_CR_RXEN) 559 dp8393x_do_receiver_enable(s); 560 if (command & SONIC_CR_STP) 561 dp8393x_do_stop_timer(s); 562 if (command & SONIC_CR_ST) 563 dp8393x_do_start_timer(s); 564 if (command & SONIC_CR_RST) 565 dp8393x_do_software_reset(s); 566 if (command & SONIC_CR_RRRA) { 567 dp8393x_do_read_rra(s); 568 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 569 } 570 if (command & SONIC_CR_LCAM) 571 dp8393x_do_load_cam(s); 572 } 573 574 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 575 { 576 dp8393xState *s = opaque; 577 int reg = addr >> s->it_shift; 578 uint16_t val = 0; 579 580 switch (reg) { 581 /* Update data before reading it */ 582 case SONIC_WT0: 583 case SONIC_WT1: 584 dp8393x_update_wt_regs(s); 585 val = s->regs[reg]; 586 break; 587 /* Accept read to some registers only when in reset mode */ 588 case SONIC_CAP2: 589 case SONIC_CAP1: 590 case SONIC_CAP0: 591 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 592 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 593 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 594 } 595 break; 596 /* All other registers have no special contrainst */ 597 default: 598 val = s->regs[reg]; 599 } 600 601 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 602 603 return s->big_endian ? val << 16 : val; 604 } 605 606 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 607 unsigned int size) 608 { 609 dp8393xState *s = opaque; 610 int reg = addr >> s->it_shift; 611 uint32_t val = s->big_endian ? data >> 16 : data; 612 613 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); 614 615 switch (reg) { 616 /* Command register */ 617 case SONIC_CR: 618 dp8393x_do_command(s, val); 619 break; 620 /* Prevent write to read-only registers */ 621 case SONIC_CAP2: 622 case SONIC_CAP1: 623 case SONIC_CAP0: 624 case SONIC_SR: 625 case SONIC_MDT: 626 DPRINTF("writing to reg %d invalid\n", reg); 627 break; 628 /* Accept write to some registers only when in reset mode */ 629 case SONIC_DCR: 630 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 631 s->regs[reg] = val & 0xbfff; 632 } else { 633 DPRINTF("writing to DCR invalid\n"); 634 } 635 break; 636 case SONIC_DCR2: 637 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 638 s->regs[reg] = val & 0xf017; 639 } else { 640 DPRINTF("writing to DCR2 invalid\n"); 641 } 642 break; 643 /* 12 lower bytes are Read Only */ 644 case SONIC_TCR: 645 s->regs[reg] = val & 0xf000; 646 break; 647 /* 9 lower bytes are Read Only */ 648 case SONIC_RCR: 649 s->regs[reg] = val & 0xffe0; 650 break; 651 /* Ignore most significant bit */ 652 case SONIC_IMR: 653 s->regs[reg] = val & 0x7fff; 654 dp8393x_update_irq(s); 655 break; 656 /* Clear bits by writing 1 to them */ 657 case SONIC_ISR: 658 val &= s->regs[reg]; 659 s->regs[reg] &= ~val; 660 if (val & SONIC_ISR_RBE) { 661 dp8393x_do_read_rra(s); 662 } 663 dp8393x_update_irq(s); 664 if (dp8393x_can_receive(s->nic->ncs)) { 665 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 666 } 667 break; 668 /* Ignore least significant bit */ 669 case SONIC_RSA: 670 case SONIC_REA: 671 case SONIC_RRP: 672 case SONIC_RWP: 673 s->regs[reg] = val & 0xfffe; 674 break; 675 /* Invert written value for some registers */ 676 case SONIC_CRCT: 677 case SONIC_FAET: 678 case SONIC_MPT: 679 s->regs[reg] = val ^ 0xffff; 680 break; 681 /* All other registers have no special contrainst */ 682 default: 683 s->regs[reg] = val; 684 } 685 686 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 687 dp8393x_set_next_tick(s); 688 } 689 } 690 691 static const MemoryRegionOps dp8393x_ops = { 692 .read = dp8393x_read, 693 .write = dp8393x_write, 694 .impl.min_access_size = 4, 695 .impl.max_access_size = 4, 696 .endianness = DEVICE_NATIVE_ENDIAN, 697 }; 698 699 static void dp8393x_watchdog(void *opaque) 700 { 701 dp8393xState *s = opaque; 702 703 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 704 return; 705 } 706 707 s->regs[SONIC_WT1] = 0xffff; 708 s->regs[SONIC_WT0] = 0xffff; 709 dp8393x_set_next_tick(s); 710 711 /* Signal underflow */ 712 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 713 dp8393x_update_irq(s); 714 } 715 716 static int dp8393x_can_receive(NetClientState *nc) 717 { 718 dp8393xState *s = qemu_get_nic_opaque(nc); 719 720 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 721 return 0; 722 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 723 return 0; 724 return 1; 725 } 726 727 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 728 int size) 729 { 730 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 731 int i; 732 733 /* Check promiscuous mode */ 734 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 735 return 0; 736 } 737 738 /* Check multicast packets */ 739 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 740 return SONIC_RCR_MC; 741 } 742 743 /* Check broadcast */ 744 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 745 return SONIC_RCR_BC; 746 } 747 748 /* Check CAM */ 749 for (i = 0; i < 16; i++) { 750 if (s->regs[SONIC_CE] & (1 << i)) { 751 /* Entry enabled */ 752 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 753 return 0; 754 } 755 } 756 } 757 758 return -1; 759 } 760 761 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 762 size_t pkt_size) 763 { 764 dp8393xState *s = qemu_get_nic_opaque(nc); 765 int packet_type; 766 uint32_t available, address; 767 int width, rx_len = pkt_size; 768 uint32_t checksum; 769 int size; 770 771 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 772 773 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 774 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 775 776 if (pkt_size + 4 > dp8393x_rbwc(s) * 2) { 777 DPRINTF("oversize packet, pkt_size is %d\n", pkt_size); 778 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE; 779 dp8393x_update_irq(s); 780 dp8393x_do_read_rra(s); 781 return pkt_size; 782 } 783 784 packet_type = dp8393x_receive_filter(s, buf, pkt_size); 785 if (packet_type < 0) { 786 DPRINTF("packet not for netcard\n"); 787 return -1; 788 } 789 790 /* Check for EOL */ 791 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 792 /* Are we still in resource exhaustion? */ 793 size = sizeof(uint16_t) * 1 * width; 794 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 795 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, 796 s->data, size); 797 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 798 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 799 /* Still EOL ; stop reception */ 800 return -1; 801 } 802 /* Link has been updated by host */ 803 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 804 } 805 806 /* Save current position */ 807 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 808 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 809 810 /* Calculate the ethernet checksum */ 811 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 812 813 /* Put packet into RBA */ 814 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); 815 address = dp8393x_crba(s); 816 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 817 buf, rx_len); 818 address += rx_len; 819 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 820 &checksum, 4); 821 address += 4; 822 rx_len += 4; 823 s->regs[SONIC_CRBA1] = address >> 16; 824 s->regs[SONIC_CRBA0] = address & 0xffff; 825 available = dp8393x_rbwc(s); 826 available -= rx_len / 2; 827 s->regs[SONIC_RBWC1] = available >> 16; 828 s->regs[SONIC_RBWC0] = available & 0xffff; 829 830 /* Update status */ 831 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 832 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 833 } 834 s->regs[SONIC_RCR] |= packet_type; 835 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 836 if (s->loopback_packet) { 837 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 838 s->loopback_packet = 0; 839 } 840 841 /* Write status to memory */ 842 DPRINTF("Write status at %08x\n", dp8393x_crda(s)); 843 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 844 dp8393x_put(s, width, 1, rx_len); /* byte count */ 845 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 846 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 847 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 848 size = sizeof(uint16_t) * 5 * width; 849 address_space_write(&s->as, dp8393x_crda(s), 850 MEMTXATTRS_UNSPECIFIED, 851 s->data, size); 852 853 /* Check link field */ 854 size = sizeof(uint16_t) * width; 855 address_space_read(&s->as, 856 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 857 MEMTXATTRS_UNSPECIFIED, s->data, size); 858 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 859 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 860 /* EOL detected */ 861 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 862 } else { 863 /* Clear in_use */ 864 size = sizeof(uint16_t) * width; 865 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 866 dp8393x_put(s, width, 0, 0); 867 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 868 s->data, size); 869 870 /* Move to next descriptor */ 871 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 872 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 873 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 874 875 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 876 /* Read next RRA */ 877 dp8393x_do_read_rra(s); 878 } 879 } 880 881 /* Done */ 882 dp8393x_update_irq(s); 883 884 return pkt_size; 885 } 886 887 static void dp8393x_reset(DeviceState *dev) 888 { 889 dp8393xState *s = DP8393X(dev); 890 timer_del(s->watchdog); 891 892 memset(s->regs, 0, sizeof(s->regs)); 893 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 894 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 895 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 896 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 897 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 898 s->regs[SONIC_IMR] = 0; 899 s->regs[SONIC_ISR] = 0; 900 s->regs[SONIC_DCR2] = 0; 901 s->regs[SONIC_EOBC] = 0x02F8; 902 s->regs[SONIC_RSC] = 0; 903 s->regs[SONIC_CE] = 0; 904 s->regs[SONIC_RSC] = 0; 905 906 /* Network cable is connected */ 907 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 908 909 dp8393x_update_irq(s); 910 } 911 912 static NetClientInfo net_dp83932_info = { 913 .type = NET_CLIENT_DRIVER_NIC, 914 .size = sizeof(NICState), 915 .can_receive = dp8393x_can_receive, 916 .receive = dp8393x_receive, 917 }; 918 919 static void dp8393x_instance_init(Object *obj) 920 { 921 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 922 dp8393xState *s = DP8393X(obj); 923 924 sysbus_init_mmio(sbd, &s->mmio); 925 sysbus_init_mmio(sbd, &s->prom); 926 sysbus_init_irq(sbd, &s->irq); 927 } 928 929 static void dp8393x_realize(DeviceState *dev, Error **errp) 930 { 931 dp8393xState *s = DP8393X(dev); 932 int i, checksum; 933 uint8_t *prom; 934 Error *local_err = NULL; 935 936 address_space_init(&s->as, s->dma_mr, "dp8393x"); 937 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 938 "dp8393x-regs", 0x40 << s->it_shift); 939 940 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 941 object_get_typename(OBJECT(dev)), dev->id, s); 942 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 943 944 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 945 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 946 947 memory_region_init_ram(&s->prom, OBJECT(dev), 948 "dp8393x-prom", SONIC_PROM_SIZE, &local_err); 949 if (local_err) { 950 error_propagate(errp, local_err); 951 return; 952 } 953 memory_region_set_readonly(&s->prom, true); 954 prom = memory_region_get_ram_ptr(&s->prom); 955 checksum = 0; 956 for (i = 0; i < 6; i++) { 957 prom[i] = s->conf.macaddr.a[i]; 958 checksum += prom[i]; 959 if (checksum > 0xff) { 960 checksum = (checksum + 1) & 0xff; 961 } 962 } 963 prom[7] = 0xff - checksum; 964 } 965 966 static const VMStateDescription vmstate_dp8393x = { 967 .name = "dp8393x", 968 .version_id = 0, 969 .minimum_version_id = 0, 970 .fields = (VMStateField []) { 971 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 972 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 973 VMSTATE_END_OF_LIST() 974 } 975 }; 976 977 static Property dp8393x_properties[] = { 978 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 979 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 980 TYPE_MEMORY_REGION, MemoryRegion *), 981 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 982 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 983 DEFINE_PROP_END_OF_LIST(), 984 }; 985 986 static void dp8393x_class_init(ObjectClass *klass, void *data) 987 { 988 DeviceClass *dc = DEVICE_CLASS(klass); 989 990 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 991 dc->realize = dp8393x_realize; 992 dc->reset = dp8393x_reset; 993 dc->vmsd = &vmstate_dp8393x; 994 device_class_set_props(dc, dp8393x_properties); 995 } 996 997 static const TypeInfo dp8393x_info = { 998 .name = TYPE_DP8393X, 999 .parent = TYPE_SYS_BUS_DEVICE, 1000 .instance_size = sizeof(dp8393xState), 1001 .instance_init = dp8393x_instance_init, 1002 .class_init = dp8393x_class_init, 1003 }; 1004 1005 static void dp8393x_register_types(void) 1006 { 1007 type_register_static(&dp8393x_info); 1008 } 1009 1010 type_init(dp8393x_register_types) 1011