1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 31 //#define DEBUG_SONIC 32 33 #define SONIC_PROM_SIZE 0x1000 34 35 #ifdef DEBUG_SONIC 36 #define DPRINTF(fmt, ...) \ 37 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 38 static const char* reg_names[] = { 39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 47 #else 48 #define DPRINTF(fmt, ...) do {} while (0) 49 #endif 50 51 #define SONIC_ERROR(fmt, ...) \ 52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 53 54 #define SONIC_CR 0x00 55 #define SONIC_DCR 0x01 56 #define SONIC_RCR 0x02 57 #define SONIC_TCR 0x03 58 #define SONIC_IMR 0x04 59 #define SONIC_ISR 0x05 60 #define SONIC_UTDA 0x06 61 #define SONIC_CTDA 0x07 62 #define SONIC_TPS 0x08 63 #define SONIC_TFC 0x09 64 #define SONIC_TSA0 0x0a 65 #define SONIC_TSA1 0x0b 66 #define SONIC_TFS 0x0c 67 #define SONIC_URDA 0x0d 68 #define SONIC_CRDA 0x0e 69 #define SONIC_CRBA0 0x0f 70 #define SONIC_CRBA1 0x10 71 #define SONIC_RBWC0 0x11 72 #define SONIC_RBWC1 0x12 73 #define SONIC_EOBC 0x13 74 #define SONIC_URRA 0x14 75 #define SONIC_RSA 0x15 76 #define SONIC_REA 0x16 77 #define SONIC_RRP 0x17 78 #define SONIC_RWP 0x18 79 #define SONIC_TRBA0 0x19 80 #define SONIC_TRBA1 0x1a 81 #define SONIC_LLFA 0x1f 82 #define SONIC_TTDA 0x20 83 #define SONIC_CEP 0x21 84 #define SONIC_CAP2 0x22 85 #define SONIC_CAP1 0x23 86 #define SONIC_CAP0 0x24 87 #define SONIC_CE 0x25 88 #define SONIC_CDP 0x26 89 #define SONIC_CDC 0x27 90 #define SONIC_SR 0x28 91 #define SONIC_WT0 0x29 92 #define SONIC_WT1 0x2a 93 #define SONIC_RSC 0x2b 94 #define SONIC_CRCT 0x2c 95 #define SONIC_FAET 0x2d 96 #define SONIC_MPT 0x2e 97 #define SONIC_MDT 0x2f 98 #define SONIC_DCR2 0x3f 99 100 #define SONIC_CR_HTX 0x0001 101 #define SONIC_CR_TXP 0x0002 102 #define SONIC_CR_RXDIS 0x0004 103 #define SONIC_CR_RXEN 0x0008 104 #define SONIC_CR_STP 0x0010 105 #define SONIC_CR_ST 0x0020 106 #define SONIC_CR_RST 0x0080 107 #define SONIC_CR_RRRA 0x0100 108 #define SONIC_CR_LCAM 0x0200 109 #define SONIC_CR_MASK 0x03bf 110 111 #define SONIC_DCR_DW 0x0020 112 #define SONIC_DCR_LBR 0x2000 113 #define SONIC_DCR_EXBUS 0x8000 114 115 #define SONIC_RCR_PRX 0x0001 116 #define SONIC_RCR_LBK 0x0002 117 #define SONIC_RCR_FAER 0x0004 118 #define SONIC_RCR_CRCR 0x0008 119 #define SONIC_RCR_CRS 0x0020 120 #define SONIC_RCR_LPKT 0x0040 121 #define SONIC_RCR_BC 0x0080 122 #define SONIC_RCR_MC 0x0100 123 #define SONIC_RCR_LB0 0x0200 124 #define SONIC_RCR_LB1 0x0400 125 #define SONIC_RCR_AMC 0x0800 126 #define SONIC_RCR_PRO 0x1000 127 #define SONIC_RCR_BRD 0x2000 128 #define SONIC_RCR_RNT 0x4000 129 130 #define SONIC_TCR_PTX 0x0001 131 #define SONIC_TCR_BCM 0x0002 132 #define SONIC_TCR_FU 0x0004 133 #define SONIC_TCR_EXC 0x0040 134 #define SONIC_TCR_CRSL 0x0080 135 #define SONIC_TCR_NCRS 0x0100 136 #define SONIC_TCR_EXD 0x0400 137 #define SONIC_TCR_CRCI 0x2000 138 #define SONIC_TCR_PINT 0x8000 139 140 #define SONIC_ISR_RBE 0x0020 141 #define SONIC_ISR_RDE 0x0040 142 #define SONIC_ISR_TC 0x0080 143 #define SONIC_ISR_TXDN 0x0200 144 #define SONIC_ISR_PKTRX 0x0400 145 #define SONIC_ISR_PINT 0x0800 146 #define SONIC_ISR_LCD 0x1000 147 148 #define SONIC_DESC_EOL 0x0001 149 #define SONIC_DESC_ADDR 0xFFFE 150 151 #define TYPE_DP8393X "dp8393x" 152 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 153 154 typedef struct dp8393xState { 155 SysBusDevice parent_obj; 156 157 /* Hardware */ 158 uint8_t it_shift; 159 bool big_endian; 160 qemu_irq irq; 161 #ifdef DEBUG_SONIC 162 int irq_level; 163 #endif 164 QEMUTimer *watchdog; 165 int64_t wt_last_update; 166 NICConf conf; 167 NICState *nic; 168 MemoryRegion mmio; 169 MemoryRegion prom; 170 171 /* Registers */ 172 uint8_t cam[16][6]; 173 uint16_t regs[0x40]; 174 175 /* Temporaries */ 176 uint8_t tx_buffer[0x10000]; 177 uint16_t data[12]; 178 int loopback_packet; 179 180 /* Memory access */ 181 MemoryRegion *dma_mr; 182 AddressSpace as; 183 } dp8393xState; 184 185 /* Accessor functions for values which are formed by 186 * concatenating two 16 bit device registers. By putting these 187 * in their own functions with a uint32_t return type we avoid the 188 * pitfall of implicit sign extension where ((x << 16) | y) is a 189 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 190 */ 191 static uint32_t dp8393x_cdp(dp8393xState *s) 192 { 193 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 194 } 195 196 static uint32_t dp8393x_crba(dp8393xState *s) 197 { 198 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 199 } 200 201 static uint32_t dp8393x_crda(dp8393xState *s) 202 { 203 return (s->regs[SONIC_URDA] << 16) | 204 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); 205 } 206 207 static uint32_t dp8393x_rbwc(dp8393xState *s) 208 { 209 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 210 } 211 212 static uint32_t dp8393x_rrp(dp8393xState *s) 213 { 214 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 215 } 216 217 static uint32_t dp8393x_tsa(dp8393xState *s) 218 { 219 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 220 } 221 222 static uint32_t dp8393x_ttda(dp8393xState *s) 223 { 224 return (s->regs[SONIC_UTDA] << 16) | 225 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR); 226 } 227 228 static uint32_t dp8393x_wt(dp8393xState *s) 229 { 230 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 231 } 232 233 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 234 { 235 uint16_t val; 236 237 if (s->big_endian) { 238 val = be16_to_cpu(s->data[offset * width + width - 1]); 239 } else { 240 val = le16_to_cpu(s->data[offset * width]); 241 } 242 return val; 243 } 244 245 static void dp8393x_put(dp8393xState *s, int width, int offset, 246 uint16_t val) 247 { 248 if (s->big_endian) { 249 if (width == 2) { 250 s->data[offset * 2] = 0; 251 s->data[offset * 2 + 1] = cpu_to_be16(val); 252 } else { 253 s->data[offset] = cpu_to_be16(val); 254 } 255 } else { 256 if (width == 2) { 257 s->data[offset * 2] = cpu_to_le16(val); 258 s->data[offset * 2 + 1] = 0; 259 } else { 260 s->data[offset] = cpu_to_le16(val); 261 } 262 } 263 } 264 265 static void dp8393x_update_irq(dp8393xState *s) 266 { 267 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 268 269 #ifdef DEBUG_SONIC 270 if (level != s->irq_level) { 271 s->irq_level = level; 272 if (level) { 273 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 274 } else { 275 DPRINTF("lower irq\n"); 276 } 277 } 278 #endif 279 280 qemu_set_irq(s->irq, level); 281 } 282 283 static void dp8393x_do_load_cam(dp8393xState *s) 284 { 285 int width, size; 286 uint16_t index = 0; 287 288 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 289 size = sizeof(uint16_t) * 4 * width; 290 291 while (s->regs[SONIC_CDC] & 0x1f) { 292 /* Fill current entry */ 293 address_space_read(&s->as, dp8393x_cdp(s), 294 MEMTXATTRS_UNSPECIFIED, s->data, size); 295 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 296 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 297 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 298 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 299 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 300 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 301 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 302 s->cam[index][0], s->cam[index][1], s->cam[index][2], 303 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 304 /* Move to next entry */ 305 s->regs[SONIC_CDC]--; 306 s->regs[SONIC_CDP] += size; 307 index++; 308 } 309 310 /* Read CAM enable */ 311 address_space_read(&s->as, dp8393x_cdp(s), 312 MEMTXATTRS_UNSPECIFIED, s->data, size); 313 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 314 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 315 316 /* Done */ 317 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 318 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 319 dp8393x_update_irq(s); 320 } 321 322 static void dp8393x_do_read_rra(dp8393xState *s) 323 { 324 int width, size; 325 326 /* Read memory */ 327 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 328 size = sizeof(uint16_t) * 4 * width; 329 address_space_read(&s->as, dp8393x_rrp(s), 330 MEMTXATTRS_UNSPECIFIED, s->data, size); 331 332 /* Update SONIC registers */ 333 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 334 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 335 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 336 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 337 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 338 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 339 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 340 341 /* Go to next entry */ 342 s->regs[SONIC_RRP] += size; 343 344 /* Handle wrap */ 345 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 346 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 347 } 348 349 /* Check resource exhaustion */ 350 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 351 { 352 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 353 dp8393x_update_irq(s); 354 } 355 356 /* Done */ 357 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 358 } 359 360 static void dp8393x_do_software_reset(dp8393xState *s) 361 { 362 timer_del(s->watchdog); 363 364 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 365 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 366 } 367 368 static void dp8393x_set_next_tick(dp8393xState *s) 369 { 370 uint32_t ticks; 371 int64_t delay; 372 373 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 374 timer_del(s->watchdog); 375 return; 376 } 377 378 ticks = dp8393x_wt(s); 379 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 380 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 381 timer_mod(s->watchdog, s->wt_last_update + delay); 382 } 383 384 static void dp8393x_update_wt_regs(dp8393xState *s) 385 { 386 int64_t elapsed; 387 uint32_t val; 388 389 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 390 timer_del(s->watchdog); 391 return; 392 } 393 394 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 395 val = dp8393x_wt(s); 396 val -= elapsed / 5000000; 397 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 398 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 399 dp8393x_set_next_tick(s); 400 401 } 402 403 static void dp8393x_do_start_timer(dp8393xState *s) 404 { 405 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 406 dp8393x_set_next_tick(s); 407 } 408 409 static void dp8393x_do_stop_timer(dp8393xState *s) 410 { 411 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 412 dp8393x_update_wt_regs(s); 413 } 414 415 static int dp8393x_can_receive(NetClientState *nc); 416 417 static void dp8393x_do_receiver_enable(dp8393xState *s) 418 { 419 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 420 if (dp8393x_can_receive(s->nic->ncs)) { 421 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 422 } 423 } 424 425 static void dp8393x_do_receiver_disable(dp8393xState *s) 426 { 427 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 428 } 429 430 static void dp8393x_do_transmit_packets(dp8393xState *s) 431 { 432 NetClientState *nc = qemu_get_queue(s->nic); 433 int width, size; 434 int tx_len, len; 435 uint16_t i; 436 437 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 438 439 while (1) { 440 /* Read memory */ 441 size = sizeof(uint16_t) * 6 * width; 442 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 443 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 444 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 445 MEMTXATTRS_UNSPECIFIED, s->data, size); 446 tx_len = 0; 447 448 /* Update registers */ 449 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 450 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 451 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 452 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 453 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 454 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 455 456 /* Handle programmable interrupt */ 457 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 458 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 459 } else { 460 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 461 } 462 463 for (i = 0; i < s->regs[SONIC_TFC]; ) { 464 /* Append fragment */ 465 len = s->regs[SONIC_TFS]; 466 if (tx_len + len > sizeof(s->tx_buffer)) { 467 len = sizeof(s->tx_buffer) - tx_len; 468 } 469 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, 470 &s->tx_buffer[tx_len], len); 471 tx_len += len; 472 473 i++; 474 if (i != s->regs[SONIC_TFC]) { 475 /* Read next fragment details */ 476 size = sizeof(uint16_t) * 3 * width; 477 address_space_read(&s->as, 478 dp8393x_ttda(s) 479 + sizeof(uint16_t) * width * (4 + 3 * i), 480 MEMTXATTRS_UNSPECIFIED, s->data, 481 size); 482 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 483 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 484 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 485 } 486 } 487 488 /* Handle Ethernet checksum */ 489 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 490 /* Don't append FCS there, to look like slirp packets 491 * which don't have one */ 492 } else { 493 /* Remove existing FCS */ 494 tx_len -= 4; 495 } 496 497 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 498 /* Loopback */ 499 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 500 if (nc->info->can_receive(nc)) { 501 s->loopback_packet = 1; 502 nc->info->receive(nc, s->tx_buffer, tx_len); 503 } 504 } else { 505 /* Transmit packet */ 506 qemu_send_packet(nc, s->tx_buffer, tx_len); 507 } 508 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 509 510 /* Write status */ 511 dp8393x_put(s, width, 0, 512 s->regs[SONIC_TCR] & 0x0fff); /* status */ 513 size = sizeof(uint16_t) * width; 514 address_space_write(&s->as, dp8393x_ttda(s), 515 MEMTXATTRS_UNSPECIFIED, s->data, size); 516 517 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 518 /* Read footer of packet */ 519 size = sizeof(uint16_t) * width; 520 address_space_read(&s->as, 521 dp8393x_ttda(s) 522 + sizeof(uint16_t) * width 523 * (4 + 3 * s->regs[SONIC_TFC]), 524 MEMTXATTRS_UNSPECIFIED, s->data, 525 size); 526 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; 527 if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) { 528 /* EOL detected */ 529 break; 530 } 531 } 532 } 533 534 /* Done */ 535 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 536 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 537 dp8393x_update_irq(s); 538 } 539 540 static void dp8393x_do_halt_transmission(dp8393xState *s) 541 { 542 /* Nothing to do */ 543 } 544 545 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 546 { 547 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 548 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 549 return; 550 } 551 552 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 553 554 if (command & SONIC_CR_HTX) 555 dp8393x_do_halt_transmission(s); 556 if (command & SONIC_CR_TXP) 557 dp8393x_do_transmit_packets(s); 558 if (command & SONIC_CR_RXDIS) 559 dp8393x_do_receiver_disable(s); 560 if (command & SONIC_CR_RXEN) 561 dp8393x_do_receiver_enable(s); 562 if (command & SONIC_CR_STP) 563 dp8393x_do_stop_timer(s); 564 if (command & SONIC_CR_ST) 565 dp8393x_do_start_timer(s); 566 if (command & SONIC_CR_RST) 567 dp8393x_do_software_reset(s); 568 if (command & SONIC_CR_RRRA) 569 dp8393x_do_read_rra(s); 570 if (command & SONIC_CR_LCAM) 571 dp8393x_do_load_cam(s); 572 } 573 574 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 575 { 576 dp8393xState *s = opaque; 577 int reg = addr >> s->it_shift; 578 uint16_t val = 0; 579 580 switch (reg) { 581 /* Update data before reading it */ 582 case SONIC_WT0: 583 case SONIC_WT1: 584 dp8393x_update_wt_regs(s); 585 val = s->regs[reg]; 586 break; 587 /* Accept read to some registers only when in reset mode */ 588 case SONIC_CAP2: 589 case SONIC_CAP1: 590 case SONIC_CAP0: 591 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 592 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 593 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 594 } 595 break; 596 /* All other registers have no special contrainst */ 597 default: 598 val = s->regs[reg]; 599 } 600 601 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 602 603 return s->big_endian ? val << 16 : val; 604 } 605 606 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 607 unsigned int size) 608 { 609 dp8393xState *s = opaque; 610 int reg = addr >> s->it_shift; 611 uint32_t val = s->big_endian ? data >> 16 : data; 612 613 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); 614 615 switch (reg) { 616 /* Command register */ 617 case SONIC_CR: 618 dp8393x_do_command(s, val); 619 break; 620 /* Prevent write to read-only registers */ 621 case SONIC_CAP2: 622 case SONIC_CAP1: 623 case SONIC_CAP0: 624 case SONIC_SR: 625 case SONIC_MDT: 626 DPRINTF("writing to reg %d invalid\n", reg); 627 break; 628 /* Accept write to some registers only when in reset mode */ 629 case SONIC_DCR: 630 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 631 s->regs[reg] = val & 0xbfff; 632 } else { 633 DPRINTF("writing to DCR invalid\n"); 634 } 635 break; 636 case SONIC_DCR2: 637 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 638 s->regs[reg] = val & 0xf017; 639 } else { 640 DPRINTF("writing to DCR2 invalid\n"); 641 } 642 break; 643 /* 12 lower bytes are Read Only */ 644 case SONIC_TCR: 645 s->regs[reg] = val & 0xf000; 646 break; 647 /* 9 lower bytes are Read Only */ 648 case SONIC_RCR: 649 s->regs[reg] = val & 0xffe0; 650 break; 651 /* Ignore most significant bit */ 652 case SONIC_IMR: 653 s->regs[reg] = val & 0x7fff; 654 dp8393x_update_irq(s); 655 break; 656 /* Clear bits by writing 1 to them */ 657 case SONIC_ISR: 658 val &= s->regs[reg]; 659 s->regs[reg] &= ~val; 660 if (val & SONIC_ISR_RBE) { 661 dp8393x_do_read_rra(s); 662 } 663 dp8393x_update_irq(s); 664 if (dp8393x_can_receive(s->nic->ncs)) { 665 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 666 } 667 break; 668 /* Ignore least significant bit */ 669 case SONIC_RSA: 670 case SONIC_REA: 671 case SONIC_RRP: 672 case SONIC_RWP: 673 s->regs[reg] = val & 0xfffe; 674 break; 675 /* Invert written value for some registers */ 676 case SONIC_CRCT: 677 case SONIC_FAET: 678 case SONIC_MPT: 679 s->regs[reg] = val ^ 0xffff; 680 break; 681 /* All other registers have no special contrainst */ 682 default: 683 s->regs[reg] = val; 684 } 685 686 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 687 dp8393x_set_next_tick(s); 688 } 689 } 690 691 static const MemoryRegionOps dp8393x_ops = { 692 .read = dp8393x_read, 693 .write = dp8393x_write, 694 .impl.min_access_size = 4, 695 .impl.max_access_size = 4, 696 .endianness = DEVICE_NATIVE_ENDIAN, 697 }; 698 699 static void dp8393x_watchdog(void *opaque) 700 { 701 dp8393xState *s = opaque; 702 703 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 704 return; 705 } 706 707 s->regs[SONIC_WT1] = 0xffff; 708 s->regs[SONIC_WT0] = 0xffff; 709 dp8393x_set_next_tick(s); 710 711 /* Signal underflow */ 712 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 713 dp8393x_update_irq(s); 714 } 715 716 static int dp8393x_can_receive(NetClientState *nc) 717 { 718 dp8393xState *s = qemu_get_nic_opaque(nc); 719 720 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 721 return 0; 722 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 723 return 0; 724 return 1; 725 } 726 727 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 728 int size) 729 { 730 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 731 int i; 732 733 /* Check promiscuous mode */ 734 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 735 return 0; 736 } 737 738 /* Check multicast packets */ 739 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 740 return SONIC_RCR_MC; 741 } 742 743 /* Check broadcast */ 744 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 745 return SONIC_RCR_BC; 746 } 747 748 /* Check CAM */ 749 for (i = 0; i < 16; i++) { 750 if (s->regs[SONIC_CE] & (1 << i)) { 751 /* Entry enabled */ 752 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 753 return 0; 754 } 755 } 756 } 757 758 return -1; 759 } 760 761 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 762 size_t pkt_size) 763 { 764 dp8393xState *s = qemu_get_nic_opaque(nc); 765 int packet_type; 766 uint32_t available, address; 767 int width, rx_len = pkt_size; 768 uint32_t checksum; 769 int size; 770 771 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 772 773 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 774 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 775 776 packet_type = dp8393x_receive_filter(s, buf, pkt_size); 777 if (packet_type < 0) { 778 DPRINTF("packet not for netcard\n"); 779 return -1; 780 } 781 782 /* Check for EOL */ 783 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 784 /* Are we still in resource exhaustion? */ 785 size = sizeof(uint16_t) * 1 * width; 786 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 787 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, 788 s->data, size); 789 if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) { 790 /* Still EOL ; stop reception */ 791 return -1; 792 } else { 793 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 794 } 795 } 796 797 /* Save current position */ 798 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 799 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 800 801 /* Calculate the ethernet checksum */ 802 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 803 804 /* Put packet into RBA */ 805 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); 806 address = dp8393x_crba(s); 807 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 808 buf, rx_len); 809 address += rx_len; 810 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 811 &checksum, 4); 812 rx_len += 4; 813 s->regs[SONIC_CRBA1] = address >> 16; 814 s->regs[SONIC_CRBA0] = address & 0xffff; 815 available = dp8393x_rbwc(s); 816 available -= rx_len / 2; 817 s->regs[SONIC_RBWC1] = available >> 16; 818 s->regs[SONIC_RBWC0] = available & 0xffff; 819 820 /* Update status */ 821 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 822 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 823 } 824 s->regs[SONIC_RCR] |= packet_type; 825 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 826 if (s->loopback_packet) { 827 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 828 s->loopback_packet = 0; 829 } 830 831 /* Write status to memory */ 832 DPRINTF("Write status at %08x\n", dp8393x_crda(s)); 833 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 834 dp8393x_put(s, width, 1, rx_len); /* byte count */ 835 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 836 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 837 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 838 size = sizeof(uint16_t) * 5 * width; 839 address_space_write(&s->as, dp8393x_crda(s), 840 MEMTXATTRS_UNSPECIFIED, 841 s->data, size); 842 843 /* Move to next descriptor */ 844 size = sizeof(uint16_t) * width; 845 address_space_read(&s->as, 846 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 847 MEMTXATTRS_UNSPECIFIED, s->data, size); 848 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 849 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 850 /* EOL detected */ 851 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 852 } else { 853 /* Clear in_use */ 854 size = sizeof(uint16_t) * width; 855 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 856 dp8393x_put(s, width, 0, 0); 857 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 858 s->data, size); 859 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 860 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 861 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 862 863 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 864 /* Read next RRA */ 865 dp8393x_do_read_rra(s); 866 } 867 } 868 869 /* Done */ 870 dp8393x_update_irq(s); 871 872 return pkt_size; 873 } 874 875 static void dp8393x_reset(DeviceState *dev) 876 { 877 dp8393xState *s = DP8393X(dev); 878 timer_del(s->watchdog); 879 880 memset(s->regs, 0, sizeof(s->regs)); 881 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 882 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 883 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 884 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 885 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 886 s->regs[SONIC_IMR] = 0; 887 s->regs[SONIC_ISR] = 0; 888 s->regs[SONIC_DCR2] = 0; 889 s->regs[SONIC_EOBC] = 0x02F8; 890 s->regs[SONIC_RSC] = 0; 891 s->regs[SONIC_CE] = 0; 892 s->regs[SONIC_RSC] = 0; 893 894 /* Network cable is connected */ 895 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 896 897 dp8393x_update_irq(s); 898 } 899 900 static NetClientInfo net_dp83932_info = { 901 .type = NET_CLIENT_DRIVER_NIC, 902 .size = sizeof(NICState), 903 .can_receive = dp8393x_can_receive, 904 .receive = dp8393x_receive, 905 }; 906 907 static void dp8393x_instance_init(Object *obj) 908 { 909 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 910 dp8393xState *s = DP8393X(obj); 911 912 sysbus_init_mmio(sbd, &s->mmio); 913 sysbus_init_mmio(sbd, &s->prom); 914 sysbus_init_irq(sbd, &s->irq); 915 } 916 917 static void dp8393x_realize(DeviceState *dev, Error **errp) 918 { 919 dp8393xState *s = DP8393X(dev); 920 int i, checksum; 921 uint8_t *prom; 922 Error *local_err = NULL; 923 924 address_space_init(&s->as, s->dma_mr, "dp8393x"); 925 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 926 "dp8393x-regs", 0x40 << s->it_shift); 927 928 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 929 object_get_typename(OBJECT(dev)), dev->id, s); 930 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 931 932 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 933 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 934 935 memory_region_init_ram(&s->prom, OBJECT(dev), 936 "dp8393x-prom", SONIC_PROM_SIZE, &local_err); 937 if (local_err) { 938 error_propagate(errp, local_err); 939 return; 940 } 941 memory_region_set_readonly(&s->prom, true); 942 prom = memory_region_get_ram_ptr(&s->prom); 943 checksum = 0; 944 for (i = 0; i < 6; i++) { 945 prom[i] = s->conf.macaddr.a[i]; 946 checksum += prom[i]; 947 if (checksum > 0xff) { 948 checksum = (checksum + 1) & 0xff; 949 } 950 } 951 prom[7] = 0xff - checksum; 952 } 953 954 static const VMStateDescription vmstate_dp8393x = { 955 .name = "dp8393x", 956 .version_id = 0, 957 .minimum_version_id = 0, 958 .fields = (VMStateField []) { 959 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 960 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 961 VMSTATE_END_OF_LIST() 962 } 963 }; 964 965 static Property dp8393x_properties[] = { 966 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 967 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 968 TYPE_MEMORY_REGION, MemoryRegion *), 969 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 970 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 971 DEFINE_PROP_END_OF_LIST(), 972 }; 973 974 static void dp8393x_class_init(ObjectClass *klass, void *data) 975 { 976 DeviceClass *dc = DEVICE_CLASS(klass); 977 978 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 979 dc->realize = dp8393x_realize; 980 dc->reset = dp8393x_reset; 981 dc->vmsd = &vmstate_dp8393x; 982 device_class_set_props(dc, dp8393x_properties); 983 } 984 985 static const TypeInfo dp8393x_info = { 986 .name = TYPE_DP8393X, 987 .parent = TYPE_SYS_BUS_DEVICE, 988 .instance_size = sizeof(dp8393xState), 989 .instance_init = dp8393x_instance_init, 990 .class_init = dp8393x_class_init, 991 }; 992 993 static void dp8393x_register_types(void) 994 { 995 type_register_static(&dp8393x_info); 996 } 997 998 type_init(dp8393x_register_types) 999