1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 31 //#define DEBUG_SONIC 32 33 #define SONIC_PROM_SIZE 0x1000 34 35 #ifdef DEBUG_SONIC 36 #define DPRINTF(fmt, ...) \ 37 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) 38 static const char* reg_names[] = { 39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 47 #else 48 #define DPRINTF(fmt, ...) do {} while (0) 49 #endif 50 51 #define SONIC_ERROR(fmt, ...) \ 52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) 53 54 #define SONIC_CR 0x00 55 #define SONIC_DCR 0x01 56 #define SONIC_RCR 0x02 57 #define SONIC_TCR 0x03 58 #define SONIC_IMR 0x04 59 #define SONIC_ISR 0x05 60 #define SONIC_UTDA 0x06 61 #define SONIC_CTDA 0x07 62 #define SONIC_TPS 0x08 63 #define SONIC_TFC 0x09 64 #define SONIC_TSA0 0x0a 65 #define SONIC_TSA1 0x0b 66 #define SONIC_TFS 0x0c 67 #define SONIC_URDA 0x0d 68 #define SONIC_CRDA 0x0e 69 #define SONIC_CRBA0 0x0f 70 #define SONIC_CRBA1 0x10 71 #define SONIC_RBWC0 0x11 72 #define SONIC_RBWC1 0x12 73 #define SONIC_EOBC 0x13 74 #define SONIC_URRA 0x14 75 #define SONIC_RSA 0x15 76 #define SONIC_REA 0x16 77 #define SONIC_RRP 0x17 78 #define SONIC_RWP 0x18 79 #define SONIC_TRBA0 0x19 80 #define SONIC_TRBA1 0x1a 81 #define SONIC_LLFA 0x1f 82 #define SONIC_TTDA 0x20 83 #define SONIC_CEP 0x21 84 #define SONIC_CAP2 0x22 85 #define SONIC_CAP1 0x23 86 #define SONIC_CAP0 0x24 87 #define SONIC_CE 0x25 88 #define SONIC_CDP 0x26 89 #define SONIC_CDC 0x27 90 #define SONIC_SR 0x28 91 #define SONIC_WT0 0x29 92 #define SONIC_WT1 0x2a 93 #define SONIC_RSC 0x2b 94 #define SONIC_CRCT 0x2c 95 #define SONIC_FAET 0x2d 96 #define SONIC_MPT 0x2e 97 #define SONIC_MDT 0x2f 98 #define SONIC_DCR2 0x3f 99 100 #define SONIC_CR_HTX 0x0001 101 #define SONIC_CR_TXP 0x0002 102 #define SONIC_CR_RXDIS 0x0004 103 #define SONIC_CR_RXEN 0x0008 104 #define SONIC_CR_STP 0x0010 105 #define SONIC_CR_ST 0x0020 106 #define SONIC_CR_RST 0x0080 107 #define SONIC_CR_RRRA 0x0100 108 #define SONIC_CR_LCAM 0x0200 109 #define SONIC_CR_MASK 0x03bf 110 111 #define SONIC_DCR_DW 0x0020 112 #define SONIC_DCR_LBR 0x2000 113 #define SONIC_DCR_EXBUS 0x8000 114 115 #define SONIC_RCR_PRX 0x0001 116 #define SONIC_RCR_LBK 0x0002 117 #define SONIC_RCR_FAER 0x0004 118 #define SONIC_RCR_CRCR 0x0008 119 #define SONIC_RCR_CRS 0x0020 120 #define SONIC_RCR_LPKT 0x0040 121 #define SONIC_RCR_BC 0x0080 122 #define SONIC_RCR_MC 0x0100 123 #define SONIC_RCR_LB0 0x0200 124 #define SONIC_RCR_LB1 0x0400 125 #define SONIC_RCR_AMC 0x0800 126 #define SONIC_RCR_PRO 0x1000 127 #define SONIC_RCR_BRD 0x2000 128 #define SONIC_RCR_RNT 0x4000 129 130 #define SONIC_TCR_PTX 0x0001 131 #define SONIC_TCR_BCM 0x0002 132 #define SONIC_TCR_FU 0x0004 133 #define SONIC_TCR_EXC 0x0040 134 #define SONIC_TCR_CRSL 0x0080 135 #define SONIC_TCR_NCRS 0x0100 136 #define SONIC_TCR_EXD 0x0400 137 #define SONIC_TCR_CRCI 0x2000 138 #define SONIC_TCR_PINT 0x8000 139 140 #define SONIC_ISR_RBE 0x0020 141 #define SONIC_ISR_RDE 0x0040 142 #define SONIC_ISR_TC 0x0080 143 #define SONIC_ISR_TXDN 0x0200 144 #define SONIC_ISR_PKTRX 0x0400 145 #define SONIC_ISR_PINT 0x0800 146 #define SONIC_ISR_LCD 0x1000 147 148 #define SONIC_DESC_EOL 0x0001 149 #define SONIC_DESC_ADDR 0xFFFE 150 151 #define TYPE_DP8393X "dp8393x" 152 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) 153 154 typedef struct dp8393xState { 155 SysBusDevice parent_obj; 156 157 /* Hardware */ 158 uint8_t it_shift; 159 bool big_endian; 160 qemu_irq irq; 161 #ifdef DEBUG_SONIC 162 int irq_level; 163 #endif 164 QEMUTimer *watchdog; 165 int64_t wt_last_update; 166 NICConf conf; 167 NICState *nic; 168 MemoryRegion mmio; 169 MemoryRegion prom; 170 171 /* Registers */ 172 uint8_t cam[16][6]; 173 uint16_t regs[0x40]; 174 175 /* Temporaries */ 176 uint8_t tx_buffer[0x10000]; 177 uint16_t data[12]; 178 int loopback_packet; 179 180 /* Memory access */ 181 MemoryRegion *dma_mr; 182 AddressSpace as; 183 } dp8393xState; 184 185 /* Accessor functions for values which are formed by 186 * concatenating two 16 bit device registers. By putting these 187 * in their own functions with a uint32_t return type we avoid the 188 * pitfall of implicit sign extension where ((x << 16) | y) is a 189 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 190 */ 191 static uint32_t dp8393x_cdp(dp8393xState *s) 192 { 193 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 194 } 195 196 static uint32_t dp8393x_crba(dp8393xState *s) 197 { 198 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 199 } 200 201 static uint32_t dp8393x_crda(dp8393xState *s) 202 { 203 return (s->regs[SONIC_URDA] << 16) | 204 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); 205 } 206 207 static uint32_t dp8393x_rbwc(dp8393xState *s) 208 { 209 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 210 } 211 212 static uint32_t dp8393x_rrp(dp8393xState *s) 213 { 214 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 215 } 216 217 static uint32_t dp8393x_tsa(dp8393xState *s) 218 { 219 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 220 } 221 222 static uint32_t dp8393x_ttda(dp8393xState *s) 223 { 224 return (s->regs[SONIC_UTDA] << 16) | 225 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR); 226 } 227 228 static uint32_t dp8393x_wt(dp8393xState *s) 229 { 230 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 231 } 232 233 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 234 { 235 uint16_t val; 236 237 if (s->big_endian) { 238 val = be16_to_cpu(s->data[offset * width + width - 1]); 239 } else { 240 val = le16_to_cpu(s->data[offset * width]); 241 } 242 return val; 243 } 244 245 static void dp8393x_put(dp8393xState *s, int width, int offset, 246 uint16_t val) 247 { 248 if (s->big_endian) { 249 s->data[offset * width + width - 1] = cpu_to_be16(val); 250 } else { 251 s->data[offset * width] = cpu_to_le16(val); 252 } 253 } 254 255 static void dp8393x_update_irq(dp8393xState *s) 256 { 257 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 258 259 #ifdef DEBUG_SONIC 260 if (level != s->irq_level) { 261 s->irq_level = level; 262 if (level) { 263 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); 264 } else { 265 DPRINTF("lower irq\n"); 266 } 267 } 268 #endif 269 270 qemu_set_irq(s->irq, level); 271 } 272 273 static void dp8393x_do_load_cam(dp8393xState *s) 274 { 275 int width, size; 276 uint16_t index = 0; 277 278 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 279 size = sizeof(uint16_t) * 4 * width; 280 281 while (s->regs[SONIC_CDC] & 0x1f) { 282 /* Fill current entry */ 283 address_space_read(&s->as, dp8393x_cdp(s), 284 MEMTXATTRS_UNSPECIFIED, s->data, size); 285 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 286 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 287 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 288 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 289 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 290 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 291 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, 292 s->cam[index][0], s->cam[index][1], s->cam[index][2], 293 s->cam[index][3], s->cam[index][4], s->cam[index][5]); 294 /* Move to next entry */ 295 s->regs[SONIC_CDC]--; 296 s->regs[SONIC_CDP] += size; 297 index++; 298 } 299 300 /* Read CAM enable */ 301 address_space_read(&s->as, dp8393x_cdp(s), 302 MEMTXATTRS_UNSPECIFIED, s->data, size); 303 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 304 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); 305 306 /* Done */ 307 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 308 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 309 dp8393x_update_irq(s); 310 } 311 312 static void dp8393x_do_read_rra(dp8393xState *s) 313 { 314 int width, size; 315 316 /* Read memory */ 317 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 318 size = sizeof(uint16_t) * 4 * width; 319 address_space_read(&s->as, dp8393x_rrp(s), 320 MEMTXATTRS_UNSPECIFIED, s->data, size); 321 322 /* Update SONIC registers */ 323 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 324 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 325 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 326 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 327 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", 328 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 329 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 330 331 /* Go to next entry */ 332 s->regs[SONIC_RRP] += size; 333 334 /* Handle wrap */ 335 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 336 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 337 } 338 339 /* Check resource exhaustion */ 340 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) 341 { 342 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 343 dp8393x_update_irq(s); 344 } 345 346 /* Done */ 347 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 348 } 349 350 static void dp8393x_do_software_reset(dp8393xState *s) 351 { 352 timer_del(s->watchdog); 353 354 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX); 355 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 356 } 357 358 static void dp8393x_set_next_tick(dp8393xState *s) 359 { 360 uint32_t ticks; 361 int64_t delay; 362 363 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 364 timer_del(s->watchdog); 365 return; 366 } 367 368 ticks = dp8393x_wt(s); 369 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 370 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 371 timer_mod(s->watchdog, s->wt_last_update + delay); 372 } 373 374 static void dp8393x_update_wt_regs(dp8393xState *s) 375 { 376 int64_t elapsed; 377 uint32_t val; 378 379 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 380 timer_del(s->watchdog); 381 return; 382 } 383 384 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 385 val = dp8393x_wt(s); 386 val -= elapsed / 5000000; 387 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 388 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 389 dp8393x_set_next_tick(s); 390 391 } 392 393 static void dp8393x_do_start_timer(dp8393xState *s) 394 { 395 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 396 dp8393x_set_next_tick(s); 397 } 398 399 static void dp8393x_do_stop_timer(dp8393xState *s) 400 { 401 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 402 dp8393x_update_wt_regs(s); 403 } 404 405 static int dp8393x_can_receive(NetClientState *nc); 406 407 static void dp8393x_do_receiver_enable(dp8393xState *s) 408 { 409 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 410 if (dp8393x_can_receive(s->nic->ncs)) { 411 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 412 } 413 } 414 415 static void dp8393x_do_receiver_disable(dp8393xState *s) 416 { 417 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 418 } 419 420 static void dp8393x_do_transmit_packets(dp8393xState *s) 421 { 422 NetClientState *nc = qemu_get_queue(s->nic); 423 int width, size; 424 int tx_len, len; 425 uint16_t i; 426 427 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 428 429 while (1) { 430 /* Read memory */ 431 size = sizeof(uint16_t) * 6 * width; 432 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 433 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); 434 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 435 MEMTXATTRS_UNSPECIFIED, s->data, size); 436 tx_len = 0; 437 438 /* Update registers */ 439 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 440 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 441 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 442 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 443 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 444 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 445 446 /* Handle programmable interrupt */ 447 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 448 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 449 } else { 450 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 451 } 452 453 for (i = 0; i < s->regs[SONIC_TFC]; ) { 454 /* Append fragment */ 455 len = s->regs[SONIC_TFS]; 456 if (tx_len + len > sizeof(s->tx_buffer)) { 457 len = sizeof(s->tx_buffer) - tx_len; 458 } 459 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, 460 &s->tx_buffer[tx_len], len); 461 tx_len += len; 462 463 i++; 464 if (i != s->regs[SONIC_TFC]) { 465 /* Read next fragment details */ 466 size = sizeof(uint16_t) * 3 * width; 467 address_space_read(&s->as, 468 dp8393x_ttda(s) 469 + sizeof(uint16_t) * width * (4 + 3 * i), 470 MEMTXATTRS_UNSPECIFIED, s->data, 471 size); 472 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 473 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 474 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 475 } 476 } 477 478 /* Handle Ethernet checksum */ 479 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 480 /* Don't append FCS there, to look like slirp packets 481 * which don't have one */ 482 } else { 483 /* Remove existing FCS */ 484 tx_len -= 4; 485 } 486 487 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 488 /* Loopback */ 489 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 490 if (nc->info->can_receive(nc)) { 491 s->loopback_packet = 1; 492 nc->info->receive(nc, s->tx_buffer, tx_len); 493 } 494 } else { 495 /* Transmit packet */ 496 qemu_send_packet(nc, s->tx_buffer, tx_len); 497 } 498 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 499 500 /* Write status */ 501 dp8393x_put(s, width, 0, 502 s->regs[SONIC_TCR] & 0x0fff); /* status */ 503 size = sizeof(uint16_t) * width; 504 address_space_write(&s->as, dp8393x_ttda(s), 505 MEMTXATTRS_UNSPECIFIED, s->data, size); 506 507 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 508 /* Read footer of packet */ 509 size = sizeof(uint16_t) * width; 510 address_space_read(&s->as, 511 dp8393x_ttda(s) 512 + sizeof(uint16_t) * width 513 * (4 + 3 * s->regs[SONIC_TFC]), 514 MEMTXATTRS_UNSPECIFIED, s->data, 515 size); 516 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; 517 if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) { 518 /* EOL detected */ 519 break; 520 } 521 } 522 } 523 524 /* Done */ 525 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 526 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 527 dp8393x_update_irq(s); 528 } 529 530 static void dp8393x_do_halt_transmission(dp8393xState *s) 531 { 532 /* Nothing to do */ 533 } 534 535 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 536 { 537 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 538 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 539 return; 540 } 541 542 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 543 544 if (command & SONIC_CR_HTX) 545 dp8393x_do_halt_transmission(s); 546 if (command & SONIC_CR_TXP) 547 dp8393x_do_transmit_packets(s); 548 if (command & SONIC_CR_RXDIS) 549 dp8393x_do_receiver_disable(s); 550 if (command & SONIC_CR_RXEN) 551 dp8393x_do_receiver_enable(s); 552 if (command & SONIC_CR_STP) 553 dp8393x_do_stop_timer(s); 554 if (command & SONIC_CR_ST) 555 dp8393x_do_start_timer(s); 556 if (command & SONIC_CR_RST) 557 dp8393x_do_software_reset(s); 558 if (command & SONIC_CR_RRRA) 559 dp8393x_do_read_rra(s); 560 if (command & SONIC_CR_LCAM) 561 dp8393x_do_load_cam(s); 562 } 563 564 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 565 { 566 dp8393xState *s = opaque; 567 int reg = addr >> s->it_shift; 568 uint16_t val = 0; 569 570 switch (reg) { 571 /* Update data before reading it */ 572 case SONIC_WT0: 573 case SONIC_WT1: 574 dp8393x_update_wt_regs(s); 575 val = s->regs[reg]; 576 break; 577 /* Accept read to some registers only when in reset mode */ 578 case SONIC_CAP2: 579 case SONIC_CAP1: 580 case SONIC_CAP0: 581 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 582 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8; 583 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)]; 584 } 585 break; 586 /* All other registers have no special contrainst */ 587 default: 588 val = s->regs[reg]; 589 } 590 591 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); 592 593 return val; 594 } 595 596 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 597 unsigned int size) 598 { 599 dp8393xState *s = opaque; 600 int reg = addr >> s->it_shift; 601 602 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]); 603 604 switch (reg) { 605 /* Command register */ 606 case SONIC_CR: 607 dp8393x_do_command(s, data); 608 break; 609 /* Prevent write to read-only registers */ 610 case SONIC_CAP2: 611 case SONIC_CAP1: 612 case SONIC_CAP0: 613 case SONIC_SR: 614 case SONIC_MDT: 615 DPRINTF("writing to reg %d invalid\n", reg); 616 break; 617 /* Accept write to some registers only when in reset mode */ 618 case SONIC_DCR: 619 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 620 s->regs[reg] = data & 0xbfff; 621 } else { 622 DPRINTF("writing to DCR invalid\n"); 623 } 624 break; 625 case SONIC_DCR2: 626 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 627 s->regs[reg] = data & 0xf017; 628 } else { 629 DPRINTF("writing to DCR2 invalid\n"); 630 } 631 break; 632 /* 12 lower bytes are Read Only */ 633 case SONIC_TCR: 634 s->regs[reg] = data & 0xf000; 635 break; 636 /* 9 lower bytes are Read Only */ 637 case SONIC_RCR: 638 s->regs[reg] = data & 0xffe0; 639 break; 640 /* Ignore most significant bit */ 641 case SONIC_IMR: 642 s->regs[reg] = data & 0x7fff; 643 dp8393x_update_irq(s); 644 break; 645 /* Clear bits by writing 1 to them */ 646 case SONIC_ISR: 647 data &= s->regs[reg]; 648 s->regs[reg] &= ~data; 649 if (data & SONIC_ISR_RBE) { 650 dp8393x_do_read_rra(s); 651 } 652 dp8393x_update_irq(s); 653 if (dp8393x_can_receive(s->nic->ncs)) { 654 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 655 } 656 break; 657 /* Ignore least significant bit */ 658 case SONIC_RSA: 659 case SONIC_REA: 660 case SONIC_RRP: 661 case SONIC_RWP: 662 s->regs[reg] = data & 0xfffe; 663 break; 664 /* Invert written value for some registers */ 665 case SONIC_CRCT: 666 case SONIC_FAET: 667 case SONIC_MPT: 668 s->regs[reg] = data ^ 0xffff; 669 break; 670 /* All other registers have no special contrainst */ 671 default: 672 s->regs[reg] = data; 673 } 674 675 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 676 dp8393x_set_next_tick(s); 677 } 678 } 679 680 static const MemoryRegionOps dp8393x_ops = { 681 .read = dp8393x_read, 682 .write = dp8393x_write, 683 .impl.min_access_size = 2, 684 .impl.max_access_size = 2, 685 .endianness = DEVICE_NATIVE_ENDIAN, 686 }; 687 688 static void dp8393x_watchdog(void *opaque) 689 { 690 dp8393xState *s = opaque; 691 692 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 693 return; 694 } 695 696 s->regs[SONIC_WT1] = 0xffff; 697 s->regs[SONIC_WT0] = 0xffff; 698 dp8393x_set_next_tick(s); 699 700 /* Signal underflow */ 701 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 702 dp8393x_update_irq(s); 703 } 704 705 static int dp8393x_can_receive(NetClientState *nc) 706 { 707 dp8393xState *s = qemu_get_nic_opaque(nc); 708 709 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN)) 710 return 0; 711 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE) 712 return 0; 713 return 1; 714 } 715 716 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 717 int size) 718 { 719 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 720 int i; 721 722 /* Check promiscuous mode */ 723 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 724 return 0; 725 } 726 727 /* Check multicast packets */ 728 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 729 return SONIC_RCR_MC; 730 } 731 732 /* Check broadcast */ 733 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) { 734 return SONIC_RCR_BC; 735 } 736 737 /* Check CAM */ 738 for (i = 0; i < 16; i++) { 739 if (s->regs[SONIC_CE] & (1 << i)) { 740 /* Entry enabled */ 741 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 742 return 0; 743 } 744 } 745 } 746 747 return -1; 748 } 749 750 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 751 size_t size) 752 { 753 dp8393xState *s = qemu_get_nic_opaque(nc); 754 int packet_type; 755 uint32_t available, address; 756 int width, rx_len = size; 757 uint32_t checksum; 758 759 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 760 761 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 762 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 763 764 packet_type = dp8393x_receive_filter(s, buf, size); 765 if (packet_type < 0) { 766 DPRINTF("packet not for netcard\n"); 767 return -1; 768 } 769 770 /* XXX: Check byte ordering */ 771 772 /* Check for EOL */ 773 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 774 /* Are we still in resource exhaustion? */ 775 size = sizeof(uint16_t) * 1 * width; 776 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 777 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, 778 s->data, size); 779 if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) { 780 /* Still EOL ; stop reception */ 781 return -1; 782 } else { 783 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 784 } 785 } 786 787 /* Save current position */ 788 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 789 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 790 791 /* Calculate the ethernet checksum */ 792 checksum = cpu_to_le32(crc32(0, buf, rx_len)); 793 794 /* Put packet into RBA */ 795 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); 796 address = dp8393x_crba(s); 797 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 798 buf, rx_len); 799 address += rx_len; 800 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 801 &checksum, 4); 802 rx_len += 4; 803 s->regs[SONIC_CRBA1] = address >> 16; 804 s->regs[SONIC_CRBA0] = address & 0xffff; 805 available = dp8393x_rbwc(s); 806 available -= rx_len / 2; 807 s->regs[SONIC_RBWC1] = available >> 16; 808 s->regs[SONIC_RBWC0] = available & 0xffff; 809 810 /* Update status */ 811 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 812 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 813 } 814 s->regs[SONIC_RCR] |= packet_type; 815 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 816 if (s->loopback_packet) { 817 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 818 s->loopback_packet = 0; 819 } 820 821 /* Write status to memory */ 822 DPRINTF("Write status at %08x\n", dp8393x_crda(s)); 823 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 824 dp8393x_put(s, width, 1, rx_len); /* byte count */ 825 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 826 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 827 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 828 size = sizeof(uint16_t) * 5 * width; 829 address_space_write(&s->as, dp8393x_crda(s), 830 MEMTXATTRS_UNSPECIFIED, 831 s->data, size); 832 833 /* Move to next descriptor */ 834 size = sizeof(uint16_t) * width; 835 address_space_read(&s->as, 836 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 837 MEMTXATTRS_UNSPECIFIED, s->data, size); 838 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 839 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 840 /* EOL detected */ 841 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 842 } else { 843 /* Clear in_use, but it is always 16bit wide */ 844 int offset = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 845 if (s->big_endian && width == 2) { 846 /* we need to adjust the offset of the 16bit field */ 847 offset += sizeof(uint16_t); 848 } 849 s->data[0] = 0; 850 address_space_write(&s->as, offset, MEMTXATTRS_UNSPECIFIED, 851 s->data, sizeof(uint16_t)); 852 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 853 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 854 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); 855 856 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 857 /* Read next RRA */ 858 dp8393x_do_read_rra(s); 859 } 860 } 861 862 /* Done */ 863 dp8393x_update_irq(s); 864 865 return size; 866 } 867 868 static void dp8393x_reset(DeviceState *dev) 869 { 870 dp8393xState *s = DP8393X(dev); 871 timer_del(s->watchdog); 872 873 memset(s->regs, 0, sizeof(s->regs)); 874 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 875 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 876 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT); 877 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 878 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 879 s->regs[SONIC_IMR] = 0; 880 s->regs[SONIC_ISR] = 0; 881 s->regs[SONIC_DCR2] = 0; 882 s->regs[SONIC_EOBC] = 0x02F8; 883 s->regs[SONIC_RSC] = 0; 884 s->regs[SONIC_CE] = 0; 885 s->regs[SONIC_RSC] = 0; 886 887 /* Network cable is connected */ 888 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 889 890 dp8393x_update_irq(s); 891 } 892 893 static NetClientInfo net_dp83932_info = { 894 .type = NET_CLIENT_DRIVER_NIC, 895 .size = sizeof(NICState), 896 .can_receive = dp8393x_can_receive, 897 .receive = dp8393x_receive, 898 }; 899 900 static void dp8393x_instance_init(Object *obj) 901 { 902 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 903 dp8393xState *s = DP8393X(obj); 904 905 sysbus_init_mmio(sbd, &s->mmio); 906 sysbus_init_mmio(sbd, &s->prom); 907 sysbus_init_irq(sbd, &s->irq); 908 } 909 910 static void dp8393x_realize(DeviceState *dev, Error **errp) 911 { 912 dp8393xState *s = DP8393X(dev); 913 int i, checksum; 914 uint8_t *prom; 915 Error *local_err = NULL; 916 917 address_space_init(&s->as, s->dma_mr, "dp8393x"); 918 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 919 "dp8393x-regs", 0x40 << s->it_shift); 920 921 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 922 object_get_typename(OBJECT(dev)), dev->id, s); 923 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 924 925 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 926 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ 927 928 memory_region_init_ram(&s->prom, OBJECT(dev), 929 "dp8393x-prom", SONIC_PROM_SIZE, &local_err); 930 if (local_err) { 931 error_propagate(errp, local_err); 932 return; 933 } 934 memory_region_set_readonly(&s->prom, true); 935 prom = memory_region_get_ram_ptr(&s->prom); 936 checksum = 0; 937 for (i = 0; i < 6; i++) { 938 prom[i] = s->conf.macaddr.a[i]; 939 checksum += prom[i]; 940 if (checksum > 0xff) { 941 checksum = (checksum + 1) & 0xff; 942 } 943 } 944 prom[7] = 0xff - checksum; 945 } 946 947 static const VMStateDescription vmstate_dp8393x = { 948 .name = "dp8393x", 949 .version_id = 0, 950 .minimum_version_id = 0, 951 .fields = (VMStateField []) { 952 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 953 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), 954 VMSTATE_END_OF_LIST() 955 } 956 }; 957 958 static Property dp8393x_properties[] = { 959 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 960 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 961 TYPE_MEMORY_REGION, MemoryRegion *), 962 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 963 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 964 DEFINE_PROP_END_OF_LIST(), 965 }; 966 967 static void dp8393x_class_init(ObjectClass *klass, void *data) 968 { 969 DeviceClass *dc = DEVICE_CLASS(klass); 970 971 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 972 dc->realize = dp8393x_realize; 973 dc->reset = dp8393x_reset; 974 dc->vmsd = &vmstate_dp8393x; 975 device_class_set_props(dc, dp8393x_properties); 976 } 977 978 static const TypeInfo dp8393x_info = { 979 .name = TYPE_DP8393X, 980 .parent = TYPE_SYS_BUS_DEVICE, 981 .instance_size = sizeof(dp8393xState), 982 .instance_init = dp8393x_instance_init, 983 .class_init = dp8393x_class_init, 984 }; 985 986 static void dp8393x_register_types(void) 987 { 988 type_register_static(&dp8393x_info); 989 } 990 991 type_init(dp8393x_register_types) 992