1 /* 2 * QEMU NS SONIC DP8393x netcard 3 * 4 * Copyright (c) 2008-2009 Herve Poussineau 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "migration/vmstate.h" 25 #include "net/net.h" 26 #include "qapi/error.h" 27 #include "qemu/module.h" 28 #include "qemu/timer.h" 29 #include <zlib.h> 30 #include "qom/object.h" 31 #include "trace.h" 32 33 static const char *reg_names[] = { 34 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", 35 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", 36 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", 37 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA", 38 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC", 39 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", 40 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", 41 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; 42 43 #define SONIC_CR 0x00 44 #define SONIC_DCR 0x01 45 #define SONIC_RCR 0x02 46 #define SONIC_TCR 0x03 47 #define SONIC_IMR 0x04 48 #define SONIC_ISR 0x05 49 #define SONIC_UTDA 0x06 50 #define SONIC_CTDA 0x07 51 #define SONIC_TPS 0x08 52 #define SONIC_TFC 0x09 53 #define SONIC_TSA0 0x0a 54 #define SONIC_TSA1 0x0b 55 #define SONIC_TFS 0x0c 56 #define SONIC_URDA 0x0d 57 #define SONIC_CRDA 0x0e 58 #define SONIC_CRBA0 0x0f 59 #define SONIC_CRBA1 0x10 60 #define SONIC_RBWC0 0x11 61 #define SONIC_RBWC1 0x12 62 #define SONIC_EOBC 0x13 63 #define SONIC_URRA 0x14 64 #define SONIC_RSA 0x15 65 #define SONIC_REA 0x16 66 #define SONIC_RRP 0x17 67 #define SONIC_RWP 0x18 68 #define SONIC_TRBA0 0x19 69 #define SONIC_TRBA1 0x1a 70 #define SONIC_LLFA 0x1f 71 #define SONIC_TTDA 0x20 72 #define SONIC_CEP 0x21 73 #define SONIC_CAP2 0x22 74 #define SONIC_CAP1 0x23 75 #define SONIC_CAP0 0x24 76 #define SONIC_CE 0x25 77 #define SONIC_CDP 0x26 78 #define SONIC_CDC 0x27 79 #define SONIC_SR 0x28 80 #define SONIC_WT0 0x29 81 #define SONIC_WT1 0x2a 82 #define SONIC_RSC 0x2b 83 #define SONIC_CRCT 0x2c 84 #define SONIC_FAET 0x2d 85 #define SONIC_MPT 0x2e 86 #define SONIC_MDT 0x2f 87 #define SONIC_DCR2 0x3f 88 #define SONIC_REG_COUNT 0x40 89 90 #define SONIC_CR_HTX 0x0001 91 #define SONIC_CR_TXP 0x0002 92 #define SONIC_CR_RXDIS 0x0004 93 #define SONIC_CR_RXEN 0x0008 94 #define SONIC_CR_STP 0x0010 95 #define SONIC_CR_ST 0x0020 96 #define SONIC_CR_RST 0x0080 97 #define SONIC_CR_RRRA 0x0100 98 #define SONIC_CR_LCAM 0x0200 99 #define SONIC_CR_MASK 0x03bf 100 101 #define SONIC_DCR_DW 0x0020 102 #define SONIC_DCR_LBR 0x2000 103 #define SONIC_DCR_EXBUS 0x8000 104 105 #define SONIC_RCR_PRX 0x0001 106 #define SONIC_RCR_LBK 0x0002 107 #define SONIC_RCR_FAER 0x0004 108 #define SONIC_RCR_CRCR 0x0008 109 #define SONIC_RCR_CRS 0x0020 110 #define SONIC_RCR_LPKT 0x0040 111 #define SONIC_RCR_BC 0x0080 112 #define SONIC_RCR_MC 0x0100 113 #define SONIC_RCR_LB0 0x0200 114 #define SONIC_RCR_LB1 0x0400 115 #define SONIC_RCR_AMC 0x0800 116 #define SONIC_RCR_PRO 0x1000 117 #define SONIC_RCR_BRD 0x2000 118 #define SONIC_RCR_RNT 0x4000 119 120 #define SONIC_TCR_PTX 0x0001 121 #define SONIC_TCR_BCM 0x0002 122 #define SONIC_TCR_FU 0x0004 123 #define SONIC_TCR_EXC 0x0040 124 #define SONIC_TCR_CRSL 0x0080 125 #define SONIC_TCR_NCRS 0x0100 126 #define SONIC_TCR_EXD 0x0400 127 #define SONIC_TCR_CRCI 0x2000 128 #define SONIC_TCR_PINT 0x8000 129 130 #define SONIC_ISR_RBAE 0x0010 131 #define SONIC_ISR_RBE 0x0020 132 #define SONIC_ISR_RDE 0x0040 133 #define SONIC_ISR_TC 0x0080 134 #define SONIC_ISR_TXDN 0x0200 135 #define SONIC_ISR_PKTRX 0x0400 136 #define SONIC_ISR_PINT 0x0800 137 #define SONIC_ISR_LCD 0x1000 138 139 #define SONIC_DESC_EOL 0x0001 140 #define SONIC_DESC_ADDR 0xFFFE 141 142 #define TYPE_DP8393X "dp8393x" 143 OBJECT_DECLARE_SIMPLE_TYPE(dp8393xState, DP8393X) 144 145 struct dp8393xState { 146 SysBusDevice parent_obj; 147 148 /* Hardware */ 149 uint8_t it_shift; 150 bool big_endian; 151 bool last_rba_is_full; 152 qemu_irq irq; 153 int irq_level; 154 QEMUTimer *watchdog; 155 int64_t wt_last_update; 156 NICConf conf; 157 NICState *nic; 158 MemoryRegion mmio; 159 160 /* Registers */ 161 uint8_t cam[16][6]; 162 uint16_t regs[SONIC_REG_COUNT]; 163 164 /* Temporaries */ 165 uint8_t tx_buffer[0x10000]; 166 uint16_t data[12]; 167 int loopback_packet; 168 169 /* Memory access */ 170 MemoryRegion *dma_mr; 171 AddressSpace as; 172 }; 173 174 /* 175 * Accessor functions for values which are formed by 176 * concatenating two 16 bit device registers. By putting these 177 * in their own functions with a uint32_t return type we avoid the 178 * pitfall of implicit sign extension where ((x << 16) | y) is a 179 * signed 32 bit integer that might get sign-extended to a 64 bit integer. 180 */ 181 static uint32_t dp8393x_cdp(dp8393xState *s) 182 { 183 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP]; 184 } 185 186 static uint32_t dp8393x_crba(dp8393xState *s) 187 { 188 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0]; 189 } 190 191 static uint32_t dp8393x_crda(dp8393xState *s) 192 { 193 return (s->regs[SONIC_URDA] << 16) | 194 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); 195 } 196 197 static uint32_t dp8393x_rbwc(dp8393xState *s) 198 { 199 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0]; 200 } 201 202 static uint32_t dp8393x_rrp(dp8393xState *s) 203 { 204 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP]; 205 } 206 207 static uint32_t dp8393x_tsa(dp8393xState *s) 208 { 209 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0]; 210 } 211 212 static uint32_t dp8393x_ttda(dp8393xState *s) 213 { 214 return (s->regs[SONIC_UTDA] << 16) | 215 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR); 216 } 217 218 static uint32_t dp8393x_wt(dp8393xState *s) 219 { 220 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; 221 } 222 223 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) 224 { 225 uint16_t val; 226 227 if (s->big_endian) { 228 val = be16_to_cpu(s->data[offset * width + width - 1]); 229 } else { 230 val = le16_to_cpu(s->data[offset * width]); 231 } 232 return val; 233 } 234 235 static void dp8393x_put(dp8393xState *s, int width, int offset, 236 uint16_t val) 237 { 238 if (s->big_endian) { 239 if (width == 2) { 240 s->data[offset * 2] = 0; 241 s->data[offset * 2 + 1] = cpu_to_be16(val); 242 } else { 243 s->data[offset] = cpu_to_be16(val); 244 } 245 } else { 246 if (width == 2) { 247 s->data[offset * 2] = cpu_to_le16(val); 248 s->data[offset * 2 + 1] = 0; 249 } else { 250 s->data[offset] = cpu_to_le16(val); 251 } 252 } 253 } 254 255 static void dp8393x_update_irq(dp8393xState *s) 256 { 257 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; 258 259 if (level != s->irq_level) { 260 s->irq_level = level; 261 if (level) { 262 trace_dp8393x_raise_irq(s->regs[SONIC_ISR]); 263 } else { 264 trace_dp8393x_lower_irq(); 265 } 266 } 267 268 qemu_set_irq(s->irq, level); 269 } 270 271 static void dp8393x_do_load_cam(dp8393xState *s) 272 { 273 int width, size; 274 uint16_t index; 275 276 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 277 size = sizeof(uint16_t) * 4 * width; 278 279 while (s->regs[SONIC_CDC] & 0x1f) { 280 /* Fill current entry */ 281 address_space_read(&s->as, dp8393x_cdp(s), 282 MEMTXATTRS_UNSPECIFIED, s->data, size); 283 index = dp8393x_get(s, width, 0) & 0xf; 284 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; 285 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; 286 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; 287 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8; 288 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff; 289 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8; 290 trace_dp8393x_load_cam(index, s->cam[index][0], s->cam[index][1], 291 s->cam[index][2], s->cam[index][3], 292 s->cam[index][4], s->cam[index][5]); 293 /* Move to next entry */ 294 s->regs[SONIC_CDC]--; 295 s->regs[SONIC_CDP] += size; 296 } 297 298 /* Read CAM enable */ 299 address_space_read(&s->as, dp8393x_cdp(s), 300 MEMTXATTRS_UNSPECIFIED, s->data, size); 301 s->regs[SONIC_CE] = dp8393x_get(s, width, 0); 302 trace_dp8393x_load_cam_done(s->regs[SONIC_CE]); 303 304 /* Done */ 305 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM; 306 s->regs[SONIC_ISR] |= SONIC_ISR_LCD; 307 dp8393x_update_irq(s); 308 } 309 310 static void dp8393x_do_read_rra(dp8393xState *s) 311 { 312 int width, size; 313 314 /* Read memory */ 315 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 316 size = sizeof(uint16_t) * 4 * width; 317 address_space_read(&s->as, dp8393x_rrp(s), 318 MEMTXATTRS_UNSPECIFIED, s->data, size); 319 320 /* Update SONIC registers */ 321 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); 322 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1); 323 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2); 324 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3); 325 trace_dp8393x_read_rra_regs(s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], 326 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); 327 328 /* Go to next entry */ 329 s->regs[SONIC_RRP] += size; 330 331 /* Handle wrap */ 332 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) { 333 s->regs[SONIC_RRP] = s->regs[SONIC_RSA]; 334 } 335 336 /* Warn the host if CRBA now has the last available resource */ 337 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) { 338 s->regs[SONIC_ISR] |= SONIC_ISR_RBE; 339 dp8393x_update_irq(s); 340 } 341 342 /* Allow packet reception */ 343 s->last_rba_is_full = false; 344 } 345 346 static void dp8393x_do_software_reset(dp8393xState *s) 347 { 348 timer_del(s->watchdog); 349 350 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | 351 SONIC_CR_HTX); 352 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS; 353 } 354 355 static void dp8393x_set_next_tick(dp8393xState *s) 356 { 357 uint32_t ticks; 358 int64_t delay; 359 360 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 361 timer_del(s->watchdog); 362 return; 363 } 364 365 ticks = dp8393x_wt(s); 366 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 367 delay = NANOSECONDS_PER_SECOND * ticks / 5000000; 368 timer_mod(s->watchdog, s->wt_last_update + delay); 369 } 370 371 static void dp8393x_update_wt_regs(dp8393xState *s) 372 { 373 int64_t elapsed; 374 uint32_t val; 375 376 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 377 timer_del(s->watchdog); 378 return; 379 } 380 381 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 382 val = dp8393x_wt(s); 383 val -= elapsed / 5000000; 384 s->regs[SONIC_WT1] = (val >> 16) & 0xffff; 385 s->regs[SONIC_WT0] = (val >> 0) & 0xffff; 386 dp8393x_set_next_tick(s); 387 388 } 389 390 static void dp8393x_do_start_timer(dp8393xState *s) 391 { 392 s->regs[SONIC_CR] &= ~SONIC_CR_STP; 393 dp8393x_set_next_tick(s); 394 } 395 396 static void dp8393x_do_stop_timer(dp8393xState *s) 397 { 398 s->regs[SONIC_CR] &= ~SONIC_CR_ST; 399 dp8393x_update_wt_regs(s); 400 } 401 402 static bool dp8393x_can_receive(NetClientState *nc); 403 404 static void dp8393x_do_receiver_enable(dp8393xState *s) 405 { 406 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS; 407 if (dp8393x_can_receive(s->nic->ncs)) { 408 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 409 } 410 } 411 412 static void dp8393x_do_receiver_disable(dp8393xState *s) 413 { 414 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN; 415 } 416 417 static void dp8393x_do_transmit_packets(dp8393xState *s) 418 { 419 NetClientState *nc = qemu_get_queue(s->nic); 420 int width, size; 421 int tx_len, len; 422 uint16_t i; 423 424 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; 425 426 while (1) { 427 /* Read memory */ 428 size = sizeof(uint16_t) * 6 * width; 429 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; 430 trace_dp8393x_transmit_packet(dp8393x_ttda(s)); 431 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, 432 MEMTXATTRS_UNSPECIFIED, s->data, size); 433 tx_len = 0; 434 435 /* Update registers */ 436 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000; 437 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1); 438 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2); 439 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3); 440 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4); 441 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5); 442 443 /* Handle programmable interrupt */ 444 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { 445 s->regs[SONIC_ISR] |= SONIC_ISR_PINT; 446 } else { 447 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT; 448 } 449 450 for (i = 0; i < s->regs[SONIC_TFC]; ) { 451 /* Append fragment */ 452 len = s->regs[SONIC_TFS]; 453 if (tx_len + len > sizeof(s->tx_buffer)) { 454 len = sizeof(s->tx_buffer) - tx_len; 455 } 456 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, 457 &s->tx_buffer[tx_len], len); 458 tx_len += len; 459 460 i++; 461 if (i != s->regs[SONIC_TFC]) { 462 /* Read next fragment details */ 463 size = sizeof(uint16_t) * 3 * width; 464 address_space_read(&s->as, 465 dp8393x_ttda(s) 466 + sizeof(uint16_t) * width * (4 + 3 * i), 467 MEMTXATTRS_UNSPECIFIED, s->data, 468 size); 469 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); 470 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); 471 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); 472 } 473 } 474 475 /* Handle Ethernet checksum */ 476 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { 477 /* 478 * Don't append FCS there, to look like slirp packets 479 * which don't have one 480 */ 481 } else { 482 /* Remove existing FCS */ 483 tx_len -= 4; 484 if (tx_len < 0) { 485 trace_dp8393x_transmit_txlen_error(tx_len); 486 break; 487 } 488 } 489 490 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) { 491 /* Loopback */ 492 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL; 493 if (nc->info->can_receive(nc)) { 494 s->loopback_packet = 1; 495 qemu_receive_packet(nc, s->tx_buffer, tx_len); 496 } 497 } else { 498 /* Transmit packet */ 499 qemu_send_packet(nc, s->tx_buffer, tx_len); 500 } 501 s->regs[SONIC_TCR] |= SONIC_TCR_PTX; 502 503 /* Write status */ 504 dp8393x_put(s, width, 0, 505 s->regs[SONIC_TCR] & 0x0fff); /* status */ 506 size = sizeof(uint16_t) * width; 507 address_space_write(&s->as, dp8393x_ttda(s), 508 MEMTXATTRS_UNSPECIFIED, s->data, size); 509 510 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { 511 /* Read footer of packet */ 512 size = sizeof(uint16_t) * width; 513 address_space_read(&s->as, 514 dp8393x_ttda(s) 515 + sizeof(uint16_t) * width 516 * (4 + 3 * s->regs[SONIC_TFC]), 517 MEMTXATTRS_UNSPECIFIED, s->data, 518 size); 519 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0); 520 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) { 521 /* EOL detected */ 522 break; 523 } 524 } 525 } 526 527 /* Done */ 528 s->regs[SONIC_CR] &= ~SONIC_CR_TXP; 529 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN; 530 dp8393x_update_irq(s); 531 } 532 533 static void dp8393x_do_halt_transmission(dp8393xState *s) 534 { 535 /* Nothing to do */ 536 } 537 538 static void dp8393x_do_command(dp8393xState *s, uint16_t command) 539 { 540 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) { 541 s->regs[SONIC_CR] &= ~SONIC_CR_RST; 542 return; 543 } 544 545 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK); 546 547 if (command & SONIC_CR_HTX) { 548 dp8393x_do_halt_transmission(s); 549 } 550 if (command & SONIC_CR_TXP) { 551 dp8393x_do_transmit_packets(s); 552 } 553 if (command & SONIC_CR_RXDIS) { 554 dp8393x_do_receiver_disable(s); 555 } 556 if (command & SONIC_CR_RXEN) { 557 dp8393x_do_receiver_enable(s); 558 } 559 if (command & SONIC_CR_STP) { 560 dp8393x_do_stop_timer(s); 561 } 562 if (command & SONIC_CR_ST) { 563 dp8393x_do_start_timer(s); 564 } 565 if (command & SONIC_CR_RST) { 566 dp8393x_do_software_reset(s); 567 } 568 if (command & SONIC_CR_RRRA) { 569 dp8393x_do_read_rra(s); 570 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA; 571 } 572 if (command & SONIC_CR_LCAM) { 573 dp8393x_do_load_cam(s); 574 } 575 } 576 577 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) 578 { 579 dp8393xState *s = opaque; 580 int reg = addr >> s->it_shift; 581 uint16_t val = 0; 582 583 switch (reg) { 584 /* Update data before reading it */ 585 case SONIC_WT0: 586 case SONIC_WT1: 587 dp8393x_update_wt_regs(s); 588 val = s->regs[reg]; 589 break; 590 /* Accept read to some registers only when in reset mode */ 591 case SONIC_CAP2: 592 case SONIC_CAP1: 593 case SONIC_CAP0: 594 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 595 val = s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg) + 1] << 8; 596 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg)]; 597 } 598 break; 599 /* All other registers have no special contraints */ 600 default: 601 val = s->regs[reg]; 602 } 603 604 trace_dp8393x_read(reg, reg_names[reg], val, size); 605 606 return s->big_endian ? val << 16 : val; 607 } 608 609 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, 610 unsigned int size) 611 { 612 dp8393xState *s = opaque; 613 int reg = addr >> s->it_shift; 614 uint32_t val = s->big_endian ? data >> 16 : data; 615 616 trace_dp8393x_write(reg, reg_names[reg], val, size); 617 618 switch (reg) { 619 /* Command register */ 620 case SONIC_CR: 621 dp8393x_do_command(s, val); 622 break; 623 /* Prevent write to read-only registers */ 624 case SONIC_CAP2: 625 case SONIC_CAP1: 626 case SONIC_CAP0: 627 case SONIC_SR: 628 case SONIC_MDT: 629 trace_dp8393x_write_invalid(reg); 630 break; 631 /* Accept write to some registers only when in reset mode */ 632 case SONIC_DCR: 633 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 634 s->regs[reg] = val & 0xbfff; 635 } else { 636 trace_dp8393x_write_invalid_dcr("DCR"); 637 } 638 break; 639 case SONIC_DCR2: 640 if (s->regs[SONIC_CR] & SONIC_CR_RST) { 641 s->regs[reg] = val & 0xf017; 642 } else { 643 trace_dp8393x_write_invalid_dcr("DCR2"); 644 } 645 break; 646 /* 12 lower bytes are Read Only */ 647 case SONIC_TCR: 648 s->regs[reg] = val & 0xf000; 649 break; 650 /* 9 lower bytes are Read Only */ 651 case SONIC_RCR: 652 s->regs[reg] = val & 0xffe0; 653 break; 654 /* Ignore most significant bit */ 655 case SONIC_IMR: 656 s->regs[reg] = val & 0x7fff; 657 dp8393x_update_irq(s); 658 break; 659 /* Clear bits by writing 1 to them */ 660 case SONIC_ISR: 661 val &= s->regs[reg]; 662 s->regs[reg] &= ~val; 663 if (val & SONIC_ISR_RBE) { 664 dp8393x_do_read_rra(s); 665 } 666 dp8393x_update_irq(s); 667 break; 668 /* The guest is required to store aligned pointers here */ 669 case SONIC_RSA: 670 case SONIC_REA: 671 case SONIC_RRP: 672 case SONIC_RWP: 673 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { 674 s->regs[reg] = val & 0xfffc; 675 } else { 676 s->regs[reg] = val & 0xfffe; 677 } 678 break; 679 /* Invert written value for some registers */ 680 case SONIC_CRCT: 681 case SONIC_FAET: 682 case SONIC_MPT: 683 s->regs[reg] = val ^ 0xffff; 684 break; 685 /* All other registers have no special contrainst */ 686 default: 687 s->regs[reg] = val; 688 } 689 690 if (reg == SONIC_WT0 || reg == SONIC_WT1) { 691 dp8393x_set_next_tick(s); 692 } 693 } 694 695 static const MemoryRegionOps dp8393x_ops = { 696 .read = dp8393x_read, 697 .write = dp8393x_write, 698 .impl.min_access_size = 4, 699 .impl.max_access_size = 4, 700 .endianness = DEVICE_NATIVE_ENDIAN, 701 }; 702 703 static void dp8393x_watchdog(void *opaque) 704 { 705 dp8393xState *s = opaque; 706 707 if (s->regs[SONIC_CR] & SONIC_CR_STP) { 708 return; 709 } 710 711 s->regs[SONIC_WT1] = 0xffff; 712 s->regs[SONIC_WT0] = 0xffff; 713 dp8393x_set_next_tick(s); 714 715 /* Signal underflow */ 716 s->regs[SONIC_ISR] |= SONIC_ISR_TC; 717 dp8393x_update_irq(s); 718 } 719 720 static bool dp8393x_can_receive(NetClientState *nc) 721 { 722 dp8393xState *s = qemu_get_nic_opaque(nc); 723 724 return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN); 725 } 726 727 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf, 728 int size) 729 { 730 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 731 int i; 732 733 /* Check promiscuous mode */ 734 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) { 735 return 0; 736 } 737 738 /* Check multicast packets */ 739 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) { 740 return SONIC_RCR_MC; 741 } 742 743 /* Check broadcast */ 744 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && 745 !memcmp(buf, bcast, sizeof(bcast))) { 746 return SONIC_RCR_BC; 747 } 748 749 /* Check CAM */ 750 for (i = 0; i < 16; i++) { 751 if (s->regs[SONIC_CE] & (1 << i)) { 752 /* Entry enabled */ 753 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { 754 return 0; 755 } 756 } 757 } 758 759 return -1; 760 } 761 762 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, 763 size_t pkt_size) 764 { 765 dp8393xState *s = qemu_get_nic_opaque(nc); 766 int packet_type; 767 uint32_t available, address; 768 int width, rx_len, padded_len; 769 uint32_t checksum; 770 int size; 771 772 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER | 773 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC); 774 775 if (s->last_rba_is_full) { 776 return pkt_size; 777 } 778 779 rx_len = pkt_size + sizeof(checksum); 780 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { 781 width = 2; 782 padded_len = ((rx_len - 1) | 3) + 1; 783 } else { 784 width = 1; 785 padded_len = ((rx_len - 1) | 1) + 1; 786 } 787 788 if (padded_len > dp8393x_rbwc(s) * 2) { 789 trace_dp8393x_receive_oversize(pkt_size); 790 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE; 791 dp8393x_update_irq(s); 792 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 793 goto done; 794 } 795 796 packet_type = dp8393x_receive_filter(s, buf, pkt_size); 797 if (packet_type < 0) { 798 trace_dp8393x_receive_not_netcard(); 799 return -1; 800 } 801 802 /* Check for EOL */ 803 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 804 /* Are we still in resource exhaustion? */ 805 size = sizeof(uint16_t) * 1 * width; 806 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; 807 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, 808 s->data, size); 809 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 810 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 811 /* Still EOL ; stop reception */ 812 return -1; 813 } 814 /* Link has been updated by host */ 815 816 /* Clear in_use */ 817 size = sizeof(uint16_t) * width; 818 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 819 dp8393x_put(s, width, 0, 0); 820 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 821 s->data, size); 822 823 /* Move to next descriptor */ 824 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 825 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 826 } 827 828 /* Save current position */ 829 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1]; 830 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0]; 831 832 /* Calculate the ethernet checksum */ 833 checksum = cpu_to_le32(crc32(0, buf, pkt_size)); 834 835 /* Put packet into RBA */ 836 trace_dp8393x_receive_packet(dp8393x_crba(s)); 837 address = dp8393x_crba(s); 838 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 839 buf, pkt_size); 840 address += pkt_size; 841 842 /* Put frame checksum into RBA */ 843 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 844 &checksum, sizeof(checksum)); 845 address += sizeof(checksum); 846 847 /* Pad short packets to keep pointers aligned */ 848 if (rx_len < padded_len) { 849 size = padded_len - rx_len; 850 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 851 "\xFF\xFF\xFF", size); 852 address += size; 853 } 854 855 s->regs[SONIC_CRBA1] = address >> 16; 856 s->regs[SONIC_CRBA0] = address & 0xffff; 857 available = dp8393x_rbwc(s); 858 available -= padded_len >> 1; 859 s->regs[SONIC_RBWC1] = available >> 16; 860 s->regs[SONIC_RBWC0] = available & 0xffff; 861 862 /* Update status */ 863 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) { 864 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT; 865 } 866 s->regs[SONIC_RCR] |= packet_type; 867 s->regs[SONIC_RCR] |= SONIC_RCR_PRX; 868 if (s->loopback_packet) { 869 s->regs[SONIC_RCR] |= SONIC_RCR_LBK; 870 s->loopback_packet = 0; 871 } 872 873 /* Write status to memory */ 874 trace_dp8393x_receive_write_status(dp8393x_crda(s)); 875 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ 876 dp8393x_put(s, width, 1, rx_len); /* byte count */ 877 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ 878 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ 879 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ 880 size = sizeof(uint16_t) * 5 * width; 881 address_space_write(&s->as, dp8393x_crda(s), 882 MEMTXATTRS_UNSPECIFIED, 883 s->data, size); 884 885 /* Check link field */ 886 size = sizeof(uint16_t) * width; 887 address_space_read(&s->as, 888 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, 889 MEMTXATTRS_UNSPECIFIED, s->data, size); 890 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); 891 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { 892 /* EOL detected */ 893 s->regs[SONIC_ISR] |= SONIC_ISR_RDE; 894 } else { 895 /* Clear in_use */ 896 size = sizeof(uint16_t) * width; 897 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; 898 dp8393x_put(s, width, 0, 0); 899 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, 900 s->data, size); 901 902 /* Move to next descriptor */ 903 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; 904 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; 905 } 906 907 dp8393x_update_irq(s); 908 909 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | 910 ((s->regs[SONIC_RSC] + 1) & 0x00ff); 911 912 done: 913 914 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) { 915 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) { 916 /* Stop packet reception */ 917 s->last_rba_is_full = true; 918 } else { 919 /* Read next resource */ 920 dp8393x_do_read_rra(s); 921 } 922 } 923 924 return pkt_size; 925 } 926 927 static void dp8393x_reset(DeviceState *dev) 928 { 929 dp8393xState *s = DP8393X(dev); 930 timer_del(s->watchdog); 931 932 memset(s->regs, 0, sizeof(s->regs)); 933 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */ 934 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; 935 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); 936 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | 937 SONIC_RCR_RNT); 938 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX; 939 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM; 940 s->regs[SONIC_IMR] = 0; 941 s->regs[SONIC_ISR] = 0; 942 s->regs[SONIC_DCR2] = 0; 943 s->regs[SONIC_EOBC] = 0x02F8; 944 s->regs[SONIC_RSC] = 0; 945 s->regs[SONIC_CE] = 0; 946 s->regs[SONIC_RSC] = 0; 947 948 /* Network cable is connected */ 949 s->regs[SONIC_RCR] |= SONIC_RCR_CRS; 950 951 dp8393x_update_irq(s); 952 } 953 954 static NetClientInfo net_dp83932_info = { 955 .type = NET_CLIENT_DRIVER_NIC, 956 .size = sizeof(NICState), 957 .can_receive = dp8393x_can_receive, 958 .receive = dp8393x_receive, 959 }; 960 961 static void dp8393x_instance_init(Object *obj) 962 { 963 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 964 dp8393xState *s = DP8393X(obj); 965 966 sysbus_init_mmio(sbd, &s->mmio); 967 sysbus_init_irq(sbd, &s->irq); 968 } 969 970 static void dp8393x_realize(DeviceState *dev, Error **errp) 971 { 972 dp8393xState *s = DP8393X(dev); 973 974 address_space_init(&s->as, s->dma_mr, "dp8393x"); 975 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, 976 "dp8393x-regs", SONIC_REG_COUNT << s->it_shift); 977 978 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, 979 object_get_typename(OBJECT(dev)), dev->id, s); 980 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 981 982 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); 983 } 984 985 static const VMStateDescription vmstate_dp8393x = { 986 .name = "dp8393x", 987 .version_id = 0, 988 .minimum_version_id = 0, 989 .fields = (VMStateField []) { 990 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), 991 VMSTATE_UINT16_ARRAY(regs, dp8393xState, SONIC_REG_COUNT), 992 VMSTATE_END_OF_LIST() 993 } 994 }; 995 996 static Property dp8393x_properties[] = { 997 DEFINE_NIC_PROPERTIES(dp8393xState, conf), 998 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr, 999 TYPE_MEMORY_REGION, MemoryRegion *), 1000 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), 1001 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), 1002 DEFINE_PROP_END_OF_LIST(), 1003 }; 1004 1005 static void dp8393x_class_init(ObjectClass *klass, void *data) 1006 { 1007 DeviceClass *dc = DEVICE_CLASS(klass); 1008 1009 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 1010 dc->realize = dp8393x_realize; 1011 dc->reset = dp8393x_reset; 1012 dc->vmsd = &vmstate_dp8393x; 1013 device_class_set_props(dc, dp8393x_properties); 1014 } 1015 1016 static const TypeInfo dp8393x_info = { 1017 .name = TYPE_DP8393X, 1018 .parent = TYPE_SYS_BUS_DEVICE, 1019 .instance_size = sizeof(dp8393xState), 1020 .instance_init = dp8393x_instance_init, 1021 .class_init = dp8393x_class_init, 1022 }; 1023 1024 static void dp8393x_register_types(void) 1025 { 1026 type_register_static(&dp8393x_info); 1027 } 1028 1029 type_init(dp8393x_register_types) 1030