1 /* 2 * CAN device - SJA1000 chip emulation for QEMU 3 * 4 * Copyright (c) 2013-2014 Jin Yang 5 * Copyright (c) 2014-2018 Pavel Pisa 6 * 7 * Initial development supported by Google GSoC 2013 from RTEMS project slot 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "chardev/char.h" 31 #include "hw/irq.h" 32 #include "migration/vmstate.h" 33 #include "net/can_emu.h" 34 35 #include "can_sja1000.h" 36 37 #ifndef DEBUG_FILTER 38 #define DEBUG_FILTER 0 39 #endif /*DEBUG_FILTER*/ 40 41 #ifndef DEBUG_CAN 42 #define DEBUG_CAN 0 43 #endif /*DEBUG_CAN*/ 44 45 #define DPRINTF(fmt, ...) \ 46 do { \ 47 if (DEBUG_CAN) { \ 48 qemu_log("[cansja]: " fmt , ## __VA_ARGS__); \ 49 } \ 50 } while (0) 51 52 static void can_sja_software_reset(CanSJA1000State *s) 53 { 54 s->mode &= ~0x31; 55 s->mode |= 0x01; 56 s->status_pel &= ~0x37; 57 s->status_pel |= 0x34; 58 59 s->rxbuf_start = 0x00; 60 s->rxmsg_cnt = 0x00; 61 s->rx_cnt = 0x00; 62 } 63 64 void can_sja_hardware_reset(CanSJA1000State *s) 65 { 66 /* Reset by hardware, p10 */ 67 s->mode = 0x01; 68 s->status_pel = 0x3c; 69 s->interrupt_pel = 0x00; 70 s->clock = 0x00; 71 s->rxbuf_start = 0x00; 72 s->rxmsg_cnt = 0x00; 73 s->rx_cnt = 0x00; 74 75 s->control = 0x01; 76 s->status_bas = 0x0c; 77 s->interrupt_bas = 0x00; 78 79 qemu_irq_lower(s->irq); 80 } 81 82 static 83 void can_sja_single_filter(struct qemu_can_filter *filter, 84 const uint8_t *acr, const uint8_t *amr, int extended) 85 { 86 if (extended) { 87 filter->can_id = (uint32_t)acr[0] << 21; 88 filter->can_id |= (uint32_t)acr[1] << 13; 89 filter->can_id |= (uint32_t)acr[2] << 5; 90 filter->can_id |= (uint32_t)acr[3] >> 3; 91 if (acr[3] & 4) { 92 filter->can_id |= QEMU_CAN_RTR_FLAG; 93 } 94 95 filter->can_mask = (uint32_t)amr[0] << 21; 96 filter->can_mask |= (uint32_t)amr[1] << 13; 97 filter->can_mask |= (uint32_t)amr[2] << 5; 98 filter->can_mask |= (uint32_t)amr[3] >> 3; 99 filter->can_mask = ~filter->can_mask & QEMU_CAN_EFF_MASK; 100 if (!(amr[3] & 4)) { 101 filter->can_mask |= QEMU_CAN_RTR_FLAG; 102 } 103 } else { 104 filter->can_id = (uint32_t)acr[0] << 3; 105 filter->can_id |= (uint32_t)acr[1] >> 5; 106 if (acr[1] & 0x10) { 107 filter->can_id |= QEMU_CAN_RTR_FLAG; 108 } 109 110 filter->can_mask = (uint32_t)amr[0] << 3; 111 filter->can_mask |= (uint32_t)amr[1] << 5; 112 filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK; 113 if (!(amr[1] & 0x10)) { 114 filter->can_mask |= QEMU_CAN_RTR_FLAG; 115 } 116 } 117 } 118 119 static 120 void can_sja_dual_filter(struct qemu_can_filter *filter, 121 const uint8_t *acr, const uint8_t *amr, int extended) 122 { 123 if (extended) { 124 filter->can_id = (uint32_t)acr[0] << 21; 125 filter->can_id |= (uint32_t)acr[1] << 13; 126 127 filter->can_mask = (uint32_t)amr[0] << 21; 128 filter->can_mask |= (uint32_t)amr[1] << 13; 129 filter->can_mask = ~filter->can_mask & QEMU_CAN_EFF_MASK & ~0x1fff; 130 } else { 131 filter->can_id = (uint32_t)acr[0] << 3; 132 filter->can_id |= (uint32_t)acr[1] >> 5; 133 if (acr[1] & 0x10) { 134 filter->can_id |= QEMU_CAN_RTR_FLAG; 135 } 136 137 filter->can_mask = (uint32_t)amr[0] << 3; 138 filter->can_mask |= (uint32_t)amr[1] >> 5; 139 filter->can_mask = ~filter->can_mask & QEMU_CAN_SFF_MASK; 140 if (!(amr[1] & 0x10)) { 141 filter->can_mask |= QEMU_CAN_RTR_FLAG; 142 } 143 } 144 } 145 146 /* Details in DS-p22, what we need to do here is to test the data. */ 147 static 148 int can_sja_accept_filter(CanSJA1000State *s, 149 const qemu_can_frame *frame) 150 { 151 152 struct qemu_can_filter filter; 153 154 if (s->clock & 0x80) { /* PeliCAN Mode */ 155 if (s->mode & (1 << 3)) { /* Single mode. */ 156 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 157 can_sja_single_filter(&filter, 158 s->code_mask + 0, s->code_mask + 4, 1); 159 160 if (!can_bus_filter_match(&filter, frame->can_id)) { 161 return 0; 162 } 163 } else { /* SFF */ 164 can_sja_single_filter(&filter, 165 s->code_mask + 0, s->code_mask + 4, 0); 166 167 if (!can_bus_filter_match(&filter, frame->can_id)) { 168 return 0; 169 } 170 171 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 172 return 1; 173 } 174 175 if (frame->can_dlc == 0) { 176 return 1; 177 } 178 179 if ((frame->data[0] & ~(s->code_mask[6])) != 180 (s->code_mask[2] & ~(s->code_mask[6]))) { 181 return 0; 182 } 183 184 if (frame->can_dlc < 2) { 185 return 1; 186 } 187 188 if ((frame->data[1] & ~(s->code_mask[7])) == 189 (s->code_mask[3] & ~(s->code_mask[7]))) { 190 return 1; 191 } 192 193 return 0; 194 } 195 } else { /* Dual mode */ 196 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 197 can_sja_dual_filter(&filter, 198 s->code_mask + 0, s->code_mask + 4, 1); 199 200 if (can_bus_filter_match(&filter, frame->can_id)) { 201 return 1; 202 } 203 204 can_sja_dual_filter(&filter, 205 s->code_mask + 2, s->code_mask + 6, 1); 206 207 if (can_bus_filter_match(&filter, frame->can_id)) { 208 return 1; 209 } 210 211 return 0; 212 } else { 213 can_sja_dual_filter(&filter, 214 s->code_mask + 0, s->code_mask + 4, 0); 215 216 if (can_bus_filter_match(&filter, frame->can_id)) { 217 uint8_t expect; 218 uint8_t mask; 219 expect = s->code_mask[1] << 4; 220 expect |= s->code_mask[3] & 0x0f; 221 222 mask = s->code_mask[5] << 4; 223 mask |= s->code_mask[7] & 0x0f; 224 mask = ~mask & 0xff; 225 226 if ((frame->data[0] & mask) == 227 (expect & mask)) { 228 return 1; 229 } 230 } 231 232 can_sja_dual_filter(&filter, 233 s->code_mask + 2, s->code_mask + 6, 0); 234 235 if (can_bus_filter_match(&filter, frame->can_id)) { 236 return 1; 237 } 238 239 return 0; 240 } 241 } 242 } 243 244 return 1; 245 } 246 247 static void can_display_msg(const char *prefix, const qemu_can_frame *msg) 248 { 249 int i; 250 FILE *logfile = qemu_log_lock(); 251 252 qemu_log("%s%03X [%01d] %s %s", 253 prefix, 254 msg->can_id & QEMU_CAN_EFF_MASK, 255 msg->can_dlc, 256 msg->can_id & QEMU_CAN_EFF_FLAG ? "EFF" : "SFF", 257 msg->can_id & QEMU_CAN_RTR_FLAG ? "RTR" : "DAT"); 258 259 for (i = 0; i < msg->can_dlc; i++) { 260 qemu_log(" %02X", msg->data[i]); 261 } 262 qemu_log("\n"); 263 qemu_log_flush(); 264 qemu_log_unlock(logfile); 265 } 266 267 static void buff2frame_pel(const uint8_t *buff, qemu_can_frame *frame) 268 { 269 uint8_t i; 270 271 frame->flags = 0; 272 frame->can_id = 0; 273 if (buff[0] & 0x40) { /* RTR */ 274 frame->can_id = QEMU_CAN_RTR_FLAG; 275 } 276 frame->can_dlc = buff[0] & 0x0f; 277 278 if (buff[0] & 0x80) { /* Extended */ 279 frame->can_id |= QEMU_CAN_EFF_FLAG; 280 frame->can_id |= buff[1] << 21; /* ID.28~ID.21 */ 281 frame->can_id |= buff[2] << 13; /* ID.20~ID.13 */ 282 frame->can_id |= buff[3] << 5; 283 frame->can_id |= buff[4] >> 3; 284 for (i = 0; i < frame->can_dlc; i++) { 285 frame->data[i] = buff[5 + i]; 286 } 287 for (; i < 8; i++) { 288 frame->data[i] = 0; 289 } 290 } else { 291 frame->can_id |= buff[1] << 3; 292 frame->can_id |= buff[2] >> 5; 293 for (i = 0; i < frame->can_dlc; i++) { 294 frame->data[i] = buff[3 + i]; 295 } 296 for (; i < 8; i++) { 297 frame->data[i] = 0; 298 } 299 } 300 } 301 302 303 static void buff2frame_bas(const uint8_t *buff, qemu_can_frame *frame) 304 { 305 uint8_t i; 306 307 frame->flags = 0; 308 frame->can_id = ((buff[0] << 3) & (0xff << 3)) + ((buff[1] >> 5) & 0x07); 309 if (buff[1] & 0x10) { /* RTR */ 310 frame->can_id = QEMU_CAN_RTR_FLAG; 311 } 312 frame->can_dlc = buff[1] & 0x0f; 313 314 for (i = 0; i < frame->can_dlc; i++) { 315 frame->data[i] = buff[2 + i]; 316 } 317 for (; i < 8; i++) { 318 frame->data[i] = 0; 319 } 320 } 321 322 323 static int frame2buff_pel(const qemu_can_frame *frame, uint8_t *buff) 324 { 325 int i; 326 327 if (frame->can_id & QEMU_CAN_ERR_FLAG) { /* error frame, NOT support now. */ 328 return -1; 329 } 330 331 buff[0] = 0x0f & frame->can_dlc; /* DLC */ 332 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 333 buff[0] |= (1 << 6); 334 } 335 if (frame->can_id & QEMU_CAN_EFF_FLAG) { /* EFF */ 336 buff[0] |= (1 << 7); 337 buff[1] = extract32(frame->can_id, 21, 8); /* ID.28~ID.21 */ 338 buff[2] = extract32(frame->can_id, 13, 8); /* ID.20~ID.13 */ 339 buff[3] = extract32(frame->can_id, 5, 8); /* ID.12~ID.05 */ 340 buff[4] = extract32(frame->can_id, 0, 5) << 3; /* ID.04~ID.00,xxx */ 341 for (i = 0; i < frame->can_dlc; i++) { 342 buff[5 + i] = frame->data[i]; 343 } 344 return frame->can_dlc + 5; 345 } else { /* SFF */ 346 buff[1] = extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */ 347 buff[2] = extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx */ 348 for (i = 0; i < frame->can_dlc; i++) { 349 buff[3 + i] = frame->data[i]; 350 } 351 352 return frame->can_dlc + 3; 353 } 354 355 return -1; 356 } 357 358 static int frame2buff_bas(const qemu_can_frame *frame, uint8_t *buff) 359 { 360 int i; 361 362 /* 363 * EFF, no support for BasicMode 364 * No use for Error frames now, 365 * they could be used in future to update SJA1000 error state 366 */ 367 if ((frame->can_id & QEMU_CAN_EFF_FLAG) || 368 (frame->can_id & QEMU_CAN_ERR_FLAG)) { 369 return -1; 370 } 371 372 buff[0] = extract32(frame->can_id, 3, 8); /* ID.10~ID.03 */ 373 buff[1] = extract32(frame->can_id, 0, 3) << 5; /* ID.02~ID.00,xxxxx */ 374 if (frame->can_id & QEMU_CAN_RTR_FLAG) { /* RTR */ 375 buff[1] |= (1 << 4); 376 } 377 buff[1] |= frame->can_dlc & 0x0f; 378 for (i = 0; i < frame->can_dlc; i++) { 379 buff[2 + i] = frame->data[i]; 380 } 381 382 return frame->can_dlc + 2; 383 } 384 385 static void can_sja_update_pel_irq(CanSJA1000State *s) 386 { 387 if (s->interrupt_en & s->interrupt_pel) { 388 qemu_irq_raise(s->irq); 389 } else { 390 qemu_irq_lower(s->irq); 391 } 392 } 393 394 static void can_sja_update_bas_irq(CanSJA1000State *s) 395 { 396 if ((s->control >> 1) & s->interrupt_bas) { 397 qemu_irq_raise(s->irq); 398 } else { 399 qemu_irq_lower(s->irq); 400 } 401 } 402 403 void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val, 404 unsigned size) 405 { 406 qemu_can_frame frame; 407 uint32_t tmp; 408 uint8_t tmp8, count; 409 410 411 DPRINTF("write 0x%02llx addr 0x%02x\n", 412 (unsigned long long)val, (unsigned int)addr); 413 414 if (addr > CAN_SJA_MEM_SIZE) { 415 return ; 416 } 417 418 if (s->clock & 0x80) { /* PeliCAN Mode */ 419 switch (addr) { 420 case SJA_MOD: /* Mode register */ 421 s->mode = 0x1f & val; 422 if ((s->mode & 0x01) && ((val & 0x01) == 0)) { 423 /* Go to operation mode from reset mode. */ 424 if (s->mode & (1 << 3)) { /* Single mode. */ 425 /* For EFF */ 426 can_sja_single_filter(&s->filter[0], 427 s->code_mask + 0, s->code_mask + 4, 1); 428 429 /* For SFF */ 430 can_sja_single_filter(&s->filter[1], 431 s->code_mask + 0, s->code_mask + 4, 0); 432 433 can_bus_client_set_filters(&s->bus_client, s->filter, 2); 434 } else { /* Dual mode */ 435 /* For EFF */ 436 can_sja_dual_filter(&s->filter[0], 437 s->code_mask + 0, s->code_mask + 4, 1); 438 439 can_sja_dual_filter(&s->filter[1], 440 s->code_mask + 2, s->code_mask + 6, 1); 441 442 /* For SFF */ 443 can_sja_dual_filter(&s->filter[2], 444 s->code_mask + 0, s->code_mask + 4, 0); 445 446 can_sja_dual_filter(&s->filter[3], 447 s->code_mask + 2, s->code_mask + 6, 0); 448 449 can_bus_client_set_filters(&s->bus_client, s->filter, 4); 450 } 451 452 s->rxmsg_cnt = 0; 453 s->rx_cnt = 0; 454 } 455 break; 456 457 case SJA_CMR: /* Command register. */ 458 if (0x01 & val) { /* Send transmission request. */ 459 buff2frame_pel(s->tx_buff, &frame); 460 if (DEBUG_FILTER) { 461 can_display_msg("[cansja]: Tx request " , &frame); 462 } 463 464 /* 465 * Clear transmission complete status, 466 * and Transmit Buffer Status. 467 * write to the backends. 468 */ 469 s->status_pel &= ~(3 << 2); 470 471 can_bus_client_send(&s->bus_client, &frame, 1); 472 473 /* 474 * Set transmission complete status 475 * and Transmit Buffer Status. 476 */ 477 s->status_pel |= (3 << 2); 478 479 /* Clear transmit status. */ 480 s->status_pel &= ~(1 << 5); 481 s->interrupt_pel |= 0x02; 482 can_sja_update_pel_irq(s); 483 } 484 if (0x04 & val) { /* Release Receive Buffer */ 485 if (s->rxmsg_cnt <= 0) { 486 break; 487 } 488 489 tmp8 = s->rx_buff[s->rxbuf_start]; count = 0; 490 if (tmp8 & (1 << 7)) { /* EFF */ 491 count += 2; 492 } 493 count += 3; 494 if (!(tmp8 & (1 << 6))) { /* DATA */ 495 count += (tmp8 & 0x0f); 496 } 497 498 if (DEBUG_FILTER) { 499 qemu_log("[cansja]: message released from " 500 "Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count); 501 } 502 503 s->rxbuf_start += count; 504 s->rxbuf_start %= SJA_RCV_BUF_LEN; 505 506 s->rx_cnt -= count; 507 s->rxmsg_cnt--; 508 if (s->rxmsg_cnt == 0) { 509 s->status_pel &= ~(1 << 0); 510 s->interrupt_pel &= ~(1 << 0); 511 can_sja_update_pel_irq(s); 512 } 513 } 514 if (0x08 & val) { /* Clear data overrun */ 515 s->status_pel &= ~(1 << 1); 516 s->interrupt_pel &= ~(1 << 3); 517 can_sja_update_pel_irq(s); 518 } 519 break; 520 case SJA_SR: /* Status register */ 521 case SJA_IR: /* Interrupt register */ 522 break; /* Do nothing */ 523 case SJA_IER: /* Interrupt enable register */ 524 s->interrupt_en = val; 525 break; 526 case 16: /* RX frame information addr16-28. */ 527 s->status_pel |= (1 << 5); /* Set transmit status. */ 528 /* fallthrough */ 529 case 17 ... 28: 530 if (s->mode & 0x01) { /* Reset mode */ 531 if (addr < 24) { 532 s->code_mask[addr - 16] = val; 533 } 534 } else { /* Operation mode */ 535 s->tx_buff[addr - 16] = val; /* Store to TX buffer directly. */ 536 } 537 break; 538 case SJA_CDR: 539 s->clock = val; 540 break; 541 } 542 } else { /* Basic Mode */ 543 switch (addr) { 544 case SJA_BCAN_CTR: /* Control register, addr 0 */ 545 if ((s->control & 0x01) && ((val & 0x01) == 0)) { 546 /* Go to operation mode from reset mode. */ 547 s->filter[0].can_id = (s->code << 3) & (0xff << 3); 548 tmp = (~(s->mask << 3)) & (0xff << 3); 549 tmp |= QEMU_CAN_EFF_FLAG; /* Only Basic CAN Frame. */ 550 s->filter[0].can_mask = tmp; 551 can_bus_client_set_filters(&s->bus_client, s->filter, 1); 552 553 s->rxmsg_cnt = 0; 554 s->rx_cnt = 0; 555 } else if (!(s->control & 0x01) && !(val & 0x01)) { 556 can_sja_software_reset(s); 557 } 558 559 s->control = 0x1f & val; 560 break; 561 case SJA_BCAN_CMR: /* Command register, addr 1 */ 562 if (0x01 & val) { /* Send transmission request. */ 563 buff2frame_bas(s->tx_buff, &frame); 564 if (DEBUG_FILTER) { 565 can_display_msg("[cansja]: Tx request " , &frame); 566 } 567 568 /* 569 * Clear transmission complete status, 570 * and Transmit Buffer Status. 571 */ 572 s->status_bas &= ~(3 << 2); 573 574 /* write to the backends. */ 575 can_bus_client_send(&s->bus_client, &frame, 1); 576 577 /* 578 * Set transmission complete status, 579 * and Transmit Buffer Status. 580 */ 581 s->status_bas |= (3 << 2); 582 583 /* Clear transmit status. */ 584 s->status_bas &= ~(1 << 5); 585 s->interrupt_bas |= 0x02; 586 can_sja_update_bas_irq(s); 587 } 588 if (0x04 & val) { /* Release Receive Buffer */ 589 if (s->rxmsg_cnt <= 0) { 590 break; 591 } 592 593 tmp8 = s->rx_buff[(s->rxbuf_start + 1) % SJA_RCV_BUF_LEN]; 594 count = 2 + (tmp8 & 0x0f); 595 596 if (DEBUG_FILTER) { 597 qemu_log("[cansja]: message released from " 598 "Rx FIFO cnt=%d, count=%d\n", s->rx_cnt, count); 599 } 600 601 s->rxbuf_start += count; 602 s->rxbuf_start %= SJA_RCV_BUF_LEN; 603 s->rx_cnt -= count; 604 s->rxmsg_cnt--; 605 606 if (s->rxmsg_cnt == 0) { 607 s->status_bas &= ~(1 << 0); 608 s->interrupt_bas &= ~(1 << 0); 609 can_sja_update_bas_irq(s); 610 } 611 } 612 if (0x08 & val) { /* Clear data overrun */ 613 s->status_bas &= ~(1 << 1); 614 s->interrupt_bas &= ~(1 << 3); 615 can_sja_update_bas_irq(s); 616 } 617 break; 618 case 4: 619 s->code = val; 620 break; 621 case 5: 622 s->mask = val; 623 break; 624 case 10: 625 s->status_bas |= (1 << 5); /* Set transmit status. */ 626 /* fallthrough */ 627 case 11 ... 19: 628 if ((s->control & 0x01) == 0) { /* Operation mode */ 629 s->tx_buff[addr - 10] = val; /* Store to TX buffer directly. */ 630 } 631 break; 632 case SJA_CDR: 633 s->clock = val; 634 break; 635 } 636 } 637 } 638 639 uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size) 640 { 641 uint64_t temp = 0; 642 643 DPRINTF("read addr 0x%02x ...\n", (unsigned int)addr); 644 645 if (addr > CAN_SJA_MEM_SIZE) { 646 return 0; 647 } 648 649 if (s->clock & 0x80) { /* PeliCAN Mode */ 650 switch (addr) { 651 case SJA_MOD: /* Mode register, addr 0 */ 652 temp = s->mode; 653 break; 654 case SJA_CMR: /* Command register, addr 1 */ 655 temp = 0x00; /* Command register, cannot be read. */ 656 break; 657 case SJA_SR: /* Status register, addr 2 */ 658 temp = s->status_pel; 659 break; 660 case SJA_IR: /* Interrupt register, addr 3 */ 661 temp = s->interrupt_pel; 662 s->interrupt_pel = 0; 663 if (s->rxmsg_cnt) { 664 s->interrupt_pel |= (1 << 0); /* Receive interrupt. */ 665 } 666 can_sja_update_pel_irq(s); 667 break; 668 case SJA_IER: /* Interrupt enable register, addr 4 */ 669 temp = s->interrupt_en; 670 break; 671 case 5: /* Reserved */ 672 case 6: /* Bus timing 0, hardware related, not support now. */ 673 case 7: /* Bus timing 1, hardware related, not support now. */ 674 case 8: /* 675 * Output control register, hardware related, 676 * not supported for now. 677 */ 678 case 9: /* Test. */ 679 case 10 ... 15: /* Reserved */ 680 temp = 0x00; 681 break; 682 683 case 16 ... 28: 684 if (s->mode & 0x01) { /* Reset mode */ 685 if (addr < 24) { 686 temp = s->code_mask[addr - 16]; 687 } else { 688 temp = 0x00; 689 } 690 } else { /* Operation mode */ 691 temp = s->rx_buff[(s->rxbuf_start + addr - 16) % 692 SJA_RCV_BUF_LEN]; 693 } 694 break; 695 case SJA_CDR: 696 temp = s->clock; 697 break; 698 default: 699 temp = 0xff; 700 } 701 } else { /* Basic Mode */ 702 switch (addr) { 703 case SJA_BCAN_CTR: /* Control register, addr 0 */ 704 temp = s->control; 705 break; 706 case SJA_BCAN_SR: /* Status register, addr 2 */ 707 temp = s->status_bas; 708 break; 709 case SJA_BCAN_IR: /* Interrupt register, addr 3 */ 710 temp = s->interrupt_bas; 711 s->interrupt_bas = 0; 712 if (s->rxmsg_cnt) { 713 s->interrupt_bas |= (1 << 0); /* Receive interrupt. */ 714 } 715 can_sja_update_bas_irq(s); 716 break; 717 case 4: 718 temp = s->code; 719 break; 720 case 5: 721 temp = s->mask; 722 break; 723 case 20 ... 29: 724 temp = s->rx_buff[(s->rxbuf_start + addr - 20) % SJA_RCV_BUF_LEN]; 725 break; 726 case 31: 727 temp = s->clock; 728 break; 729 default: 730 temp = 0xff; 731 break; 732 } 733 } 734 DPRINTF("read addr 0x%02x, %d bytes, content 0x%02lx\n", 735 (int)addr, size, (long unsigned int)temp); 736 737 return temp; 738 } 739 740 bool can_sja_can_receive(CanBusClientState *client) 741 { 742 CanSJA1000State *s = container_of(client, CanSJA1000State, bus_client); 743 744 if (s->clock & 0x80) { /* PeliCAN Mode */ 745 if (s->mode & 0x01) { /* reset mode. */ 746 return false; 747 } 748 } else { /* BasicCAN mode */ 749 if (s->control & 0x01) { 750 return false; 751 } 752 } 753 754 return true; /* always return true, when operation mode */ 755 } 756 757 ssize_t can_sja_receive(CanBusClientState *client, const qemu_can_frame *frames, 758 size_t frames_cnt) 759 { 760 CanSJA1000State *s = container_of(client, CanSJA1000State, bus_client); 761 static uint8_t rcv[SJA_MSG_MAX_LEN]; 762 int i; 763 int ret = -1; 764 const qemu_can_frame *frame = frames; 765 766 if (frames_cnt <= 0) { 767 return 0; 768 } 769 if (DEBUG_FILTER) { 770 can_display_msg("[cansja]: receive ", frame); 771 } 772 773 if (s->clock & 0x80) { /* PeliCAN Mode */ 774 775 /* the CAN controller is receiving a message */ 776 s->status_pel |= (1 << 4); 777 778 if (can_sja_accept_filter(s, frame) == 0) { 779 s->status_pel &= ~(1 << 4); 780 if (DEBUG_FILTER) { 781 qemu_log("[cansja]: filter rejects message\n"); 782 } 783 return ret; 784 } 785 786 ret = frame2buff_pel(frame, rcv); 787 if (ret < 0) { 788 s->status_pel &= ~(1 << 4); 789 if (DEBUG_FILTER) { 790 qemu_log("[cansja]: message store failed\n"); 791 } 792 return ret; /* maybe not support now. */ 793 } 794 795 if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */ 796 s->status_pel |= (1 << 1); /* Overrun status */ 797 s->interrupt_pel |= (1 << 3); 798 s->status_pel &= ~(1 << 4); 799 if (DEBUG_FILTER) { 800 qemu_log("[cansja]: receive FIFO overrun\n"); 801 } 802 can_sja_update_pel_irq(s); 803 return ret; 804 } 805 s->rx_cnt += ret; 806 s->rxmsg_cnt++; 807 if (DEBUG_FILTER) { 808 qemu_log("[cansja]: message stored in receive FIFO\n"); 809 } 810 811 for (i = 0; i < ret; i++) { 812 s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] = rcv[i]; 813 } 814 s->rx_ptr %= SJA_RCV_BUF_LEN; /* update the pointer. */ 815 816 s->status_pel |= 0x01; /* Set the Receive Buffer Status. DS-p23 */ 817 s->interrupt_pel |= 0x01; 818 s->status_pel &= ~(1 << 4); 819 s->status_pel |= (1 << 0); 820 can_sja_update_pel_irq(s); 821 } else { /* BasicCAN mode */ 822 823 /* the CAN controller is receiving a message */ 824 s->status_bas |= (1 << 4); 825 826 ret = frame2buff_bas(frame, rcv); 827 if (ret < 0) { 828 s->status_bas &= ~(1 << 4); 829 if (DEBUG_FILTER) { 830 qemu_log("[cansja]: message store failed\n"); 831 } 832 return ret; /* maybe not support now. */ 833 } 834 835 if (s->rx_cnt + ret > SJA_RCV_BUF_LEN) { /* Data overrun. */ 836 s->status_bas |= (1 << 1); /* Overrun status */ 837 s->status_bas &= ~(1 << 4); 838 s->interrupt_bas |= (1 << 3); 839 can_sja_update_bas_irq(s); 840 if (DEBUG_FILTER) { 841 qemu_log("[cansja]: receive FIFO overrun\n"); 842 } 843 return ret; 844 } 845 s->rx_cnt += ret; 846 s->rxmsg_cnt++; 847 848 if (DEBUG_FILTER) { 849 qemu_log("[cansja]: message stored\n"); 850 } 851 852 for (i = 0; i < ret; i++) { 853 s->rx_buff[(s->rx_ptr++) % SJA_RCV_BUF_LEN] = rcv[i]; 854 } 855 s->rx_ptr %= SJA_RCV_BUF_LEN; /* update the pointer. */ 856 857 s->status_bas |= 0x01; /* Set the Receive Buffer Status. DS-p15 */ 858 s->status_bas &= ~(1 << 4); 859 s->interrupt_bas |= (1 << 0); 860 can_sja_update_bas_irq(s); 861 } 862 return 1; 863 } 864 865 static CanBusClientInfo can_sja_bus_client_info = { 866 .can_receive = can_sja_can_receive, 867 .receive = can_sja_receive, 868 }; 869 870 871 int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus) 872 { 873 s->bus_client.info = &can_sja_bus_client_info; 874 875 if (!bus) { 876 return -EINVAL; 877 } 878 879 if (can_bus_insert_client(bus, &s->bus_client) < 0) { 880 return -1; 881 } 882 883 return 0; 884 } 885 886 void can_sja_disconnect(CanSJA1000State *s) 887 { 888 can_bus_remove_client(&s->bus_client); 889 } 890 891 int can_sja_init(CanSJA1000State *s, qemu_irq irq) 892 { 893 s->irq = irq; 894 895 qemu_irq_lower(s->irq); 896 897 can_sja_hardware_reset(s); 898 899 return 0; 900 } 901 902 const VMStateDescription vmstate_qemu_can_filter = { 903 .name = "qemu_can_filter", 904 .version_id = 1, 905 .minimum_version_id = 1, 906 .minimum_version_id_old = 1, 907 .fields = (VMStateField[]) { 908 VMSTATE_UINT32(can_id, qemu_can_filter), 909 VMSTATE_UINT32(can_mask, qemu_can_filter), 910 VMSTATE_END_OF_LIST() 911 } 912 }; 913 914 static int can_sja_post_load(void *opaque, int version_id) 915 { 916 CanSJA1000State *s = opaque; 917 if (s->clock & 0x80) { /* PeliCAN Mode */ 918 can_sja_update_pel_irq(s); 919 } else { 920 can_sja_update_bas_irq(s); 921 } 922 return 0; 923 } 924 925 /* VMState is needed for live migration of QEMU images */ 926 const VMStateDescription vmstate_can_sja = { 927 .name = "can_sja", 928 .version_id = 1, 929 .minimum_version_id = 1, 930 .minimum_version_id_old = 1, 931 .post_load = can_sja_post_load, 932 .fields = (VMStateField[]) { 933 VMSTATE_UINT8(mode, CanSJA1000State), 934 935 VMSTATE_UINT8(status_pel, CanSJA1000State), 936 VMSTATE_UINT8(interrupt_pel, CanSJA1000State), 937 VMSTATE_UINT8(interrupt_en, CanSJA1000State), 938 VMSTATE_UINT8(rxmsg_cnt, CanSJA1000State), 939 VMSTATE_UINT8(rxbuf_start, CanSJA1000State), 940 VMSTATE_UINT8(clock, CanSJA1000State), 941 942 VMSTATE_BUFFER(code_mask, CanSJA1000State), 943 VMSTATE_BUFFER(tx_buff, CanSJA1000State), 944 945 VMSTATE_BUFFER(rx_buff, CanSJA1000State), 946 947 VMSTATE_UINT32(rx_ptr, CanSJA1000State), 948 VMSTATE_UINT32(rx_cnt, CanSJA1000State), 949 950 VMSTATE_UINT8(control, CanSJA1000State), 951 952 VMSTATE_UINT8(status_bas, CanSJA1000State), 953 VMSTATE_UINT8(interrupt_bas, CanSJA1000State), 954 VMSTATE_UINT8(code, CanSJA1000State), 955 VMSTATE_UINT8(mask, CanSJA1000State), 956 957 VMSTATE_STRUCT_ARRAY(filter, CanSJA1000State, 4, 0, 958 vmstate_qemu_can_filter, qemu_can_filter), 959 960 961 VMSTATE_END_OF_LIST() 962 } 963 }; 964