1 /* 2 * MIOe-3680 PCI CAN device (SJA1000 based) emulation 3 * 4 * Copyright (c) 2016 Deniz Eren (deniz.eren@icloud.com) 5 * 6 * Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by 7 * Jin Yang and Pavel Pisa 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/module.h" 30 #include "qapi/error.h" 31 #include "hw/irq.h" 32 #include "hw/pci/pci_device.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "net/can_emu.h" 36 37 #include "can_sja1000.h" 38 #include "qom/object.h" 39 40 #define TYPE_CAN_PCI_DEV "mioe3680_pci" 41 42 typedef struct Mioe3680PCIState Mioe3680PCIState; 43 DECLARE_INSTANCE_CHECKER(Mioe3680PCIState, MIOe3680_PCI_DEV, 44 TYPE_CAN_PCI_DEV) 45 46 /* the PCI device and vendor IDs */ 47 #ifndef MIOe3680_PCI_VENDOR_ID1 48 #define MIOe3680_PCI_VENDOR_ID1 0x13fe 49 #endif 50 51 #ifndef MIOe3680_PCI_DEVICE_ID1 52 #define MIOe3680_PCI_DEVICE_ID1 0xc302 53 #endif 54 55 #define MIOe3680_PCI_SJA_COUNT 2 56 #define MIOe3680_PCI_SJA_RANGE 0x400 57 58 #define MIOe3680_PCI_BYTES_PER_SJA 0x80 59 60 struct Mioe3680PCIState { 61 /*< private >*/ 62 PCIDevice dev; 63 /*< public >*/ 64 MemoryRegion sja_io[MIOe3680_PCI_SJA_COUNT]; 65 66 CanSJA1000State sja_state[MIOe3680_PCI_SJA_COUNT]; 67 qemu_irq irq; 68 69 char *model; /* The model that support, only SJA1000 now. */ 70 CanBusState *canbus[MIOe3680_PCI_SJA_COUNT]; 71 }; 72 73 static void mioe3680_pci_reset(DeviceState *dev) 74 { 75 Mioe3680PCIState *d = MIOe3680_PCI_DEV(dev); 76 int i; 77 78 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 79 can_sja_hardware_reset(&d->sja_state[i]); 80 } 81 } 82 83 static uint64_t mioe3680_pci_sja1_io_read(void *opaque, hwaddr addr, 84 unsigned size) 85 { 86 Mioe3680PCIState *d = opaque; 87 CanSJA1000State *s = &d->sja_state[0]; 88 89 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 90 return 0; 91 } 92 93 return can_sja_mem_read(s, addr >> 2, size); 94 } 95 96 static void mioe3680_pci_sja1_io_write(void *opaque, hwaddr addr, uint64_t data, 97 unsigned size) 98 { 99 Mioe3680PCIState *d = opaque; 100 CanSJA1000State *s = &d->sja_state[0]; 101 102 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 103 return; 104 } 105 106 can_sja_mem_write(s, addr >> 2, data, size); 107 } 108 109 static uint64_t mioe3680_pci_sja2_io_read(void *opaque, hwaddr addr, 110 unsigned size) 111 { 112 Mioe3680PCIState *d = opaque; 113 CanSJA1000State *s = &d->sja_state[1]; 114 115 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 116 return 0; 117 } 118 119 return can_sja_mem_read(s, addr >> 2, size); 120 } 121 122 static void mioe3680_pci_sja2_io_write(void *opaque, hwaddr addr, uint64_t data, 123 unsigned size) 124 { 125 Mioe3680PCIState *d = opaque; 126 CanSJA1000State *s = &d->sja_state[1]; 127 128 if (addr >= MIOe3680_PCI_BYTES_PER_SJA) { 129 return; 130 } 131 132 can_sja_mem_write(s, addr >> 2, data, size); 133 } 134 135 static const MemoryRegionOps mioe3680_pci_sja1_io_ops = { 136 .read = mioe3680_pci_sja1_io_read, 137 .write = mioe3680_pci_sja1_io_write, 138 .endianness = DEVICE_LITTLE_ENDIAN, 139 .impl = { 140 .max_access_size = 1, 141 }, 142 }; 143 144 static const MemoryRegionOps mioe3680_pci_sja2_io_ops = { 145 .read = mioe3680_pci_sja2_io_read, 146 .write = mioe3680_pci_sja2_io_write, 147 .endianness = DEVICE_LITTLE_ENDIAN, 148 .impl = { 149 .max_access_size = 1, 150 }, 151 }; 152 153 static void mioe3680_pci_realize(PCIDevice *pci_dev, Error **errp) 154 { 155 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); 156 uint8_t *pci_conf; 157 int i; 158 159 pci_conf = pci_dev->config; 160 pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 161 162 d->irq = pci_allocate_irq(&d->dev); 163 164 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 165 can_sja_init(&d->sja_state[i], d->irq); 166 } 167 168 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 169 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) { 170 error_setg(errp, "can_sja_connect_to_bus failed"); 171 return; 172 } 173 } 174 175 memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_ops, 176 d, "mioe3680_pci-sja1", MIOe3680_PCI_SJA_RANGE); 177 memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_ops, 178 d, "mioe3680_pci-sja2", MIOe3680_PCI_SJA_RANGE); 179 180 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 181 pci_register_bar(&d->dev, /*BAR*/ i, PCI_BASE_ADDRESS_SPACE_IO, 182 &d->sja_io[i]); 183 } 184 } 185 186 static void mioe3680_pci_exit(PCIDevice *pci_dev) 187 { 188 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); 189 int i; 190 191 for (i = 0 ; i < MIOe3680_PCI_SJA_COUNT; i++) { 192 can_sja_disconnect(&d->sja_state[i]); 193 } 194 195 qemu_free_irq(d->irq); 196 } 197 198 static const VMStateDescription vmstate_mioe3680_pci = { 199 .name = "mioe3680_pci", 200 .version_id = 1, 201 .minimum_version_id = 1, 202 .fields = (const VMStateField[]) { 203 VMSTATE_PCI_DEVICE(dev, Mioe3680PCIState), 204 VMSTATE_STRUCT(sja_state[0], Mioe3680PCIState, 0, vmstate_can_sja, 205 CanSJA1000State), 206 VMSTATE_STRUCT(sja_state[1], Mioe3680PCIState, 0, vmstate_can_sja, 207 CanSJA1000State), 208 VMSTATE_END_OF_LIST() 209 } 210 }; 211 212 static void mioe3680_pci_instance_init(Object *obj) 213 { 214 Mioe3680PCIState *d = MIOe3680_PCI_DEV(obj); 215 216 object_property_add_link(obj, "canbus0", TYPE_CAN_BUS, 217 (Object **)&d->canbus[0], 218 qdev_prop_allow_set_link_before_realize, 219 0); 220 object_property_add_link(obj, "canbus1", TYPE_CAN_BUS, 221 (Object **)&d->canbus[1], 222 qdev_prop_allow_set_link_before_realize, 223 0); 224 } 225 226 static void mioe3680_pci_class_init(ObjectClass *klass, void *data) 227 { 228 DeviceClass *dc = DEVICE_CLASS(klass); 229 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 230 231 k->realize = mioe3680_pci_realize; 232 k->exit = mioe3680_pci_exit; 233 k->vendor_id = MIOe3680_PCI_VENDOR_ID1; 234 k->device_id = MIOe3680_PCI_DEVICE_ID1; 235 k->revision = 0x00; 236 k->class_id = 0x000c09; 237 k->subsystem_vendor_id = MIOe3680_PCI_VENDOR_ID1; 238 k->subsystem_id = MIOe3680_PCI_DEVICE_ID1; 239 dc->desc = "Mioe3680 PCICANx"; 240 dc->vmsd = &vmstate_mioe3680_pci; 241 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 242 device_class_set_legacy_reset(dc, mioe3680_pci_reset); 243 } 244 245 static const TypeInfo mioe3680_pci_info = { 246 .name = TYPE_CAN_PCI_DEV, 247 .parent = TYPE_PCI_DEVICE, 248 .instance_size = sizeof(Mioe3680PCIState), 249 .class_init = mioe3680_pci_class_init, 250 .instance_init = mioe3680_pci_instance_init, 251 .interfaces = (InterfaceInfo[]) { 252 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 253 { }, 254 }, 255 }; 256 257 static void mioe3680_pci_register_types(void) 258 { 259 type_register_static(&mioe3680_pci_info); 260 } 261 262 type_init(mioe3680_pci_register_types) 263