1*870c034dSAlistair Francis /* 2*870c034dSAlistair Francis * STM32F4xx SYSCFG 3*870c034dSAlistair Francis * 4*870c034dSAlistair Francis * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5*870c034dSAlistair Francis * 6*870c034dSAlistair Francis * Permission is hereby granted, free of charge, to any person obtaining a copy 7*870c034dSAlistair Francis * of this software and associated documentation files (the "Software"), to deal 8*870c034dSAlistair Francis * in the Software without restriction, including without limitation the rights 9*870c034dSAlistair Francis * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10*870c034dSAlistair Francis * copies of the Software, and to permit persons to whom the Software is 11*870c034dSAlistair Francis * furnished to do so, subject to the following conditions: 12*870c034dSAlistair Francis * 13*870c034dSAlistair Francis * The above copyright notice and this permission notice shall be included in 14*870c034dSAlistair Francis * all copies or substantial portions of the Software. 15*870c034dSAlistair Francis * 16*870c034dSAlistair Francis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17*870c034dSAlistair Francis * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*870c034dSAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*870c034dSAlistair Francis * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20*870c034dSAlistair Francis * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21*870c034dSAlistair Francis * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22*870c034dSAlistair Francis * THE SOFTWARE. 23*870c034dSAlistair Francis */ 24*870c034dSAlistair Francis 25*870c034dSAlistair Francis #include "qemu/osdep.h" 26*870c034dSAlistair Francis #include "qemu/log.h" 27*870c034dSAlistair Francis #include "trace.h" 28*870c034dSAlistair Francis #include "hw/irq.h" 29*870c034dSAlistair Francis #include "migration/vmstate.h" 30*870c034dSAlistair Francis #include "hw/misc/stm32f4xx_syscfg.h" 31*870c034dSAlistair Francis 32*870c034dSAlistair Francis static void stm32f4xx_syscfg_reset(DeviceState *dev) 33*870c034dSAlistair Francis { 34*870c034dSAlistair Francis STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev); 35*870c034dSAlistair Francis 36*870c034dSAlistair Francis s->syscfg_memrmp = 0x00000000; 37*870c034dSAlistair Francis s->syscfg_pmc = 0x00000000; 38*870c034dSAlistair Francis s->syscfg_exticr[0] = 0x00000000; 39*870c034dSAlistair Francis s->syscfg_exticr[1] = 0x00000000; 40*870c034dSAlistair Francis s->syscfg_exticr[2] = 0x00000000; 41*870c034dSAlistair Francis s->syscfg_exticr[3] = 0x00000000; 42*870c034dSAlistair Francis s->syscfg_cmpcr = 0x00000000; 43*870c034dSAlistair Francis } 44*870c034dSAlistair Francis 45*870c034dSAlistair Francis static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level) 46*870c034dSAlistair Francis { 47*870c034dSAlistair Francis STM32F4xxSyscfgState *s = opaque; 48*870c034dSAlistair Francis int icrreg = irq / 4; 49*870c034dSAlistair Francis int startbit = (irq & 3) * 4; 50*870c034dSAlistair Francis uint8_t config = config = irq / 16; 51*870c034dSAlistair Francis 52*870c034dSAlistair Francis trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level); 53*870c034dSAlistair Francis 54*870c034dSAlistair Francis g_assert(icrreg < SYSCFG_NUM_EXTICR); 55*870c034dSAlistair Francis 56*870c034dSAlistair Francis if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) { 57*870c034dSAlistair Francis qemu_set_irq(s->gpio_out[irq], level); 58*870c034dSAlistair Francis trace_stm32f4xx_pulse_exti(irq); 59*870c034dSAlistair Francis } 60*870c034dSAlistair Francis } 61*870c034dSAlistair Francis 62*870c034dSAlistair Francis static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr, 63*870c034dSAlistair Francis unsigned int size) 64*870c034dSAlistair Francis { 65*870c034dSAlistair Francis STM32F4xxSyscfgState *s = opaque; 66*870c034dSAlistair Francis 67*870c034dSAlistair Francis trace_stm32f4xx_syscfg_read(addr); 68*870c034dSAlistair Francis 69*870c034dSAlistair Francis switch (addr) { 70*870c034dSAlistair Francis case SYSCFG_MEMRMP: 71*870c034dSAlistair Francis return s->syscfg_memrmp; 72*870c034dSAlistair Francis case SYSCFG_PMC: 73*870c034dSAlistair Francis return s->syscfg_pmc; 74*870c034dSAlistair Francis case SYSCFG_EXTICR1...SYSCFG_EXTICR4: 75*870c034dSAlistair Francis return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4]; 76*870c034dSAlistair Francis case SYSCFG_CMPCR: 77*870c034dSAlistair Francis return s->syscfg_cmpcr; 78*870c034dSAlistair Francis default: 79*870c034dSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 80*870c034dSAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 81*870c034dSAlistair Francis return 0; 82*870c034dSAlistair Francis } 83*870c034dSAlistair Francis } 84*870c034dSAlistair Francis 85*870c034dSAlistair Francis static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr, 86*870c034dSAlistair Francis uint64_t val64, unsigned int size) 87*870c034dSAlistair Francis { 88*870c034dSAlistair Francis STM32F4xxSyscfgState *s = opaque; 89*870c034dSAlistair Francis uint32_t value = val64; 90*870c034dSAlistair Francis 91*870c034dSAlistair Francis trace_stm32f4xx_syscfg_write(value, addr); 92*870c034dSAlistair Francis 93*870c034dSAlistair Francis switch (addr) { 94*870c034dSAlistair Francis case SYSCFG_MEMRMP: 95*870c034dSAlistair Francis qemu_log_mask(LOG_UNIMP, 96*870c034dSAlistair Francis "%s: Changing the memory mapping isn't supported " \ 97*870c034dSAlistair Francis "in QEMU\n", __func__); 98*870c034dSAlistair Francis return; 99*870c034dSAlistair Francis case SYSCFG_PMC: 100*870c034dSAlistair Francis qemu_log_mask(LOG_UNIMP, 101*870c034dSAlistair Francis "%s: Changing the memory mapping isn't supported " \ 102*870c034dSAlistair Francis "in QEMU\n", __func__); 103*870c034dSAlistair Francis return; 104*870c034dSAlistair Francis case SYSCFG_EXTICR1...SYSCFG_EXTICR4: 105*870c034dSAlistair Francis s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF); 106*870c034dSAlistair Francis return; 107*870c034dSAlistair Francis case SYSCFG_CMPCR: 108*870c034dSAlistair Francis s->syscfg_cmpcr = value; 109*870c034dSAlistair Francis return; 110*870c034dSAlistair Francis default: 111*870c034dSAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, 112*870c034dSAlistair Francis "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr); 113*870c034dSAlistair Francis } 114*870c034dSAlistair Francis } 115*870c034dSAlistair Francis 116*870c034dSAlistair Francis static const MemoryRegionOps stm32f4xx_syscfg_ops = { 117*870c034dSAlistair Francis .read = stm32f4xx_syscfg_read, 118*870c034dSAlistair Francis .write = stm32f4xx_syscfg_write, 119*870c034dSAlistair Francis .endianness = DEVICE_NATIVE_ENDIAN, 120*870c034dSAlistair Francis }; 121*870c034dSAlistair Francis 122*870c034dSAlistair Francis static void stm32f4xx_syscfg_init(Object *obj) 123*870c034dSAlistair Francis { 124*870c034dSAlistair Francis STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj); 125*870c034dSAlistair Francis 126*870c034dSAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 127*870c034dSAlistair Francis 128*870c034dSAlistair Francis memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s, 129*870c034dSAlistair Francis TYPE_STM32F4XX_SYSCFG, 0x400); 130*870c034dSAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 131*870c034dSAlistair Francis 132*870c034dSAlistair Francis qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9); 133*870c034dSAlistair Francis qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16); 134*870c034dSAlistair Francis } 135*870c034dSAlistair Francis 136*870c034dSAlistair Francis static const VMStateDescription vmstate_stm32f4xx_syscfg = { 137*870c034dSAlistair Francis .name = TYPE_STM32F4XX_SYSCFG, 138*870c034dSAlistair Francis .version_id = 1, 139*870c034dSAlistair Francis .minimum_version_id = 1, 140*870c034dSAlistair Francis .fields = (VMStateField[]) { 141*870c034dSAlistair Francis VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState), 142*870c034dSAlistair Francis VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState), 143*870c034dSAlistair Francis VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState, 144*870c034dSAlistair Francis SYSCFG_NUM_EXTICR), 145*870c034dSAlistair Francis VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState), 146*870c034dSAlistair Francis VMSTATE_END_OF_LIST() 147*870c034dSAlistair Francis } 148*870c034dSAlistair Francis }; 149*870c034dSAlistair Francis 150*870c034dSAlistair Francis static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data) 151*870c034dSAlistair Francis { 152*870c034dSAlistair Francis DeviceClass *dc = DEVICE_CLASS(klass); 153*870c034dSAlistair Francis 154*870c034dSAlistair Francis dc->reset = stm32f4xx_syscfg_reset; 155*870c034dSAlistair Francis dc->vmsd = &vmstate_stm32f4xx_syscfg; 156*870c034dSAlistair Francis } 157*870c034dSAlistair Francis 158*870c034dSAlistair Francis static const TypeInfo stm32f4xx_syscfg_info = { 159*870c034dSAlistair Francis .name = TYPE_STM32F4XX_SYSCFG, 160*870c034dSAlistair Francis .parent = TYPE_SYS_BUS_DEVICE, 161*870c034dSAlistair Francis .instance_size = sizeof(STM32F4xxSyscfgState), 162*870c034dSAlistair Francis .instance_init = stm32f4xx_syscfg_init, 163*870c034dSAlistair Francis .class_init = stm32f4xx_syscfg_class_init, 164*870c034dSAlistair Francis }; 165*870c034dSAlistair Francis 166*870c034dSAlistair Francis static void stm32f4xx_syscfg_register_types(void) 167*870c034dSAlistair Francis { 168*870c034dSAlistair Francis type_register_static(&stm32f4xx_syscfg_info); 169*870c034dSAlistair Francis } 170*870c034dSAlistair Francis 171*870c034dSAlistair Francis type_init(stm32f4xx_syscfg_register_types) 172