1 /* 2 * QEMU SiFive Test Finisher 3 * 4 * Copyright (c) 2018 SiFive, Inc. 5 * 6 * Test finisher memory mapped device used to exit simulation 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/sysbus.h" 23 #include "qemu/module.h" 24 #include "target/riscv/cpu.h" 25 #include "hw/riscv/sifive_test.h" 26 27 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size) 28 { 29 return 0; 30 } 31 32 static void sifive_test_write(void *opaque, hwaddr addr, 33 uint64_t val64, unsigned int size) 34 { 35 if (addr == 0) { 36 int status = val64 & 0xffff; 37 int code = (val64 >> 16) & 0xffff; 38 switch (status) { 39 case FINISHER_FAIL: 40 exit(code); 41 case FINISHER_PASS: 42 exit(0); 43 default: 44 break; 45 } 46 } 47 hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n", 48 __func__, (int)addr, val64); 49 } 50 51 static const MemoryRegionOps sifive_test_ops = { 52 .read = sifive_test_read, 53 .write = sifive_test_write, 54 .endianness = DEVICE_NATIVE_ENDIAN, 55 .valid = { 56 .min_access_size = 4, 57 .max_access_size = 4 58 } 59 }; 60 61 static void sifive_test_init(Object *obj) 62 { 63 SiFiveTestState *s = SIFIVE_TEST(obj); 64 65 memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s, 66 TYPE_SIFIVE_TEST, 0x1000); 67 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); 68 } 69 70 static const TypeInfo sifive_test_info = { 71 .name = TYPE_SIFIVE_TEST, 72 .parent = TYPE_SYS_BUS_DEVICE, 73 .instance_size = sizeof(SiFiveTestState), 74 .instance_init = sifive_test_init, 75 }; 76 77 static void sifive_test_register_types(void) 78 { 79 type_register_static(&sifive_test_info); 80 } 81 82 type_init(sifive_test_register_types) 83 84 85 /* 86 * Create Test device. 87 */ 88 DeviceState *sifive_test_create(hwaddr addr) 89 { 90 DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_TEST); 91 qdev_init_nofail(dev); 92 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); 93 return dev; 94 } 95